Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless-next-2.6 into for-davem

Conflicts:
	drivers/net/wireless/libertas_tf/cmd.c
	drivers/net/wireless/libertas_tf/main.c

6 files changed, 159 insertions, 129 deletions

diff --git a/include/linux/nl80211.h b/include/linux/nl80211.h
index 2ea3edeee7aa..f8750f9a65b8 100644
--- a/include/linux/nl80211.h
+++ b/include/linux/nl80211.h
@@ -709,6 +709,9 @@ enum nl80211_commands {
  *      NL80211_CMD_AUTHENTICATE, NL80211_CMD_DEAUTHENTICATE,
  *      NL80211_CMD_DISASSOCIATE.
  *
+ * @NL80211_ATTR_AP_ISOLATE: (AP mode) Do not forward traffic between stations
+ *      connected to this BSS.
+ *
  * @NL80211_ATTR_MAX: highest attribute number currently defined
  * @__NL80211_ATTR_AFTER_LAST: internal use
  */
@@ -864,6 +867,8 @@ enum nl80211_attrs {
 
         NL80211_ATTR_LOCAL_STATE_CHANGE,
 
+        NL80211_ATTR_AP_ISOLATE,
+
         /* add attributes here, update the policy in nl80211.c */
 
         __NL80211_ATTR_AFTER_LAST,
diff --git a/include/linux/ssb/ssb.h b/include/linux/ssb/ssb.h
index 24f988547361..a2608bff9c78 100644
--- a/include/linux/ssb/ssb.h
+++ b/include/linux/ssb/ssb.h
@@ -305,6 +305,7 @@ struct ssb_bus {
         /* ID information about the Chip. */
         u16 chip_id;
         u16 chip_rev;
+        u16 sprom_offset;
         u16 sprom_size;         /* number of words in sprom */
         u8 chip_package;
 
@@ -394,6 +395,9 @@ extern int ssb_bus_sdiobus_register(struct ssb_bus *bus,
 
 extern void ssb_bus_unregister(struct ssb_bus *bus);
 
+/* Does the device have an SPROM? */
+extern bool ssb_is_sprom_available(struct ssb_bus *bus);
+
 /* Set a fallback SPROM.
  * See kdoc at the function definition for complete documentation. */
 extern int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom);
diff --git a/include/linux/ssb/ssb_driver_chipcommon.h b/include/linux/ssb/ssb_driver_chipcommon.h
index 4e27acf0a92f..2cdf249b4e5f 100644
--- a/include/linux/ssb/ssb_driver_chipcommon.h
+++ b/include/linux/ssb/ssb_driver_chipcommon.h
@@ -53,6 +53,7 @@
 #define  SSB_CHIPCO_CAP_64BIT           0x08000000      /* 64-bit Backplane */
 #define  SSB_CHIPCO_CAP_PMU             0x10000000      /* PMU available (rev >= 20) */
 #define  SSB_CHIPCO_CAP_ECI             0x20000000      /* ECI available (rev >= 20) */
+#define  SSB_CHIPCO_CAP_SPROM           0x40000000      /* SPROM present */
 #define SSB_CHIPCO_CORECTL              0x0008
 #define  SSB_CHIPCO_CORECTL_UARTCLK0    0x00000001      /* Drive UART with internal clock */
 #define  SSB_CHIPCO_CORECTL_SE          0x00000002      /* sync clk out enable (corerev >= 3) */
@@ -385,6 +386,7 @@
 
 
 /** Chip specific Chip-Status register contents. */
+#define SSB_CHIPCO_CHST_4322_SPROM_EXISTS       0x00000040 /* SPROM present */
 #define SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL      0x00000003
 #define SSB_CHIPCO_CHST_4325_DEFCIS_SEL         0 /* OTP is powered up, use def. CIS, no SPROM */
 #define SSB_CHIPCO_CHST_4325_SPROM_SEL          1 /* OTP is powered up, SPROM is present */
@@ -398,6 +400,18 @@
 #define SSB_CHIPCO_CHST_4325_RCAL_VALUE_SHIFT   4
 #define SSB_CHIPCO_CHST_4325_PMUTOP_2B          0x00000200 /* 1 for 2b, 0 for to 2a */
 
+/** Macros to determine SPROM presence based on Chip-Status register. */
+#define SSB_CHIPCO_CHST_4312_SPROM_PRESENT(status) \
+        ((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
+                SSB_CHIPCO_CHST_4325_OTP_SEL)
+#define SSB_CHIPCO_CHST_4322_SPROM_PRESENT(status) \
+        (status & SSB_CHIPCO_CHST_4322_SPROM_EXISTS)
+#define SSB_CHIPCO_CHST_4325_SPROM_PRESENT(status) \
+        (((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
+                SSB_CHIPCO_CHST_4325_DEFCIS_SEL) && \
+         ((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
+                SSB_CHIPCO_CHST_4325_OTP_SEL))
+
 
 
 /** Clockcontrol masks and values **/
@@ -564,6 +578,7 @@ struct ssb_chipcommon_pmu {
 struct ssb_chipcommon {
         struct ssb_device *dev;
         u32 capabilities;
+        u32 status;
         /* Fast Powerup Delay constant */
         u16 fast_pwrup_delay;
         struct ssb_chipcommon_pmu pmu;
diff --git a/include/linux/ssb/ssb_regs.h b/include/linux/ssb/ssb_regs.h
index 9ae9082eaeb4..a6d5225b9275 100644
--- a/include/linux/ssb/ssb_regs.h
+++ b/include/linux/ssb/ssb_regs.h
@@ -170,26 +170,27 @@
 #define SSB_SPROMSIZE_WORDS_R4          220
 #define SSB_SPROMSIZE_BYTES_R123        (SSB_SPROMSIZE_WORDS_R123 * sizeof(u16))
 #define SSB_SPROMSIZE_BYTES_R4          (SSB_SPROMSIZE_WORDS_R4 * sizeof(u16))
-#define SSB_SPROM_BASE                  0x1000
-#define SSB_SPROM_REVISION              0x107E
+#define SSB_SPROM_BASE1                 0x1000
+#define SSB_SPROM_BASE31                0x0800
+#define SSB_SPROM_REVISION              0x007E
 #define  SSB_SPROM_REVISION_REV         0x00FF  /* SPROM Revision number */
 #define  SSB_SPROM_REVISION_CRC         0xFF00  /* SPROM CRC8 value */
 #define  SSB_SPROM_REVISION_CRC_SHIFT   8
 
 /* SPROM Revision 1 */
-#define SSB_SPROM1_SPID                 0x1004  /* Subsystem Product ID for PCI */
-#define SSB_SPROM1_SVID                 0x1006  /* Subsystem Vendor ID for PCI */
-#define SSB_SPROM1_PID                  0x1008  /* Product ID for PCI */
-#define SSB_SPROM1_IL0MAC               0x1048  /* 6 bytes MAC address for 802.11b/g */
-#define SSB_SPROM1_ET0MAC               0x104E  /* 6 bytes MAC address for Ethernet */
-#define SSB_SPROM1_ET1MAC               0x1054  /* 6 bytes MAC address for 802.11a */
-#define SSB_SPROM1_ETHPHY               0x105A  /* Ethernet PHY settings */
+#define SSB_SPROM1_SPID                 0x0004  /* Subsystem Product ID for PCI */
+#define SSB_SPROM1_SVID                 0x0006  /* Subsystem Vendor ID for PCI */
+#define SSB_SPROM1_PID                  0x0008  /* Product ID for PCI */
+#define SSB_SPROM1_IL0MAC               0x0048  /* 6 bytes MAC address for 802.11b/g */
+#define SSB_SPROM1_ET0MAC               0x004E  /* 6 bytes MAC address for Ethernet */
+#define SSB_SPROM1_ET1MAC               0x0054  /* 6 bytes MAC address for 802.11a */
+#define SSB_SPROM1_ETHPHY               0x005A  /* Ethernet PHY settings */
 #define  SSB_SPROM1_ETHPHY_ET0A         0x001F  /* MII Address for enet0 */
 #define  SSB_SPROM1_ETHPHY_ET1A         0x03E0  /* MII Address for enet1 */
 #define  SSB_SPROM1_ETHPHY_ET1A_SHIFT   5
 #define  SSB_SPROM1_ETHPHY_ET0M         (1<<14) /* MDIO for enet0 */
 #define  SSB_SPROM1_ETHPHY_ET1M         (1<<15) /* MDIO for enet1 */
-#define SSB_SPROM1_BINF                 0x105C  /* Board info */
+#define SSB_SPROM1_BINF                 0x005C  /* Board info */
 #define  SSB_SPROM1_BINF_BREV           0x00FF  /* Board Revision */
 #define  SSB_SPROM1_BINF_CCODE          0x0F00  /* Country Code */
 #define  SSB_SPROM1_BINF_CCODE_SHIFT    8
@@ -197,63 +198,63 @@
 #define  SSB_SPROM1_BINF_ANTBG_SHIFT    12
 #define  SSB_SPROM1_BINF_ANTA           0xC000  /* Available A-PHY antennas */
 #define  SSB_SPROM1_BINF_ANTA_SHIFT     14
-#define SSB_SPROM1_PA0B0                0x105E
-#define SSB_SPROM1_PA0B1                0x1060
-#define SSB_SPROM1_PA0B2                0x1062
-#define SSB_SPROM1_GPIOA                0x1064  /* General Purpose IO pins 0 and 1 */
+#define SSB_SPROM1_PA0B0                0x005E
+#define SSB_SPROM1_PA0B1                0x0060
+#define SSB_SPROM1_PA0B2                0x0062
+#define SSB_SPROM1_GPIOA                0x0064  /* General Purpose IO pins 0 and 1 */
 #define  SSB_SPROM1_GPIOA_P0            0x00FF  /* Pin 0 */
 #define  SSB_SPROM1_GPIOA_P1            0xFF00  /* Pin 1 */
 #define  SSB_SPROM1_GPIOA_P1_SHIFT      8
-#define SSB_SPROM1_GPIOB                0x1066  /* General Purpuse IO pins 2 and 3 */
+#define SSB_SPROM1_GPIOB                0x0066  /* General Purpuse IO pins 2 and 3 */
 #define  SSB_SPROM1_GPIOB_P2            0x00FF  /* Pin 2 */
 #define  SSB_SPROM1_GPIOB_P3            0xFF00  /* Pin 3 */
 #define  SSB_SPROM1_GPIOB_P3_SHIFT      8
-#define SSB_SPROM1_MAXPWR               0x1068  /* Power Amplifier Max Power */
+#define SSB_SPROM1_MAXPWR               0x0068  /* Power Amplifier Max Power */
 #define  SSB_SPROM1_MAXPWR_BG           0x00FF  /* B-PHY and G-PHY (in dBm Q5.2) */
 #define  SSB_SPROM1_MAXPWR_A            0xFF00  /* A-PHY (in dBm Q5.2) */
 #define  SSB_SPROM1_MAXPWR_A_SHIFT      8
-#define SSB_SPROM1_PA1B0                0x106A
-#define SSB_SPROM1_PA1B1                0x106C
-#define SSB_SPROM1_PA1B2                0x106E
-#define SSB_SPROM1_ITSSI                0x1070  /* Idle TSSI Target */
+#define SSB_SPROM1_PA1B0                0x006A
+#define SSB_SPROM1_PA1B1                0x006C
+#define SSB_SPROM1_PA1B2                0x006E
+#define SSB_SPROM1_ITSSI                0x0070  /* Idle TSSI Target */
 #define  SSB_SPROM1_ITSSI_BG            0x00FF  /* B-PHY and G-PHY*/
 #define  SSB_SPROM1_ITSSI_A             0xFF00  /* A-PHY */
 #define  SSB_SPROM1_ITSSI_A_SHIFT       8
-#define SSB_SPROM1_BFLLO                0x1072  /* Boardflags (low 16 bits) */
-#define SSB_SPROM1_AGAIN                0x1074  /* Antenna Gain (in dBm Q5.2) */
+#define SSB_SPROM1_BFLLO                0x0072  /* Boardflags (low 16 bits) */
+#define SSB_SPROM1_AGAIN                0x0074  /* Antenna Gain (in dBm Q5.2) */
 #define  SSB_SPROM1_AGAIN_BG            0x00FF  /* B-PHY and G-PHY */
 #define  SSB_SPROM1_AGAIN_BG_SHIFT      0
 #define  SSB_SPROM1_AGAIN_A             0xFF00  /* A-PHY */
 #define  SSB_SPROM1_AGAIN_A_SHIFT       8
 
 /* SPROM Revision 2 (inherits from rev 1) */
-#define SSB_SPROM2_BFLHI                0x1038  /* Boardflags (high 16 bits) */
-#define SSB_SPROM2_MAXP_A               0x103A  /* A-PHY Max Power */
+#define SSB_SPROM2_BFLHI                0x0038  /* Boardflags (high 16 bits) */
+#define SSB_SPROM2_MAXP_A               0x003A  /* A-PHY Max Power */
 #define  SSB_SPROM2_MAXP_A_HI           0x00FF  /* Max Power High */
 #define  SSB_SPROM2_MAXP_A_LO           0xFF00  /* Max Power Low */
 #define  SSB_SPROM2_MAXP_A_LO_SHIFT     8
-#define SSB_SPROM2_PA1LOB0              0x103C  /* A-PHY PowerAmplifier Low Settings */
-#define SSB_SPROM2_PA1LOB1              0x103E  /* A-PHY PowerAmplifier Low Settings */
-#define SSB_SPROM2_PA1LOB2              0x1040  /* A-PHY PowerAmplifier Low Settings */
-#define SSB_SPROM2_PA1HIB0              0x1042  /* A-PHY PowerAmplifier High Settings */
-#define SSB_SPROM2_PA1HIB1              0x1044  /* A-PHY PowerAmplifier High Settings */
-#define SSB_SPROM2_PA1HIB2              0x1046  /* A-PHY PowerAmplifier High Settings */
-#define SSB_SPROM2_OPO                  0x1078  /* OFDM Power Offset from CCK Level */
+#define SSB_SPROM2_PA1LOB0              0x003C  /* A-PHY PowerAmplifier Low Settings */
+#define SSB_SPROM2_PA1LOB1              0x003E  /* A-PHY PowerAmplifier Low Settings */
+#define SSB_SPROM2_PA1LOB2              0x0040  /* A-PHY PowerAmplifier Low Settings */
+#define SSB_SPROM2_PA1HIB0              0x0042  /* A-PHY PowerAmplifier High Settings */
+#define SSB_SPROM2_PA1HIB1              0x0044  /* A-PHY PowerAmplifier High Settings */
+#define SSB_SPROM2_PA1HIB2              0x0046  /* A-PHY PowerAmplifier High Settings */
+#define SSB_SPROM2_OPO                  0x0078  /* OFDM Power Offset from CCK Level */
 #define  SSB_SPROM2_OPO_VALUE           0x00FF
 #define  SSB_SPROM2_OPO_UNUSED          0xFF00
-#define SSB_SPROM2_CCODE                0x107C  /* Two char Country Code */
+#define SSB_SPROM2_CCODE                0x007C  /* Two char Country Code */
 
 /* SPROM Revision 3 (inherits most data from rev 2) */
-#define SSB_SPROM3_IL0MAC               0x104A  /* 6 bytes MAC address for 802.11b/g */
-#define SSB_SPROM3_OFDMAPO              0x102C  /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
-#define SSB_SPROM3_OFDMALPO             0x1030  /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
-#define SSB_SPROM3_OFDMAHPO             0x1034  /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
-#define SSB_SPROM3_GPIOLDC              0x1042  /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
+#define SSB_SPROM3_OFDMAPO              0x002C  /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
+#define SSB_SPROM3_OFDMALPO             0x0030  /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
+#define SSB_SPROM3_OFDMAHPO             0x0034  /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
+#define SSB_SPROM3_GPIOLDC              0x0042  /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
 #define  SSB_SPROM3_GPIOLDC_OFF         0x0000FF00      /* Off Count */
 #define  SSB_SPROM3_GPIOLDC_OFF_SHIFT   8
 #define  SSB_SPROM3_GPIOLDC_ON          0x00FF0000      /* On Count */
 #define  SSB_SPROM3_GPIOLDC_ON_SHIFT    16
-#define SSB_SPROM3_CCKPO                0x1078  /* CCK Power Offset */
+#define SSB_SPROM3_IL0MAC               0x004A  /* 6 bytes MAC address for 802.11b/g */
+#define SSB_SPROM3_CCKPO                0x0078  /* CCK Power Offset */
 #define  SSB_SPROM3_CCKPO_1M            0x000F  /* 1M Rate PO */
 #define  SSB_SPROM3_CCKPO_2M            0x00F0  /* 2M Rate PO */
 #define  SSB_SPROM3_CCKPO_2M_SHIFT      4
@@ -264,100 +265,100 @@
 #define  SSB_SPROM3_OFDMGPO             0x107A  /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */
 
 /* SPROM Revision 4 */
-#define SSB_SPROM4_IL0MAC               0x104C  /* 6 byte MAC address for a/b/g/n */
-#define SSB_SPROM4_ETHPHY               0x105A  /* Ethernet PHY settings ?? */
+#define SSB_SPROM4_BFLLO                0x0044  /* Boardflags (low 16 bits) */
+#define SSB_SPROM4_BFLHI                0x0046  /* Board Flags Hi */
+#define SSB_SPROM4_IL0MAC               0x004C  /* 6 byte MAC address for a/b/g/n */
+#define SSB_SPROM4_CCODE                0x0052  /* Country Code (2 bytes) */
+#define SSB_SPROM4_GPIOA                0x0056  /* Gen. Purpose IO # 0 and 1 */
+#define  SSB_SPROM4_GPIOA_P0            0x00FF  /* Pin 0 */
+#define  SSB_SPROM4_GPIOA_P1            0xFF00  /* Pin 1 */
+#define  SSB_SPROM4_GPIOA_P1_SHIFT      8
+#define SSB_SPROM4_GPIOB                0x0058  /* Gen. Purpose IO # 2 and 3 */
+#define  SSB_SPROM4_GPIOB_P2            0x00FF  /* Pin 2 */
+#define  SSB_SPROM4_GPIOB_P3            0xFF00  /* Pin 3 */
+#define  SSB_SPROM4_GPIOB_P3_SHIFT      8
+#define SSB_SPROM4_ETHPHY               0x005A  /* Ethernet PHY settings ?? */
 #define  SSB_SPROM4_ETHPHY_ET0A         0x001F  /* MII Address for enet0 */
 #define  SSB_SPROM4_ETHPHY_ET1A         0x03E0  /* MII Address for enet1 */
 #define  SSB_SPROM4_ETHPHY_ET1A_SHIFT   5
 #define  SSB_SPROM4_ETHPHY_ET0M         (1<<14) /* MDIO for enet0 */
 #define  SSB_SPROM4_ETHPHY_ET1M         (1<<15) /* MDIO for enet1 */
-#define SSB_SPROM4_CCODE                0x1052  /* Country Code (2 bytes) */
-#define SSB_SPROM4_ANTAVAIL             0x105D  /* Antenna available bitfields */
-#define SSB_SPROM4_ANTAVAIL_A           0x00FF  /* A-PHY bitfield */
-#define SSB_SPROM4_ANTAVAIL_A_SHIFT     0
-#define SSB_SPROM4_ANTAVAIL_BG          0xFF00  /* B-PHY and G-PHY bitfield */
-#define SSB_SPROM4_ANTAVAIL_BG_SHIFT    8
-#define SSB_SPROM4_BFLLO                0x1044  /* Boardflags (low 16 bits) */
-#define SSB_SPROM4_AGAIN01              0x105E  /* Antenna Gain (in dBm Q5.2) */
+#define SSB_SPROM4_ANTAVAIL             0x005D  /* Antenna available bitfields */
+#define  SSB_SPROM4_ANTAVAIL_A          0x00FF  /* A-PHY bitfield */
+#define  SSB_SPROM4_ANTAVAIL_A_SHIFT    0
+#define  SSB_SPROM4_ANTAVAIL_BG         0xFF00  /* B-PHY and G-PHY bitfield */
+#define  SSB_SPROM4_ANTAVAIL_BG_SHIFT   8
+#define SSB_SPROM4_AGAIN01              0x005E  /* Antenna Gain (in dBm Q5.2) */
 #define  SSB_SPROM4_AGAIN0              0x00FF  /* Antenna 0 */
 #define  SSB_SPROM4_AGAIN0_SHIFT        0
 #define  SSB_SPROM4_AGAIN1              0xFF00  /* Antenna 1 */
 #define  SSB_SPROM4_AGAIN1_SHIFT        8
-#define SSB_SPROM4_AGAIN23              0x1060
+#define SSB_SPROM4_AGAIN23              0x0060
 #define  SSB_SPROM4_AGAIN2              0x00FF  /* Antenna 2 */
 #define  SSB_SPROM4_AGAIN2_SHIFT        0
 #define  SSB_SPROM4_AGAIN3              0xFF00  /* Antenna 3 */
 #define  SSB_SPROM4_AGAIN3_SHIFT        8
-#define SSB_SPROM4_BFLHI                0x1046  /* Board Flags Hi */
-#define SSB_SPROM4_MAXP_BG              0x1080  /* Max Power BG in path 1 */
+#define SSB_SPROM4_MAXP_BG              0x0080  /* Max Power BG in path 1 */
 #define  SSB_SPROM4_MAXP_BG_MASK        0x00FF  /* Mask for Max Power BG */
 #define  SSB_SPROM4_ITSSI_BG            0xFF00  /* Mask for path 1 itssi_bg */
 #define  SSB_SPROM4_ITSSI_BG_SHIFT      8
-#define SSB_SPROM4_MAXP_A               0x108A  /* Max Power A in path 1 */
+#define SSB_SPROM4_MAXP_A               0x008A  /* Max Power A in path 1 */
 #define  SSB_SPROM4_MAXP_A_MASK         0x00FF  /* Mask for Max Power A */
 #define  SSB_SPROM4_ITSSI_A             0xFF00  /* Mask for path 1 itssi_a */
 #define  SSB_SPROM4_ITSSI_A_SHIFT       8
-#define SSB_SPROM4_GPIOA                0x1056  /* Gen. Purpose IO # 0 and 1 */
-#define  SSB_SPROM4_GPIOA_P0            0x00FF  /* Pin 0 */
-#define  SSB_SPROM4_GPIOA_P1            0xFF00  /* Pin 1 */
-#define  SSB_SPROM4_GPIOA_P1_SHIFT      8
-#define SSB_SPROM4_GPIOB                0x1058  /* Gen. Purpose IO # 2 and 3 */
-#define  SSB_SPROM4_GPIOB_P2            0x00FF  /* Pin 2 */
-#define  SSB_SPROM4_GPIOB_P3            0xFF00  /* Pin 3 */
-#define  SSB_SPROM4_GPIOB_P3_SHIFT      8
-#define SSB_SPROM4_PA0B0                0x1082  /* The paXbY locations are */
-#define SSB_SPROM4_PA0B1                0x1084  /*   only guesses */
-#define SSB_SPROM4_PA0B2                0x1086
-#define SSB_SPROM4_PA1B0                0x108E
-#define SSB_SPROM4_PA1B1                0x1090
-#define SSB_SPROM4_PA1B2                0x1092
+#define SSB_SPROM4_PA0B0                0x0082  /* The paXbY locations are */
+#define SSB_SPROM4_PA0B1                0x0084  /*   only guesses */
+#define SSB_SPROM4_PA0B2                0x0086
+#define SSB_SPROM4_PA1B0                0x008E
+#define SSB_SPROM4_PA1B1                0x0090
+#define SSB_SPROM4_PA1B2                0x0092
 
 /* SPROM Revision 5 (inherits most data from rev 4) */
-#define SSB_SPROM5_BFLLO                0x104A  /* Boardflags (low 16 bits) */
-#define SSB_SPROM5_BFLHI                0x104C  /* Board Flags Hi */
-#define SSB_SPROM5_IL0MAC               0x1052  /* 6 byte MAC address for a/b/g/n */
-#define SSB_SPROM5_CCODE                0x1044  /* Country Code (2 bytes) */
-#define SSB_SPROM5_GPIOA                0x1076  /* Gen. Purpose IO # 0 and 1 */
+#define SSB_SPROM5_CCODE                0x0044  /* Country Code (2 bytes) */
+#define SSB_SPROM5_BFLLO                0x004A  /* Boardflags (low 16 bits) */
+#define SSB_SPROM5_BFLHI                0x004C  /* Board Flags Hi */
+#define SSB_SPROM5_IL0MAC               0x0052  /* 6 byte MAC address for a/b/g/n */
+#define SSB_SPROM5_GPIOA                0x0076  /* Gen. Purpose IO # 0 and 1 */
 #define  SSB_SPROM5_GPIOA_P0            0x00FF  /* Pin 0 */
 #define  SSB_SPROM5_GPIOA_P1            0xFF00  /* Pin 1 */
 #define  SSB_SPROM5_GPIOA_P1_SHIFT      8
-#define SSB_SPROM5_GPIOB                0x1078  /* Gen. Purpose IO # 2 and 3 */
+#define SSB_SPROM5_GPIOB                0x0078  /* Gen. Purpose IO # 2 and 3 */
 #define  SSB_SPROM5_GPIOB_P2            0x00FF  /* Pin 2 */
 #define  SSB_SPROM5_GPIOB_P3            0xFF00  /* Pin 3 */
 #define  SSB_SPROM5_GPIOB_P3_SHIFT      8
 
 /* SPROM Revision 8 */
-#define SSB_SPROM8_BOARDREV             0x1082  /* Board revision */
-#define SSB_SPROM8_BFLLO                0x1084  /* Board flags (bits 0-15) */
-#define SSB_SPROM8_BFLHI                0x1086  /* Board flags (bits 16-31) */
-#define SSB_SPROM8_BFL2LO               0x1088  /* Board flags (bits 32-47) */
-#define SSB_SPROM8_BFL2HI               0x108A  /* Board flags (bits 48-63) */
-#define SSB_SPROM8_IL0MAC               0x108C  /* 6 byte MAC address */
-#define SSB_SPROM8_CCODE                0x1092  /* 2 byte country code */
-#define SSB_SPROM8_ANTAVAIL             0x109C  /* Antenna available bitfields*/
-#define SSB_SPROM8_ANTAVAIL_A           0xFF00  /* A-PHY bitfield */
-#define SSB_SPROM8_ANTAVAIL_A_SHIFT     8
-#define SSB_SPROM8_ANTAVAIL_BG          0x00FF  /* B-PHY and G-PHY bitfield */
-#define SSB_SPROM8_ANTAVAIL_BG_SHIFT    0
-#define SSB_SPROM8_AGAIN01              0x109E  /* Antenna Gain (in dBm Q5.2) */
+#define SSB_SPROM8_BOARDREV             0x0082  /* Board revision */
+#define SSB_SPROM8_BFLLO                0x0084  /* Board flags (bits 0-15) */
+#define SSB_SPROM8_BFLHI                0x0086  /* Board flags (bits 16-31) */
+#define SSB_SPROM8_BFL2LO               0x0088  /* Board flags (bits 32-47) */
+#define SSB_SPROM8_BFL2HI               0x008A  /* Board flags (bits 48-63) */
+#define SSB_SPROM8_IL0MAC               0x008C  /* 6 byte MAC address */
+#define SSB_SPROM8_CCODE                0x0092  /* 2 byte country code */
+#define SSB_SPROM8_GPIOA                0x0096  /*Gen. Purpose IO # 0 and 1 */
+#define  SSB_SPROM8_GPIOA_P0            0x00FF  /* Pin 0 */
+#define  SSB_SPROM8_GPIOA_P1            0xFF00  /* Pin 1 */
+#define  SSB_SPROM8_GPIOA_P1_SHIFT      8
+#define SSB_SPROM8_GPIOB                0x0098  /* Gen. Purpose IO # 2 and 3 */
+#define  SSB_SPROM8_GPIOB_P2            0x00FF  /* Pin 2 */
+#define  SSB_SPROM8_GPIOB_P3            0xFF00  /* Pin 3 */
+#define  SSB_SPROM8_GPIOB_P3_SHIFT      8
+#define SSB_SPROM8_ANTAVAIL             0x009C  /* Antenna available bitfields*/
+#define  SSB_SPROM8_ANTAVAIL_A          0xFF00  /* A-PHY bitfield */
+#define  SSB_SPROM8_ANTAVAIL_A_SHIFT    8
+#define  SSB_SPROM8_ANTAVAIL_BG         0x00FF  /* B-PHY and G-PHY bitfield */
+#define  SSB_SPROM8_ANTAVAIL_BG_SHIFT   0
+#define SSB_SPROM8_AGAIN01              0x009E  /* Antenna Gain (in dBm Q5.2) */
 #define  SSB_SPROM8_AGAIN0              0x00FF  /* Antenna 0 */
 #define  SSB_SPROM8_AGAIN0_SHIFT        0
 #define  SSB_SPROM8_AGAIN1              0xFF00  /* Antenna 1 */
 #define  SSB_SPROM8_AGAIN1_SHIFT        8
-#define SSB_SPROM8_AGAIN23              0x10A0
+#define SSB_SPROM8_AGAIN23              0x00A0
 #define  SSB_SPROM8_AGAIN2              0x00FF  /* Antenna 2 */
 #define  SSB_SPROM8_AGAIN2_SHIFT        0
 #define  SSB_SPROM8_AGAIN3              0xFF00  /* Antenna 3 */
 #define  SSB_SPROM8_AGAIN3_SHIFT        8
-#define SSB_SPROM8_GPIOA                0x1096  /*Gen. Purpose IO # 0 and 1 */
-#define  SSB_SPROM8_GPIOA_P0            0x00FF  /* Pin 0 */
-#define  SSB_SPROM8_GPIOA_P1            0xFF00  /* Pin 1 */
-#define  SSB_SPROM8_GPIOA_P1_SHIFT      8
-#define SSB_SPROM8_GPIOB                0x1098  /* Gen. Purpose IO # 2 and 3 */
-#define  SSB_SPROM8_GPIOB_P2            0x00FF  /* Pin 2 */
-#define  SSB_SPROM8_GPIOB_P3            0xFF00  /* Pin 3 */
-#define  SSB_SPROM8_GPIOB_P3_SHIFT      8
-#define SSB_SPROM8_RSSIPARM2G           0x10A4  /* RSSI params for 2GHz */
+#define SSB_SPROM8_RSSIPARM2G           0x00A4  /* RSSI params for 2GHz */
 #define  SSB_SPROM8_RSSISMF2G           0x000F
 #define  SSB_SPROM8_RSSISMC2G           0x00F0
 #define  SSB_SPROM8_RSSISMC2G_SHIFT     4
@@ -365,7 +366,7 @@
 #define  SSB_SPROM8_RSSISAV2G_SHIFT     8
 #define  SSB_SPROM8_BXA2G               0x1800
 #define  SSB_SPROM8_BXA2G_SHIFT         11
-#define SSB_SPROM8_RSSIPARM5G           0x10A6  /* RSSI params for 5GHz */
+#define SSB_SPROM8_RSSIPARM5G           0x00A6  /* RSSI params for 5GHz */
 #define  SSB_SPROM8_RSSISMF5G           0x000F
 #define  SSB_SPROM8_RSSISMC5G           0x00F0
 #define  SSB_SPROM8_RSSISMC5G_SHIFT     4
@@ -373,47 +374,47 @@
 #define  SSB_SPROM8_RSSISAV5G_SHIFT     8
 #define  SSB_SPROM8_BXA5G               0x1800
 #define  SSB_SPROM8_BXA5G_SHIFT         11
-#define SSB_SPROM8_TRI25G               0x10A8  /* TX isolation 2.4&5.3GHz */
+#define SSB_SPROM8_TRI25G               0x00A8  /* TX isolation 2.4&5.3GHz */
 #define  SSB_SPROM8_TRI2G               0x00FF  /* TX isolation 2.4GHz */
 #define  SSB_SPROM8_TRI5G               0xFF00  /* TX isolation 5.3GHz */
 #define  SSB_SPROM8_TRI5G_SHIFT         8
-#define SSB_SPROM8_TRI5GHL              0x10AA  /* TX isolation 5.2/5.8GHz */
+#define SSB_SPROM8_TRI5GHL              0x00AA  /* TX isolation 5.2/5.8GHz */
 #define  SSB_SPROM8_TRI5GL              0x00FF  /* TX isolation 5.2GHz */
 #define  SSB_SPROM8_TRI5GH              0xFF00  /* TX isolation 5.8GHz */
 #define  SSB_SPROM8_TRI5GH_SHIFT        8
-#define SSB_SPROM8_RXPO                 0x10AC  /* RX power offsets */
+#define SSB_SPROM8_RXPO                 0x00AC  /* RX power offsets */
 #define  SSB_SPROM8_RXPO2G              0x00FF  /* 2GHz RX power offset */
 #define  SSB_SPROM8_RXPO5G              0xFF00  /* 5GHz RX power offset */
 #define  SSB_SPROM8_RXPO5G_SHIFT        8
-#define SSB_SPROM8_MAXP_BG              0x10C0  /* Max Power 2GHz in path 1 */
+#define SSB_SPROM8_MAXP_BG              0x00C0  /* Max Power 2GHz in path 1 */
 #define  SSB_SPROM8_MAXP_BG_MASK        0x00FF  /* Mask for Max Power 2GHz */
 #define  SSB_SPROM8_ITSSI_BG            0xFF00  /* Mask for path 1 itssi_bg */
 #define  SSB_SPROM8_ITSSI_BG_SHIFT      8
-#define SSB_SPROM8_PA0B0                0x10C2  /* 2GHz power amp settings */
-#define SSB_SPROM8_PA0B1                0x10C4
-#define SSB_SPROM8_PA0B2                0x10C6
-#define SSB_SPROM8_MAXP_A               0x10C8  /* Max Power 5.3GHz */
+#define SSB_SPROM8_PA0B0                0x00C2  /* 2GHz power amp settings */
+#define SSB_SPROM8_PA0B1                0x00C4
+#define SSB_SPROM8_PA0B2                0x00C6
+#define SSB_SPROM8_MAXP_A               0x00C8  /* Max Power 5.3GHz */
 #define  SSB_SPROM8_MAXP_A_MASK         0x00FF  /* Mask for Max Power 5.3GHz */
 #define  SSB_SPROM8_ITSSI_A             0xFF00  /* Mask for path 1 itssi_a */
 #define  SSB_SPROM8_ITSSI_A_SHIFT       8
-#define SSB_SPROM8_MAXP_AHL             0x10CA  /* Max Power 5.2/5.8GHz */
+#define SSB_SPROM8_MAXP_AHL             0x00CA  /* Max Power 5.2/5.8GHz */
 #define  SSB_SPROM8_MAXP_AH_MASK        0x00FF  /* Mask for Max Power 5.8GHz */
 #define  SSB_SPROM8_MAXP_AL_MASK        0xFF00  /* Mask for Max Power 5.2GHz */
 #define  SSB_SPROM8_MAXP_AL_SHIFT       8
-#define SSB_SPROM8_PA1B0                0x10CC  /* 5.3GHz power amp settings */
-#define SSB_SPROM8_PA1B1                0x10CE
-#define SSB_SPROM8_PA1B2                0x10D0
-#define SSB_SPROM8_PA1LOB0              0x10D2  /* 5.2GHz power amp settings */
-#define SSB_SPROM8_PA1LOB1              0x10D4
-#define SSB_SPROM8_PA1LOB2              0x10D6
-#define SSB_SPROM8_PA1HIB0              0x10D8  /* 5.8GHz power amp settings */
-#define SSB_SPROM8_PA1HIB1              0x10DA
-#define SSB_SPROM8_PA1HIB2              0x10DC
-#define SSB_SPROM8_CCK2GPO              0x1140  /* CCK power offset */
-#define SSB_SPROM8_OFDM2GPO             0x1142  /* 2.4GHz OFDM power offset */
-#define SSB_SPROM8_OFDM5GPO             0x1146  /* 5.3GHz OFDM power offset */
-#define SSB_SPROM8_OFDM5GLPO            0x114A  /* 5.2GHz OFDM power offset */
-#define SSB_SPROM8_OFDM5GHPO            0x114E  /* 5.8GHz OFDM power offset */
+#define SSB_SPROM8_PA1B0                0x00CC  /* 5.3GHz power amp settings */
+#define SSB_SPROM8_PA1B1                0x00CE
+#define SSB_SPROM8_PA1B2                0x00D0
+#define SSB_SPROM8_PA1LOB0              0x00D2  /* 5.2GHz power amp settings */
+#define SSB_SPROM8_PA1LOB1              0x00D4
+#define SSB_SPROM8_PA1LOB2              0x00D6
+#define SSB_SPROM8_PA1HIB0              0x00D8  /* 5.8GHz power amp settings */
+#define SSB_SPROM8_PA1HIB1              0x00DA
+#define SSB_SPROM8_PA1HIB2              0x00DC
+#define SSB_SPROM8_CCK2GPO              0x0140  /* CCK power offset */
+#define SSB_SPROM8_OFDM2GPO             0x0142  /* 2.4GHz OFDM power offset */
+#define SSB_SPROM8_OFDM5GPO             0x0146  /* 5.3GHz OFDM power offset */
+#define SSB_SPROM8_OFDM5GLPO            0x014A  /* 5.2GHz OFDM power offset */
+#define SSB_SPROM8_OFDM5GHPO            0x014E  /* 5.8GHz OFDM power offset */
 
 /* Values for SSB_SPROM1_BINF_CCODE */
 enum {
diff --git a/include/net/cfg80211.h b/include/net/cfg80211.h
index 5a4efe54cffd..7d10c0182f53 100644
--- a/include/net/cfg80211.h
+++ b/include/net/cfg80211.h
@@ -511,6 +511,7 @@ struct mpath_info {
  * @basic_rates: basic rates in IEEE 802.11 format
  *      (or NULL for no change)
  * @basic_rates_len: number of basic rates
+ * @ap_isolate: do not forward packets between connected stations
  */
 struct bss_parameters {
         int use_cts_prot;
@@ -518,6 +519,7 @@ struct bss_parameters {
         int use_short_slot_time;
         u8 *basic_rates;
         u8 basic_rates_len;
+        int ap_isolate;
 };
 
 struct mesh_config {
@@ -1018,6 +1020,8 @@ struct cfg80211_pmksa {
  *      RSN IE. It allows for faster roaming between WPA2 BSSIDs.
  * @del_pmksa: Delete a cached PMKID.
  * @flush_pmksa: Flush all cached PMKIDs.
+ * @set_power_mgmt: Configure WLAN power management. A timeout value of -1
+ *      allows the driver to adjust the dynamic ps timeout value.
  * @set_cqm_rssi_config: Configure connection quality monitor RSSI threshold.
  *
  */
diff --git a/include/net/mac80211.h b/include/net/mac80211.h
index 78908b516f42..54aa16b98b76 100644
--- a/include/net/mac80211.h
+++ b/include/net/mac80211.h
@@ -145,6 +145,7 @@ struct ieee80211_low_level_stats {
  * @BSS_CHANGED_BEACON_ENABLED: Beaconing should be
  *      enabled/disabled (beaconing modes)
  * @BSS_CHANGED_CQM: Connection quality monitor config changed
+ * @BSS_CHANGED_IBSS: IBSS join status changed
  */
 enum ieee80211_bss_change {
         BSS_CHANGED_ASSOC               = 1<<0,
@@ -158,6 +159,7 @@ enum ieee80211_bss_change {
         BSS_CHANGED_BEACON              = 1<<8,
         BSS_CHANGED_BEACON_ENABLED      = 1<<9,
         BSS_CHANGED_CQM                 = 1<<10,
+        BSS_CHANGED_IBSS                = 1<<11,
 };
 
 /**
@@ -167,6 +169,8 @@ enum ieee80211_bss_change {
  * to that BSS) that can change during the lifetime of the BSS.
  *
  * @assoc: association status
+ * @ibss_joined: indicates whether this station is part of an IBSS
+ *      or not
  * @aid: association ID number, valid only when @assoc is true
  * @use_cts_prot: use CTS protection
  * @use_short_preamble: use 802.11b short preamble;
@@ -194,7 +198,7 @@ enum ieee80211_bss_change {
 struct ieee80211_bss_conf {
         const u8 *bssid;
         /* association related data */
-        bool assoc;
+        bool assoc, ibss_joined;
         u16 aid;
         /* erp related data */
         bool use_cts_prot;
@@ -556,7 +560,6 @@ enum mac80211_rx_flags {
  * @signal: signal strength when receiving this frame, either in dBm, in dB or
  *      unspecified depending on the hardware capabilities flags
  *      @IEEE80211_HW_SIGNAL_*
- * @noise: noise when receiving this frame, in dBm (DEPRECATED).
  * @antenna: antenna used
  * @rate_idx: index of data rate into band's supported rates or MCS index if
  *      HT rates are use (RX_FLAG_HT)
@@ -567,7 +570,6 @@ struct ieee80211_rx_status {
         enum ieee80211_band band;
         int freq;
         int signal;
-        int noise __deprecated;
         int antenna;
         int rate_idx;
         int flag;
@@ -668,6 +670,9 @@ enum ieee80211_smps_mode {
  * @dynamic_ps_timeout: The dynamic powersave timeout (in ms), see the
  *      powersave documentation below. This variable is valid only when
  *      the CONF_PS flag is set.
+ * @dynamic_ps_forced_timeout: The dynamic powersave timeout (in ms) configured
+ *      by cfg80211 (essentially, wext) If set, this value overrules the value
+ *      chosen by mac80211 based on ps qos network latency.
  *
  * @power_level: requested transmit power (in dBm)
  *
@@ -687,7 +692,7 @@ enum ieee80211_smps_mode {
  */
 struct ieee80211_conf {
         u32 flags;
-        int power_level, dynamic_ps_timeout;
+        int power_level, dynamic_ps_timeout, dynamic_ps_forced_timeout;
         int max_sleep_period;
 
         u16 listen_interval;
@@ -927,10 +932,6 @@ enum ieee80211_tkip_key_type {
  *      one milliwatt. This is the preferred method since it is standardized
  *      between different devices. @max_signal does not need to be set.
  *
- * @IEEE80211_HW_NOISE_DBM:
- *      Hardware can provide noise (radio interference) values in units dBm,
- *      decibel difference from one milliwatt.
- *
  * @IEEE80211_HW_SPECTRUM_MGMT:
  *      Hardware supports spectrum management defined in 802.11h
  *      Measurement, Channel Switch, Quieting, TPC
@@ -994,7 +995,7 @@ enum ieee80211_hw_flags {
         IEEE80211_HW_2GHZ_SHORT_PREAMBLE_INCAPABLE      = 1<<4,
         IEEE80211_HW_SIGNAL_UNSPEC                      = 1<<5,
         IEEE80211_HW_SIGNAL_DBM                         = 1<<6,
-        IEEE80211_HW_NOISE_DBM                          = 1<<7,
+        /* use this hole */
         IEEE80211_HW_SPECTRUM_MGMT                      = 1<<8,
         IEEE80211_HW_AMPDU_AGGREGATION                  = 1<<9,
         IEEE80211_HW_SUPPORTS_PS                        = 1<<10,
@@ -1654,7 +1655,7 @@ struct ieee80211_ops {
                                 struct ieee80211_key_conf *conf,
                                 struct ieee80211_sta *sta,
                                 u32 iv32, u16 *phase1key);
-        int (*hw_scan)(struct ieee80211_hw *hw,
+        int (*hw_scan)(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
                        struct cfg80211_scan_request *req);
         void (*sw_scan_start)(struct ieee80211_hw *hw);
         void (*sw_scan_complete)(struct ieee80211_hw *hw);