Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC platform support updates from Kevin Hilman:
 "Our SoC branch usually contains expanded support for new SoCs and
  other core platform code.  Some highlights from this round:

   - sunxi: SMP support for A23 SoC
   - socpga: big-endian support
   - pxa: conversion to common clock framework
   - bcm: SMP support for BCM63138
   - imx: support new I.MX7D SoC
   - zte: basic support for ZX296702 SoC"

* tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (134 commits)
  ARM: zx: Add basic defconfig support for ZX296702
  ARM: dts: zx: add an initial zx296702 dts and doc
  clk: zx: add clock support to zx296702
  dt-bindings: Add #defines for ZTE ZX296702 clocks
  ARM: socfpga: fix build error due to secondary_startup
  MAINTAINERS: ARM64: EXYNOS: Extend entry for ARM64 DTS
  ARM: ep93xx: simone: support for SPI-based MMC/SD cards
  MAINTAINERS: update Shawn's email to use kernel.org one
  ARM: socfpga: support suspend to ram
  ARM: socfpga: add CPU_METHOD_OF_DECLARE for Arria 10
  ARM: socfpga: use CPU_METHOD_OF_DECLARE for socfpga_cyclone5
  ARM: EXYNOS: register power domain driver from core_initcall
  ARM: EXYNOS: use PS_HOLD based poweroff for all supported SoCs
  ARM: SAMSUNG: Constify platform_device_id
  ARM: EXYNOS: Constify irq_domain_ops
  ARM: EXYNOS: add coupled cpuidle support for Exynos3250
  ARM: EXYNOS: add exynos_get_boot_addr() helper
  ARM: EXYNOS: add exynos_set_boot_addr() helper
  ARM: EXYNOS: make exynos_core_restart() less verbose
  ARM: EXYNOS: fix exynos_boot_secondary() return value on timeout
  ...

8 files changed, 776 insertions, 3 deletions

diff --git a/include/dt-bindings/clock/imx7d-clock.h b/include/dt-bindings/clock/imx7d-clock.h
new file mode 100644
index 000000000000..728df28b00d5
--- /dev/null
+++ b/include/dt-bindings/clock/imx7d-clock.h
@@ -0,0 +1,450 @@
+/*
+ * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX7D_H
+#define __DT_BINDINGS_CLOCK_IMX7D_H
+
+#define IMX7D_OSC_24M_CLK               0
+#define IMX7D_PLL_ARM_MAIN              1
+#define IMX7D_PLL_ARM_MAIN_CLK          2
+#define IMX7D_PLL_ARM_MAIN_SRC          3
+#define IMX7D_PLL_ARM_MAIN_BYPASS       4
+#define IMX7D_PLL_SYS_MAIN              5
+#define IMX7D_PLL_SYS_MAIN_CLK          6
+#define IMX7D_PLL_SYS_MAIN_SRC          7
+#define IMX7D_PLL_SYS_MAIN_BYPASS       8
+#define IMX7D_PLL_SYS_MAIN_480M         9
+#define IMX7D_PLL_SYS_MAIN_240M         10
+#define IMX7D_PLL_SYS_MAIN_120M         11
+#define IMX7D_PLL_SYS_MAIN_480M_CLK     12
+#define IMX7D_PLL_SYS_MAIN_240M_CLK     13
+#define IMX7D_PLL_SYS_MAIN_120M_CLK     14
+#define IMX7D_PLL_SYS_PFD0_392M_CLK     15
+#define IMX7D_PLL_SYS_PFD0_196M         16
+#define IMX7D_PLL_SYS_PFD0_196M_CLK     17
+#define IMX7D_PLL_SYS_PFD1_332M_CLK     18
+#define IMX7D_PLL_SYS_PFD1_166M         19
+#define IMX7D_PLL_SYS_PFD1_166M_CLK     20
+#define IMX7D_PLL_SYS_PFD2_270M_CLK     21
+#define IMX7D_PLL_SYS_PFD2_135M         22
+#define IMX7D_PLL_SYS_PFD2_135M_CLK     23
+#define IMX7D_PLL_SYS_PFD3_CLK          24
+#define IMX7D_PLL_SYS_PFD4_CLK          25
+#define IMX7D_PLL_SYS_PFD5_CLK          26
+#define IMX7D_PLL_SYS_PFD6_CLK          27
+#define IMX7D_PLL_SYS_PFD7_CLK          28
+#define IMX7D_PLL_ENET_MAIN             29
+#define IMX7D_PLL_ENET_MAIN_CLK         30
+#define IMX7D_PLL_ENET_MAIN_SRC         31
+#define IMX7D_PLL_ENET_MAIN_BYPASS      32
+#define IMX7D_PLL_ENET_MAIN_500M        33
+#define IMX7D_PLL_ENET_MAIN_250M        34
+#define IMX7D_PLL_ENET_MAIN_125M        35
+#define IMX7D_PLL_ENET_MAIN_100M        36
+#define IMX7D_PLL_ENET_MAIN_50M         37
+#define IMX7D_PLL_ENET_MAIN_40M         38
+#define IMX7D_PLL_ENET_MAIN_25M         39
+#define IMX7D_PLL_ENET_MAIN_500M_CLK    40
+#define IMX7D_PLL_ENET_MAIN_250M_CLK    41
+#define IMX7D_PLL_ENET_MAIN_125M_CLK    42
+#define IMX7D_PLL_ENET_MAIN_100M_CLK    43
+#define IMX7D_PLL_ENET_MAIN_50M_CLK     44
+#define IMX7D_PLL_ENET_MAIN_40M_CLK     45
+#define IMX7D_PLL_ENET_MAIN_25M_CLK     46
+#define IMX7D_PLL_DRAM_MAIN             47
+#define IMX7D_PLL_DRAM_MAIN_CLK         48
+#define IMX7D_PLL_DRAM_MAIN_SRC         49
+#define IMX7D_PLL_DRAM_MAIN_BYPASS      50
+#define IMX7D_PLL_DRAM_MAIN_533M        51
+#define IMX7D_PLL_DRAM_MAIN_533M_CLK    52
+#define IMX7D_PLL_AUDIO_MAIN            53
+#define IMX7D_PLL_AUDIO_MAIN_CLK        54
+#define IMX7D_PLL_AUDIO_MAIN_SRC        55
+#define IMX7D_PLL_AUDIO_MAIN_BYPASS     56
+#define IMX7D_PLL_VIDEO_MAIN_CLK        57
+#define IMX7D_PLL_VIDEO_MAIN            58
+#define IMX7D_PLL_VIDEO_MAIN_SRC        59
+#define IMX7D_PLL_VIDEO_MAIN_BYPASS     60
+#define IMX7D_USB_MAIN_480M_CLK         61
+#define IMX7D_ARM_A7_ROOT_CLK           62
+#define IMX7D_ARM_A7_ROOT_SRC           63
+#define IMX7D_ARM_A7_ROOT_CG            64
+#define IMX7D_ARM_A7_ROOT_DIV           65
+#define IMX7D_ARM_M4_ROOT_CLK           66
+#define IMX7D_ARM_M4_ROOT_SRC           67
+#define IMX7D_ARM_M4_ROOT_CG            68
+#define IMX7D_ARM_M4_ROOT_DIV           69
+#define IMX7D_ARM_M0_ROOT_CLK           70
+#define IMX7D_ARM_M0_ROOT_SRC           71
+#define IMX7D_ARM_M0_ROOT_CG            72
+#define IMX7D_ARM_M0_ROOT_DIV           73
+#define IMX7D_MAIN_AXI_ROOT_CLK         74
+#define IMX7D_MAIN_AXI_ROOT_SRC         75
+#define IMX7D_MAIN_AXI_ROOT_CG          76
+#define IMX7D_MAIN_AXI_ROOT_DIV         77
+#define IMX7D_DISP_AXI_ROOT_CLK         78
+#define IMX7D_DISP_AXI_ROOT_SRC         79
+#define IMX7D_DISP_AXI_ROOT_CG          80
+#define IMX7D_DISP_AXI_ROOT_DIV         81
+#define IMX7D_ENET_AXI_ROOT_CLK         82
+#define IMX7D_ENET_AXI_ROOT_SRC         83
+#define IMX7D_ENET_AXI_ROOT_CG          84
+#define IMX7D_ENET_AXI_ROOT_DIV         85
+#define IMX7D_NAND_USDHC_BUS_ROOT_CLK   86
+#define IMX7D_NAND_USDHC_BUS_ROOT_SRC   87
+#define IMX7D_NAND_USDHC_BUS_ROOT_CG    88
+#define IMX7D_NAND_USDHC_BUS_ROOT_DIV   89
+#define IMX7D_AHB_CHANNEL_ROOT_CLK      90
+#define IMX7D_AHB_CHANNEL_ROOT_SRC      91
+#define IMX7D_AHB_CHANNEL_ROOT_CG       92
+#define IMX7D_AHB_CHANNEL_ROOT_DIV      93
+#define IMX7D_DRAM_PHYM_ROOT_CLK        94
+#define IMX7D_DRAM_PHYM_ROOT_SRC        95
+#define IMX7D_DRAM_PHYM_ROOT_CG         96
+#define IMX7D_DRAM_PHYM_ROOT_DIV        97
+#define IMX7D_DRAM_ROOT_CLK             98
+#define IMX7D_DRAM_ROOT_SRC             99
+#define IMX7D_DRAM_ROOT_CG              100
+#define IMX7D_DRAM_ROOT_DIV             101
+#define IMX7D_DRAM_PHYM_ALT_ROOT_CLK    102
+#define IMX7D_DRAM_PHYM_ALT_ROOT_SRC    103
+#define IMX7D_DRAM_PHYM_ALT_ROOT_CG     104
+#define IMX7D_DRAM_PHYM_ALT_ROOT_DIV    105
+#define IMX7D_DRAM_ALT_ROOT_CLK         106
+#define IMX7D_DRAM_ALT_ROOT_SRC         107
+#define IMX7D_DRAM_ALT_ROOT_CG          108
+#define IMX7D_DRAM_ALT_ROOT_DIV         109
+#define IMX7D_USB_HSIC_ROOT_CLK         110
+#define IMX7D_USB_HSIC_ROOT_SRC         111
+#define IMX7D_USB_HSIC_ROOT_CG          112
+#define IMX7D_USB_HSIC_ROOT_DIV         113
+#define IMX7D_PCIE_CTRL_ROOT_CLK        114
+#define IMX7D_PCIE_CTRL_ROOT_SRC        115
+#define IMX7D_PCIE_CTRL_ROOT_CG         116
+#define IMX7D_PCIE_CTRL_ROOT_DIV        117
+#define IMX7D_PCIE_PHY_ROOT_CLK         118
+#define IMX7D_PCIE_PHY_ROOT_SRC         119
+#define IMX7D_PCIE_PHY_ROOT_CG          120
+#define IMX7D_PCIE_PHY_ROOT_DIV         121
+#define IMX7D_EPDC_PIXEL_ROOT_CLK       122
+#define IMX7D_EPDC_PIXEL_ROOT_SRC       123
+#define IMX7D_EPDC_PIXEL_ROOT_CG        124
+#define IMX7D_EPDC_PIXEL_ROOT_DIV       125
+#define IMX7D_LCDIF_PIXEL_ROOT_CLK      126
+#define IMX7D_LCDIF_PIXEL_ROOT_SRC      127
+#define IMX7D_LCDIF_PIXEL_ROOT_CG       128
+#define IMX7D_LCDIF_PIXEL_ROOT_DIV      129
+#define IMX7D_MIPI_DSI_ROOT_CLK         130
+#define IMX7D_MIPI_DSI_ROOT_SRC         131
+#define IMX7D_MIPI_DSI_ROOT_CG          132
+#define IMX7D_MIPI_DSI_ROOT_DIV         133
+#define IMX7D_MIPI_CSI_ROOT_CLK         134
+#define IMX7D_MIPI_CSI_ROOT_SRC         135
+#define IMX7D_MIPI_CSI_ROOT_CG          136
+#define IMX7D_MIPI_CSI_ROOT_DIV         137
+#define IMX7D_MIPI_DPHY_ROOT_CLK        138
+#define IMX7D_MIPI_DPHY_ROOT_SRC        139
+#define IMX7D_MIPI_DPHY_ROOT_CG         140
+#define IMX7D_MIPI_DPHY_ROOT_DIV        141
+#define IMX7D_SAI1_ROOT_CLK             142
+#define IMX7D_SAI1_ROOT_SRC             143
+#define IMX7D_SAI1_ROOT_CG              144
+#define IMX7D_SAI1_ROOT_DIV             145
+#define IMX7D_SAI2_ROOT_CLK             146
+#define IMX7D_SAI2_ROOT_SRC             147
+#define IMX7D_SAI2_ROOT_CG              148
+#define IMX7D_SAI2_ROOT_DIV             149
+#define IMX7D_SAI3_ROOT_CLK             150
+#define IMX7D_SAI3_ROOT_SRC             151
+#define IMX7D_SAI3_ROOT_CG              152
+#define IMX7D_SAI3_ROOT_DIV             153
+#define IMX7D_SPDIF_ROOT_CLK            154
+#define IMX7D_SPDIF_ROOT_SRC            155
+#define IMX7D_SPDIF_ROOT_CG             156
+#define IMX7D_SPDIF_ROOT_DIV            157
+#define IMX7D_ENET1_REF_ROOT_CLK        158
+#define IMX7D_ENET1_REF_ROOT_SRC        159
+#define IMX7D_ENET1_REF_ROOT_CG         160
+#define IMX7D_ENET1_REF_ROOT_DIV        161
+#define IMX7D_ENET1_TIME_ROOT_CLK       162
+#define IMX7D_ENET1_TIME_ROOT_SRC       163
+#define IMX7D_ENET1_TIME_ROOT_CG        164
+#define IMX7D_ENET1_TIME_ROOT_DIV       165
+#define IMX7D_ENET2_REF_ROOT_CLK        166
+#define IMX7D_ENET2_REF_ROOT_SRC        167
+#define IMX7D_ENET2_REF_ROOT_CG         168
+#define IMX7D_ENET2_REF_ROOT_DIV        169
+#define IMX7D_ENET2_TIME_ROOT_CLK       170
+#define IMX7D_ENET2_TIME_ROOT_SRC       171
+#define IMX7D_ENET2_TIME_ROOT_CG        172
+#define IMX7D_ENET2_TIME_ROOT_DIV       173
+#define IMX7D_ENET_PHY_REF_ROOT_CLK     174
+#define IMX7D_ENET_PHY_REF_ROOT_SRC     175
+#define IMX7D_ENET_PHY_REF_ROOT_CG      176
+#define IMX7D_ENET_PHY_REF_ROOT_DIV     177
+#define IMX7D_EIM_ROOT_CLK              178
+#define IMX7D_EIM_ROOT_SRC              179
+#define IMX7D_EIM_ROOT_CG               180
+#define IMX7D_EIM_ROOT_DIV              181
+#define IMX7D_NAND_ROOT_CLK             182
+#define IMX7D_NAND_ROOT_SRC             183
+#define IMX7D_NAND_ROOT_CG              184
+#define IMX7D_NAND_ROOT_DIV             185
+#define IMX7D_QSPI_ROOT_CLK             186
+#define IMX7D_QSPI_ROOT_SRC             187
+#define IMX7D_QSPI_ROOT_CG              188
+#define IMX7D_QSPI_ROOT_DIV             189
+#define IMX7D_USDHC1_ROOT_CLK           190
+#define IMX7D_USDHC1_ROOT_SRC           191
+#define IMX7D_USDHC1_ROOT_CG            192
+#define IMX7D_USDHC1_ROOT_DIV           193
+#define IMX7D_USDHC2_ROOT_CLK           194
+#define IMX7D_USDHC2_ROOT_SRC           195
+#define IMX7D_USDHC2_ROOT_CG            196
+#define IMX7D_USDHC2_ROOT_DIV           197
+#define IMX7D_USDHC3_ROOT_CLK           198
+#define IMX7D_USDHC3_ROOT_SRC           199
+#define IMX7D_USDHC3_ROOT_CG            200
+#define IMX7D_USDHC3_ROOT_DIV           201
+#define IMX7D_CAN1_ROOT_CLK             202
+#define IMX7D_CAN1_ROOT_SRC             203
+#define IMX7D_CAN1_ROOT_CG              204
+#define IMX7D_CAN1_ROOT_DIV             205
+#define IMX7D_CAN2_ROOT_CLK             206
+#define IMX7D_CAN2_ROOT_SRC             207
+#define IMX7D_CAN2_ROOT_CG              208
+#define IMX7D_CAN2_ROOT_DIV             209
+#define IMX7D_I2C1_ROOT_CLK             210
+#define IMX7D_I2C1_ROOT_SRC             211
+#define IMX7D_I2C1_ROOT_CG              212
+#define IMX7D_I2C1_ROOT_DIV             213
+#define IMX7D_I2C2_ROOT_CLK             214
+#define IMX7D_I2C2_ROOT_SRC             215
+#define IMX7D_I2C2_ROOT_CG              216
+#define IMX7D_I2C2_ROOT_DIV             217
+#define IMX7D_I2C3_ROOT_CLK             218
+#define IMX7D_I2C3_ROOT_SRC             219
+#define IMX7D_I2C3_ROOT_CG              220
+#define IMX7D_I2C3_ROOT_DIV             221
+#define IMX7D_I2C4_ROOT_CLK             222
+#define IMX7D_I2C4_ROOT_SRC             223
+#define IMX7D_I2C4_ROOT_CG              224
+#define IMX7D_I2C4_ROOT_DIV             225
+#define IMX7D_UART1_ROOT_CLK            226
+#define IMX7D_UART1_ROOT_SRC            227
+#define IMX7D_UART1_ROOT_CG             228
+#define IMX7D_UART1_ROOT_DIV            229
+#define IMX7D_UART2_ROOT_CLK            230
+#define IMX7D_UART2_ROOT_SRC            231
+#define IMX7D_UART2_ROOT_CG             232
+#define IMX7D_UART2_ROOT_DIV            233
+#define IMX7D_UART3_ROOT_CLK            234
+#define IMX7D_UART3_ROOT_SRC            235
+#define IMX7D_UART3_ROOT_CG             236
+#define IMX7D_UART3_ROOT_DIV            237
+#define IMX7D_UART4_ROOT_CLK            238
+#define IMX7D_UART4_ROOT_SRC            239
+#define IMX7D_UART4_ROOT_CG             240
+#define IMX7D_UART4_ROOT_DIV            241
+#define IMX7D_UART5_ROOT_CLK            242
+#define IMX7D_UART5_ROOT_SRC            243
+#define IMX7D_UART5_ROOT_CG             244
+#define IMX7D_UART5_ROOT_DIV            245
+#define IMX7D_UART6_ROOT_CLK            246
+#define IMX7D_UART6_ROOT_SRC            247
+#define IMX7D_UART6_ROOT_CG             248
+#define IMX7D_UART6_ROOT_DIV            249
+#define IMX7D_UART7_ROOT_CLK            250
+#define IMX7D_UART7_ROOT_SRC            251
+#define IMX7D_UART7_ROOT_CG             252
+#define IMX7D_UART7_ROOT_DIV            253
+#define IMX7D_ECSPI1_ROOT_CLK           254
+#define IMX7D_ECSPI1_ROOT_SRC           255
+#define IMX7D_ECSPI1_ROOT_CG            256
+#define IMX7D_ECSPI1_ROOT_DIV           257
+#define IMX7D_ECSPI2_ROOT_CLK           258
+#define IMX7D_ECSPI2_ROOT_SRC           259
+#define IMX7D_ECSPI2_ROOT_CG            260
+#define IMX7D_ECSPI2_ROOT_DIV           261
+#define IMX7D_ECSPI3_ROOT_CLK           262
+#define IMX7D_ECSPI3_ROOT_SRC           263
+#define IMX7D_ECSPI3_ROOT_CG            264
+#define IMX7D_ECSPI3_ROOT_DIV           265
+#define IMX7D_ECSPI4_ROOT_CLK           266
+#define IMX7D_ECSPI4_ROOT_SRC           267
+#define IMX7D_ECSPI4_ROOT_CG            268
+#define IMX7D_ECSPI4_ROOT_DIV           269
+#define IMX7D_PWM1_ROOT_CLK             270
+#define IMX7D_PWM1_ROOT_SRC             271
+#define IMX7D_PWM1_ROOT_CG              272
+#define IMX7D_PWM1_ROOT_DIV             273
+#define IMX7D_PWM2_ROOT_CLK             274
+#define IMX7D_PWM2_ROOT_SRC             275
+#define IMX7D_PWM2_ROOT_CG              276
+#define IMX7D_PWM2_ROOT_DIV             277
+#define IMX7D_PWM3_ROOT_CLK             278
+#define IMX7D_PWM3_ROOT_SRC             279
+#define IMX7D_PWM3_ROOT_CG              280
+#define IMX7D_PWM3_ROOT_DIV             281
+#define IMX7D_PWM4_ROOT_CLK             282
+#define IMX7D_PWM4_ROOT_SRC             283
+#define IMX7D_PWM4_ROOT_CG              284
+#define IMX7D_PWM4_ROOT_DIV             285
+#define IMX7D_FLEXTIMER1_ROOT_CLK       286
+#define IMX7D_FLEXTIMER1_ROOT_SRC       287
+#define IMX7D_FLEXTIMER1_ROOT_CG        288
+#define IMX7D_FLEXTIMER1_ROOT_DIV       289
+#define IMX7D_FLEXTIMER2_ROOT_CLK       290
+#define IMX7D_FLEXTIMER2_ROOT_SRC       291
+#define IMX7D_FLEXTIMER2_ROOT_CG        292
+#define IMX7D_FLEXTIMER2_ROOT_DIV       293
+#define IMX7D_SIM1_ROOT_CLK             294
+#define IMX7D_SIM1_ROOT_SRC             295
+#define IMX7D_SIM1_ROOT_CG              296
+#define IMX7D_SIM1_ROOT_DIV             297
+#define IMX7D_SIM2_ROOT_CLK             298
+#define IMX7D_SIM2_ROOT_SRC             299
+#define IMX7D_SIM2_ROOT_CG              300
+#define IMX7D_SIM2_ROOT_DIV             301
+#define IMX7D_GPT1_ROOT_CLK             302
+#define IMX7D_GPT1_ROOT_SRC             303
+#define IMX7D_GPT1_ROOT_CG              304
+#define IMX7D_GPT1_ROOT_DIV             305
+#define IMX7D_GPT2_ROOT_CLK             306
+#define IMX7D_GPT2_ROOT_SRC             307
+#define IMX7D_GPT2_ROOT_CG              308
+#define IMX7D_GPT2_ROOT_DIV             309
+#define IMX7D_GPT3_ROOT_CLK             310
+#define IMX7D_GPT3_ROOT_SRC             311
+#define IMX7D_GPT3_ROOT_CG              312
+#define IMX7D_GPT3_ROOT_DIV             313
+#define IMX7D_GPT4_ROOT_CLK             314
+#define IMX7D_GPT4_ROOT_SRC             315
+#define IMX7D_GPT4_ROOT_CG              316
+#define IMX7D_GPT4_ROOT_DIV             317
+#define IMX7D_TRACE_ROOT_CLK            318
+#define IMX7D_TRACE_ROOT_SRC            319
+#define IMX7D_TRACE_ROOT_CG             320
+#define IMX7D_TRACE_ROOT_DIV            321
+#define IMX7D_WDOG1_ROOT_CLK            322
+#define IMX7D_WDOG_ROOT_SRC             323
+#define IMX7D_WDOG_ROOT_CG              324
+#define IMX7D_WDOG_ROOT_DIV             325
+#define IMX7D_CSI_MCLK_ROOT_CLK         326
+#define IMX7D_CSI_MCLK_ROOT_SRC         327
+#define IMX7D_CSI_MCLK_ROOT_CG          328
+#define IMX7D_CSI_MCLK_ROOT_DIV         329
+#define IMX7D_AUDIO_MCLK_ROOT_CLK       330
+#define IMX7D_AUDIO_MCLK_ROOT_SRC       331
+#define IMX7D_AUDIO_MCLK_ROOT_CG        332
+#define IMX7D_AUDIO_MCLK_ROOT_DIV       333
+#define IMX7D_WRCLK_ROOT_CLK            334
+#define IMX7D_WRCLK_ROOT_SRC            335
+#define IMX7D_WRCLK_ROOT_CG             336
+#define IMX7D_WRCLK_ROOT_DIV            337
+#define IMX7D_CLKO1_ROOT_SRC            338
+#define IMX7D_CLKO1_ROOT_CG             339
+#define IMX7D_CLKO1_ROOT_DIV            340
+#define IMX7D_CLKO2_ROOT_SRC            341
+#define IMX7D_CLKO2_ROOT_CG             342
+#define IMX7D_CLKO2_ROOT_DIV            343
+#define IMX7D_MAIN_AXI_ROOT_PRE_DIV     344
+#define IMX7D_DISP_AXI_ROOT_PRE_DIV     345
+#define IMX7D_ENET_AXI_ROOT_PRE_DIV     346
+#define IMX7D_NAND_USDHC_BUS_ROOT_PRE_DIV 347
+#define IMX7D_AHB_CHANNEL_ROOT_PRE_DIV  348
+#define IMX7D_USB_HSIC_ROOT_PRE_DIV     349
+#define IMX7D_PCIE_CTRL_ROOT_PRE_DIV    350
+#define IMX7D_PCIE_PHY_ROOT_PRE_DIV     351
+#define IMX7D_EPDC_PIXEL_ROOT_PRE_DIV   352
+#define IMX7D_LCDIF_PIXEL_ROOT_PRE_DIV  353
+#define IMX7D_MIPI_DSI_ROOT_PRE_DIV     354
+#define IMX7D_MIPI_CSI_ROOT_PRE_DIV     355
+#define IMX7D_MIPI_DPHY_ROOT_PRE_DIV    356
+#define IMX7D_SAI1_ROOT_PRE_DIV         357
+#define IMX7D_SAI2_ROOT_PRE_DIV         358
+#define IMX7D_SAI3_ROOT_PRE_DIV         359
+#define IMX7D_SPDIF_ROOT_PRE_DIV        360
+#define IMX7D_ENET1_REF_ROOT_PRE_DIV    361
+#define IMX7D_ENET1_TIME_ROOT_PRE_DIV   362
+#define IMX7D_ENET2_REF_ROOT_PRE_DIV    363
+#define IMX7D_ENET2_TIME_ROOT_PRE_DIV   364
+#define IMX7D_ENET_PHY_REF_ROOT_PRE_DIV 365
+#define IMX7D_EIM_ROOT_PRE_DIV          366
+#define IMX7D_NAND_ROOT_PRE_DIV         367
+#define IMX7D_QSPI_ROOT_PRE_DIV         368
+#define IMX7D_USDHC1_ROOT_PRE_DIV       369
+#define IMX7D_USDHC2_ROOT_PRE_DIV       370
+#define IMX7D_USDHC3_ROOT_PRE_DIV       371
+#define IMX7D_CAN1_ROOT_PRE_DIV         372
+#define IMX7D_CAN2_ROOT_PRE_DIV         373
+#define IMX7D_I2C1_ROOT_PRE_DIV         374
+#define IMX7D_I2C2_ROOT_PRE_DIV         375
+#define IMX7D_I2C3_ROOT_PRE_DIV         376
+#define IMX7D_I2C4_ROOT_PRE_DIV         377
+#define IMX7D_UART1_ROOT_PRE_DIV        378
+#define IMX7D_UART2_ROOT_PRE_DIV        379
+#define IMX7D_UART3_ROOT_PRE_DIV        380
+#define IMX7D_UART4_ROOT_PRE_DIV        381
+#define IMX7D_UART5_ROOT_PRE_DIV        382
+#define IMX7D_UART6_ROOT_PRE_DIV        383
+#define IMX7D_UART7_ROOT_PRE_DIV        384
+#define IMX7D_ECSPI1_ROOT_PRE_DIV       385
+#define IMX7D_ECSPI2_ROOT_PRE_DIV       386
+#define IMX7D_ECSPI3_ROOT_PRE_DIV       387
+#define IMX7D_ECSPI4_ROOT_PRE_DIV       388
+#define IMX7D_PWM1_ROOT_PRE_DIV         389
+#define IMX7D_PWM2_ROOT_PRE_DIV         390
+#define IMX7D_PWM3_ROOT_PRE_DIV         391
+#define IMX7D_PWM4_ROOT_PRE_DIV         392
+#define IMX7D_FLEXTIMER1_ROOT_PRE_DIV   393
+#define IMX7D_FLEXTIMER2_ROOT_PRE_DIV   394
+#define IMX7D_SIM1_ROOT_PRE_DIV         395
+#define IMX7D_SIM2_ROOT_PRE_DIV         396
+#define IMX7D_GPT1_ROOT_PRE_DIV         397
+#define IMX7D_GPT2_ROOT_PRE_DIV         398
+#define IMX7D_GPT3_ROOT_PRE_DIV         399
+#define IMX7D_GPT4_ROOT_PRE_DIV         400
+#define IMX7D_TRACE_ROOT_PRE_DIV        401
+#define IMX7D_WDOG_ROOT_PRE_DIV         402
+#define IMX7D_CSI_MCLK_ROOT_PRE_DIV     403
+#define IMX7D_AUDIO_MCLK_ROOT_PRE_DIV   404
+#define IMX7D_WRCLK_ROOT_PRE_DIV        405
+#define IMX7D_CLKO1_ROOT_PRE_DIV        406
+#define IMX7D_CLKO2_ROOT_PRE_DIV        407
+#define IMX7D_DRAM_PHYM_ALT_ROOT_PRE_DIV 408
+#define IMX7D_DRAM_ALT_ROOT_PRE_DIV     409
+#define IMX7D_LVDS1_IN_CLK              410
+#define IMX7D_LVDS1_OUT_SEL             411
+#define IMX7D_LVDS1_OUT_CLK             412
+#define IMX7D_CLK_DUMMY                 413
+#define IMX7D_GPT_3M_CLK                414
+#define IMX7D_OCRAM_CLK                 415
+#define IMX7D_OCRAM_S_CLK               416
+#define IMX7D_WDOG2_ROOT_CLK            417
+#define IMX7D_WDOG3_ROOT_CLK            418
+#define IMX7D_WDOG4_ROOT_CLK            419
+#define IMX7D_SDMA_CORE_CLK             420
+#define IMX7D_USB1_MAIN_480M_CLK        421
+#define IMX7D_USB_CTRL_CLK              422
+#define IMX7D_USB_PHY1_CLK              423
+#define IMX7D_USB_PHY2_CLK              424
+#define IMX7D_IPG_ROOT_CLK              425
+#define IMX7D_SAI1_IPG_CLK              426
+#define IMX7D_SAI2_IPG_CLK              427
+#define IMX7D_SAI3_IPG_CLK              428
+#define IMX7D_PLL_AUDIO_TEST_DIV        429
+#define IMX7D_PLL_AUDIO_POST_DIV        430
+#define IMX7D_PLL_VIDEO_TEST_DIV        431
+#define IMX7D_PLL_VIDEO_POST_DIV        432
+#define IMX7D_MU_ROOT_CLK               433
+#define IMX7D_SEMA4_HS_ROOT_CLK         434
+#define IMX7D_PLL_DRAM_TEST_DIV         435
+#define IMX7D_CLK_END                   436
+#endif /* __DT_BINDINGS_CLOCK_IMX7D_H */
diff --git a/include/dt-bindings/clock/vf610-clock.h b/include/dt-bindings/clock/vf610-clock.h
index 979d24a6799f..d19763439472 100644
--- a/include/dt-bindings/clock/vf610-clock.h
+++ b/include/dt-bindings/clock/vf610-clock.h
@@ -193,6 +193,7 @@
 #define VF610_PLL6_BYPASS               180
 #define VF610_PLL7_BYPASS               181
 #define VF610_CLK_SNVS                  182
-#define VF610_CLK_END                   183
+#define VF610_CLK_DAP                   183
+#define VF610_CLK_END                   184
 
 #endif /* __DT_BINDINGS_CLOCK_VF610_H */
diff --git a/include/dt-bindings/clock/zx296702-clock.h b/include/dt-bindings/clock/zx296702-clock.h
new file mode 100644
index 000000000000..e683dbb7e7c5
--- /dev/null
+++ b/include/dt-bindings/clock/zx296702-clock.h
@@ -0,0 +1,170 @@
+/*
+ * Copyright 2014 Linaro Ltd.
+ * Copyright (C) 2014 ZTE Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_ZX296702_H
+#define __DT_BINDINGS_CLOCK_ZX296702_H
+
+#define ZX296702_OSC                            0
+#define ZX296702_PLL_A9                         1
+#define ZX296702_PLL_A9_350M                    2
+#define ZX296702_PLL_MAC_1000M                  3
+#define ZX296702_PLL_MAC_333M                   4
+#define ZX296702_PLL_MM0_1188M                  5
+#define ZX296702_PLL_MM0_396M                   6
+#define ZX296702_PLL_MM0_198M                   7
+#define ZX296702_PLL_MM1_108M                   8
+#define ZX296702_PLL_MM1_72M                    9
+#define ZX296702_PLL_MM1_54M                    10
+#define ZX296702_PLL_LSP_104M                   11
+#define ZX296702_PLL_LSP_26M                    12
+#define ZX296702_PLL_AUDIO_294M912              13
+#define ZX296702_PLL_DDR_266M                   14
+#define ZX296702_CLK_148M5                      15
+#define ZX296702_MATRIX_ACLK                    16
+#define ZX296702_MAIN_HCLK                      17
+#define ZX296702_MAIN_PCLK                      18
+#define ZX296702_CLK_500                        19
+#define ZX296702_CLK_250                        20
+#define ZX296702_CLK_125                        21
+#define ZX296702_CLK_74M25                      22
+#define ZX296702_A9_WCLK                        23
+#define ZX296702_A9_AS1_ACLK_MUX                24
+#define ZX296702_A9_TRACE_CLKIN_MUX             25
+#define ZX296702_A9_AS1_ACLK_DIV                26
+#define ZX296702_CLK_2                          27
+#define ZX296702_CLK_27                         28
+#define ZX296702_DECPPU_ACLK_MUX                29
+#define ZX296702_PPU_ACLK_MUX                   30
+#define ZX296702_MALI400_ACLK_MUX               31
+#define ZX296702_VOU_ACLK_MUX                   32
+#define ZX296702_VOU_MAIN_WCLK_MUX              33
+#define ZX296702_VOU_AUX_WCLK_MUX               34
+#define ZX296702_VOU_SCALER_WCLK_MUX            35
+#define ZX296702_R2D_ACLK_MUX                   36
+#define ZX296702_R2D_WCLK_MUX                   37
+#define ZX296702_CLK_50                         38
+#define ZX296702_CLK_25                         39
+#define ZX296702_CLK_12                         40
+#define ZX296702_CLK_16M384                     41
+#define ZX296702_CLK_32K768                     42
+#define ZX296702_SEC_WCLK_DIV                   43
+#define ZX296702_DDR_WCLK_MUX                   44
+#define ZX296702_NAND_WCLK_MUX                  45
+#define ZX296702_LSP_26_WCLK_MUX                46
+#define ZX296702_A9_AS0_ACLK                    47
+#define ZX296702_A9_AS1_ACLK                    48
+#define ZX296702_A9_TRACE_CLKIN                 49
+#define ZX296702_DECPPU_AXI_M_ACLK              50
+#define ZX296702_DECPPU_AHB_S_HCLK              51
+#define ZX296702_PPU_AXI_M_ACLK                 52
+#define ZX296702_PPU_AHB_S_HCLK                 53
+#define ZX296702_VOU_AXI_M_ACLK                 54
+#define ZX296702_VOU_APB_PCLK                   55
+#define ZX296702_VOU_MAIN_CHANNEL_WCLK          56
+#define ZX296702_VOU_AUX_CHANNEL_WCLK           57
+#define ZX296702_VOU_HDMI_OSCLK_CEC             58
+#define ZX296702_VOU_SCALER_WCLK                59
+#define ZX296702_MALI400_AXI_M_ACLK             60
+#define ZX296702_MALI400_APB_PCLK               61
+#define ZX296702_R2D_WCLK                       62
+#define ZX296702_R2D_AXI_M_ACLK                 63
+#define ZX296702_R2D_AHB_HCLK                   64
+#define ZX296702_DDR3_AXI_S0_ACLK               65
+#define ZX296702_DDR3_APB_PCLK                  66
+#define ZX296702_DDR3_WCLK                      67
+#define ZX296702_USB20_0_AHB_HCLK               68
+#define ZX296702_USB20_0_EXTREFCLK              69
+#define ZX296702_USB20_1_AHB_HCLK               70
+#define ZX296702_USB20_1_EXTREFCLK              71
+#define ZX296702_USB20_2_AHB_HCLK               72
+#define ZX296702_USB20_2_EXTREFCLK              73
+#define ZX296702_GMAC_AXI_M_ACLK                74
+#define ZX296702_GMAC_APB_PCLK                  75
+#define ZX296702_GMAC_125_CLKIN                 76
+#define ZX296702_GMAC_RMII_CLKIN                77
+#define ZX296702_GMAC_25M_CLK                   78
+#define ZX296702_NANDFLASH_AHB_HCLK             79
+#define ZX296702_NANDFLASH_WCLK                 80
+#define ZX296702_LSP0_APB_PCLK                  81
+#define ZX296702_LSP0_AHB_HCLK                  82
+#define ZX296702_LSP0_26M_WCLK                  83
+#define ZX296702_LSP0_104M_WCLK                 84
+#define ZX296702_LSP0_16M384_WCLK               85
+#define ZX296702_LSP1_APB_PCLK                  86
+#define ZX296702_LSP1_26M_WCLK                  87
+#define ZX296702_LSP1_104M_WCLK                 88
+#define ZX296702_LSP1_32K_CLK                   89
+#define ZX296702_AON_HCLK                       90
+#define ZX296702_SYS_CTRL_PCLK                  91
+#define ZX296702_DMA_PCLK                       92
+#define ZX296702_DMA_ACLK                       93
+#define ZX296702_SEC_HCLK                       94
+#define ZX296702_AES_WCLK                       95
+#define ZX296702_DES_WCLK                       96
+#define ZX296702_IRAM_ACLK                      97
+#define ZX296702_IROM_ACLK                      98
+#define ZX296702_BOOT_CTRL_HCLK                 99
+#define ZX296702_EFUSE_CLK_30                   100
+#define ZX296702_VOU_MAIN_CHANNEL_DIV           101
+#define ZX296702_VOU_AUX_CHANNEL_DIV            102
+#define ZX296702_VOU_TV_ENC_HD_DIV              103
+#define ZX296702_VOU_TV_ENC_SD_DIV              104
+#define ZX296702_VL0_MUX                        105
+#define ZX296702_VL1_MUX                        106
+#define ZX296702_VL2_MUX                        107
+#define ZX296702_GL0_MUX                        108
+#define ZX296702_GL1_MUX                        109
+#define ZX296702_GL2_MUX                        110
+#define ZX296702_WB_MUX                         111
+#define ZX296702_HDMI_MUX                       112
+#define ZX296702_VOU_TV_ENC_HD_MUX              113
+#define ZX296702_VOU_TV_ENC_SD_MUX              114
+#define ZX296702_VL0_CLK                        115
+#define ZX296702_VL1_CLK                        116
+#define ZX296702_VL2_CLK                        117
+#define ZX296702_GL0_CLK                        118
+#define ZX296702_GL1_CLK                        119
+#define ZX296702_GL2_CLK                        120
+#define ZX296702_WB_CLK                         121
+#define ZX296702_CL_CLK                         122
+#define ZX296702_MAIN_MIX_CLK                   123
+#define ZX296702_AUX_MIX_CLK                    124
+#define ZX296702_HDMI_CLK                       125
+#define ZX296702_VOU_TV_ENC_HD_DAC_CLK          126
+#define ZX296702_VOU_TV_ENC_SD_DAC_CLK          127
+#define ZX296702_A9_PERIPHCLK                   128
+#define ZX296702_TOPCLK_END                     129
+
+#define ZX296702_SDMMC1_WCLK_MUX                0
+#define ZX296702_SDMMC1_WCLK_DIV                1
+#define ZX296702_SDMMC1_WCLK                    2
+#define ZX296702_SDMMC1_PCLK                    3
+#define ZX296702_SPDIF0_WCLK_MUX                4
+#define ZX296702_SPDIF0_WCLK                    5
+#define ZX296702_SPDIF0_PCLK                    6
+#define ZX296702_SPDIF0_DIV                     7
+#define ZX296702_I2S0_WCLK_MUX                  8
+#define ZX296702_I2S0_WCLK                      9
+#define ZX296702_I2S0_PCLK                      10
+#define ZX296702_I2S0_DIV                       11
+#define ZX296702_LSP0CLK_END                    12
+
+#define ZX296702_UART0_WCLK_MUX                 0
+#define ZX296702_UART0_WCLK                     1
+#define ZX296702_UART0_PCLK                     2
+#define ZX296702_UART1_WCLK_MUX                 3
+#define ZX296702_UART1_WCLK                     4
+#define ZX296702_UART1_PCLK                     5
+#define ZX296702_SDMMC0_WCLK_MUX                6
+#define ZX296702_SDMMC0_WCLK_DIV                7
+#define ZX296702_SDMMC0_WCLK                    8
+#define ZX296702_SDMMC0_PCLK                    9
+#define ZX296702_LSP1CLK_END                    10
+
+#endif /* __DT_BINDINGS_CLOCK_ZX296702_H */
diff --git a/include/linux/reset/bcm63xx_pmb.h b/include/linux/reset/bcm63xx_pmb.h
new file mode 100644
index 000000000000..bb4af7b5eb36
--- /dev/null
+++ b/include/linux/reset/bcm63xx_pmb.h
@@ -0,0 +1,88 @@
+/*
+ * Broadcom BCM63xx Processor Monitor Bus shared routines (SMP and reset)
+ *
+ * Copyright (C) 2015, Broadcom Corporation
+ * Author: Florian Fainelli <f.fainelli@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __BCM63XX_PMB_H
+#define __BCM63XX_PMB_H
+
+#include <linux/io.h>
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+
+/* PMB Master controller register */
+#define PMB_CTRL                0x00
+#define  PMC_PMBM_START         (1 << 31)
+#define  PMC_PMBM_TIMEOUT       (1 << 30)
+#define  PMC_PMBM_SLAVE_ERR     (1 << 29)
+#define  PMC_PMBM_BUSY          (1 << 28)
+#define  PMC_PMBM_READ          (0 << 20)
+#define  PMC_PMBM_WRITE         (1 << 20)
+#define PMB_WR_DATA             0x04
+#define PMB_TIMEOUT             0x08
+#define PMB_RD_DATA             0x0C
+
+#define PMB_BUS_ID_SHIFT        8
+
+/* Perform the low-level PMB master operation, shared between reads and
+ * writes.
+ */
+static inline int __bpcm_do_op(void __iomem *master, unsigned int addr,
+                               u32 off, u32 op)
+{
+        unsigned int timeout = 1000;
+        u32 cmd;
+
+        cmd = (PMC_PMBM_START | op | (addr & 0xff) << 12 | off);
+        writel(cmd, master + PMB_CTRL);
+        do {
+                cmd = readl(master + PMB_CTRL);
+                if (!(cmd & PMC_PMBM_START))
+                        return 0;
+
+                if (cmd & PMC_PMBM_SLAVE_ERR)
+                        return -EIO;
+
+                if (cmd & PMC_PMBM_TIMEOUT)
+                        return -ETIMEDOUT;
+
+                udelay(1);
+        } while (timeout-- > 0);
+
+        return -ETIMEDOUT;
+}
+
+static inline int bpcm_rd(void __iomem *master, unsigned int addr,
+                          u32 off, u32 *val)
+{
+        int ret = 0;
+
+        ret = __bpcm_do_op(master, addr, off >> 2, PMC_PMBM_READ);
+        *val = readl(master + PMB_RD_DATA);
+
+        return ret;
+}
+
+static inline int bpcm_wr(void __iomem *master, unsigned int addr,
+                          u32 off, u32 val)
+{
+        int ret = 0;
+
+        writel(val, master + PMB_WR_DATA);
+        ret = __bpcm_do_op(master, addr, off >> 2, PMC_PMBM_WRITE);
+
+        return ret;
+}
+
+#endif /* __BCM63XX_PMB_H */
diff --git a/include/soc/imx/revision.h b/include/soc/imx/revision.h
new file mode 100644
index 000000000000..9ea346924c35
--- /dev/null
+++ b/include/soc/imx/revision.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright 2015 Linaro Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __SOC_IMX_REVISION_H__
+#define __SOC_IMX_REVISION_H__
+
+#define IMX_CHIP_REVISION_1_0           0x10
+#define IMX_CHIP_REVISION_1_1           0x11
+#define IMX_CHIP_REVISION_1_2           0x12
+#define IMX_CHIP_REVISION_1_3           0x13
+#define IMX_CHIP_REVISION_1_4           0x14
+#define IMX_CHIP_REVISION_1_5           0x15
+#define IMX_CHIP_REVISION_2_0           0x20
+#define IMX_CHIP_REVISION_2_1           0x21
+#define IMX_CHIP_REVISION_2_2           0x22
+#define IMX_CHIP_REVISION_2_3           0x23
+#define IMX_CHIP_REVISION_3_0           0x30
+#define IMX_CHIP_REVISION_3_1           0x31
+#define IMX_CHIP_REVISION_3_2           0x32
+#define IMX_CHIP_REVISION_3_3           0x33
+#define IMX_CHIP_REVISION_UNKNOWN       0xff
+
+int mx27_revision(void);
+int mx31_revision(void);
+int mx35_revision(void);
+int mx51_revision(void);
+int mx53_revision(void);
+
+unsigned int imx_get_soc_revision(void);
+void imx_print_silicon_rev(const char *cpu, int srev);
+
+#endif /* __SOC_IMX_REVISION_H__ */
diff --git a/include/soc/imx/timer.h b/include/soc/imx/timer.h
new file mode 100644
index 000000000000..bbbafd65f464
--- /dev/null
+++ b/include/soc/imx/timer.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright 2015 Linaro Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __SOC_IMX_TIMER_H__
+#define __SOC_IMX_TIMER_H__
+
+enum imx_gpt_type {
+        GPT_TYPE_IMX1,          /* i.MX1 */
+        GPT_TYPE_IMX21,         /* i.MX21/27 */
+        GPT_TYPE_IMX31,         /* i.MX31/35/25/37/51/6Q */
+        GPT_TYPE_IMX6DL,        /* i.MX6DL/SX/SL */
+};
+
+/*
+ * This is a stop-gap solution for clock drivers like imx1/imx21 which call
+ * mxc_timer_init() to initialize timer for non-DT boot.  It can be removed
+ * when these legacy non-DT support is converted or dropped.
+ */
+void mxc_timer_init(unsigned long pbase, int irq, enum imx_gpt_type type);
+
+#endif  /* __SOC_IMX_TIMER_H__ */
diff --git a/include/soc/tegra/pmc.h b/include/soc/tegra/pmc.h
index 65a93273e72f..f5c0de43a5fa 100644
--- a/include/soc/tegra/pmc.h
+++ b/include/soc/tegra/pmc.h
@@ -26,8 +26,6 @@
 struct clk;
 struct reset_control;
 
-void tegra_pmc_restart(enum reboot_mode mode, const char *cmd);
-
 #ifdef CONFIG_PM_SLEEP
 enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void);
 void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode);
diff --git a/include/uapi/linux/serial_reg.h b/include/uapi/linux/serial_reg.h
index e9b4cb0cd7ed..1e5ac4e776da 100644
--- a/include/uapi/linux/serial_reg.h
+++ b/include/uapi/linux/serial_reg.h
@@ -331,6 +331,9 @@
  * Extra serial register definitions for the internal UARTs
  * in TI OMAP processors.
  */
+#define OMAP1_UART1_BASE        0xfffb0000
+#define OMAP1_UART2_BASE        0xfffb0800
+#define OMAP1_UART3_BASE        0xfffb9800
 #define UART_OMAP_MDR1          0x08    /* Mode definition register */
 #define UART_OMAP_MDR2          0x09    /* Mode definition register 2 */
 #define UART_OMAP_SCR           0x10    /* Supplementary control register */