Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC platform support updates from Kevin Hilman:
 "Our SoC branch usually contains expanded support for new SoCs and
  other core platform code.  Some highlights from this round:

   - sunxi: SMP support for A23 SoC
   - socpga: big-endian support
   - pxa: conversion to common clock framework
   - bcm: SMP support for BCM63138
   - imx: support new I.MX7D SoC
   - zte: basic support for ZX296702 SoC"

* tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (134 commits)
  ARM: zx: Add basic defconfig support for ZX296702
  ARM: dts: zx: add an initial zx296702 dts and doc
  clk: zx: add clock support to zx296702
  dt-bindings: Add #defines for ZTE ZX296702 clocks
  ARM: socfpga: fix build error due to secondary_startup
  MAINTAINERS: ARM64: EXYNOS: Extend entry for ARM64 DTS
  ARM: ep93xx: simone: support for SPI-based MMC/SD cards
  MAINTAINERS: update Shawn's email to use kernel.org one
  ARM: socfpga: support suspend to ram
  ARM: socfpga: add CPU_METHOD_OF_DECLARE for Arria 10
  ARM: socfpga: use CPU_METHOD_OF_DECLARE for socfpga_cyclone5
  ARM: EXYNOS: register power domain driver from core_initcall
  ARM: EXYNOS: use PS_HOLD based poweroff for all supported SoCs
  ARM: SAMSUNG: Constify platform_device_id
  ARM: EXYNOS: Constify irq_domain_ops
  ARM: EXYNOS: add coupled cpuidle support for Exynos3250
  ARM: EXYNOS: add exynos_get_boot_addr() helper
  ARM: EXYNOS: add exynos_set_boot_addr() helper
  ARM: EXYNOS: make exynos_core_restart() less verbose
  ARM: EXYNOS: fix exynos_boot_secondary() return value on timeout
  ...

8 files changed, 776 insertions, 3 deletions

diff --git a/include/dt-bindings/clock/imx7d-clock.h b/include/dt-bindings/clock/imx7d-clock.h
new file mode 100644
index 000000000000..728df28b00d5
--- /dev/null
+++ b/include/dt-bindings/clock/imx7d-clock.h
@@ -0,0 +1,450 @@
+/*
+ * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX7D_H
+#define __DT_BINDINGS_CLOCK_IMX7D_H
+
+#define IMX7D_OSC_24M_CLK               0
+#define IMX7D_PLL_ARM_MAIN              1
+#define IMX7D_PLL_ARM_MAIN_CLK          2
+#define IMX7D_PLL_ARM_MAIN_SRC          3
+#define IMX7D_PLL_ARM_MAIN_BYPASS       4
+#define IMX7D_PLL_SYS_MAIN              5
+#define IMX7D_PLL_SYS_MAIN_CLK          6
+#define IMX7D_PLL_SYS_MAIN_SRC          7
+#define IMX7D_PLL_SYS_MAIN_BYPASS       8
+#define IMX7D_PLL_SYS_MAIN_480M         9
+#define IMX7D_PLL_SYS_MAIN_240M         10
+#define IMX7D_PLL_SYS_MAIN_120M         11
+#define IMX7D_PLL_SYS_MAIN_480M_CLK     12
+#define IMX7D_PLL_SYS_MAIN_240M_CLK     13
+#define IMX7D_PLL_SYS_MAIN_120M_CLK     14
+#define IMX7D_PLL_SYS_PFD0_392M_CLK     15
+#define IMX7D_PLL_SYS_PFD0_196M         16
+#define IMX7D_PLL_SYS_PFD0_196M_CLK     17
+#define IMX7D_PLL_SYS_PFD1_332M_CLK     18
+#define IMX7D_PLL_SYS_PFD1_166M         19
+#define IMX7D_PLL_SYS_PFD1_166M_CLK     20
+#define IMX7D_PLL_SYS_PFD2_270M_CLK     21
+#define IMX7D_PLL_SYS_PFD2_135M         22
+#define IMX7D_PLL_SYS_PFD2_135M_CLK     23
+#define IMX7D_PLL_SYS_PFD3_CLK          24
+#define IMX7D_PLL_SYS_PFD4_CLK          25
+#define IMX7D_PLL_SYS_PFD5_CLK          26
+#define IMX7D_PLL_SYS_PFD6_CLK          27
+#define IMX7D_PLL_SYS_PFD7_CLK          28
+#define IMX7D_PLL_ENET_MAIN             29
+#define IMX7D_PLL_ENET_MAIN_CLK         30
+#define IMX7D_PLL_ENET_MAIN_SRC         31
+#define IMX7D_PLL_ENET_MAIN_BYPASS      32
+#define IMX7D_PLL_ENET_MAIN_500M        33
+#define IMX7D_PLL_ENET_MAIN_250M        34
+#define IMX7D_PLL_ENET_MAIN_125M        35
+#define IMX7D_PLL_ENET_MAIN_100M        36
+#define IMX7D_PLL_ENET_MAIN_50M         37
+#define IMX7D_PLL_ENET_MAIN_40M         38
+#define IMX7D_PLL_ENET_MAIN_25M         39
+#define IMX7D_PLL_ENET_MAIN_500M_CLK    40
+#define IMX7D_PLL_ENET_MAIN_250M_CLK    41
+#define IMX7D_PLL_ENET_MAIN_125M_CLK    42
+#define IMX7D_PLL_ENET_MAIN_100M_CLK    43
+#define IMX7D_PLL_ENET_MAIN_50M_CLK     44
+#define IMX7D_PLL_ENET_MAIN_40M_CLK     45
+#define IMX7D_PLL_ENET_MAIN_25M_CLK     46
+#define IMX7D_PLL_DRAM_MAIN             47
+#define IMX7D_PLL_DRAM_MAIN_CLK         48
+#define IMX7D_PLL_DRAM_MAIN_SRC         49
+#define IMX7D_PLL_DRAM_MAIN_BYPASS      50
+#define IMX7D_PLL_DRAM_MAIN_533M        51
+#define IMX7D_PLL_DRAM_MAIN_533M_CLK    52
+#define IMX7D_PLL_AUDIO_MAIN            53
+#define IMX7D_PLL_AUDIO_MAIN_CLK        54
+#define IMX7D_PLL_AUDIO_MAIN_SRC        55
+#define IMX7D_PLL_AUDIO_MAIN_BYPASS     56
+#define IMX7D_PLL_VIDEO_MAIN_CLK        57
+#define IMX7D_PLL_VIDEO_MAIN            58
+#define IMX7D_PLL_VIDEO_MAIN_SRC        59
+#define IMX7D_PLL_VIDEO_MAIN_BYPASS     60
+#define IMX7D_USB_MAIN_480M_CLK         61
+#define IMX7D_ARM_A7_ROOT_CLK           62
+#define IMX7D_ARM_A7_ROOT_SRC           63
+#define IMX7D_ARM_A7_ROOT_CG            64
+#define IMX7D_ARM_A7_ROOT_DIV           65
+#define IMX7D_ARM_M4_ROOT_CLK           66
+#define IMX7D_ARM_M4_ROOT_SRC           67
+#define IMX7D_ARM_M4_ROOT_CG            68
+#define IMX7D_ARM_M4_ROOT_DIV           69
+#define IMX7D_ARM_M0_ROOT_CLK           70
+#define IMX7D_ARM_M0_ROOT_SRC           71
+#define IMX7D_ARM_M0_ROOT_CG            72
+#define IMX7D_ARM_M0_ROOT_DIV           73
+#define IMX7D_MAIN_AXI_ROOT_CLK         74
+#define IMX7D_MAIN_AXI_ROOT_SRC         75
+#define IMX7D_MAIN_AXI_ROOT_CG          76
+#define IMX7D_MAIN_AXI_ROOT_DIV         77
+#define IMX7D_DISP_AXI_ROOT_CLK         78
+#define IMX7D_DISP_AXI_ROOT_SRC         79
+#define IMX7D_DISP_AXI_ROOT_CG          80
+#define IMX7D_DISP_AXI_ROOT_DIV         81
+#define IMX7D_ENET_AXI_ROOT_CLK         82
+#define IMX7D_ENET_AXI_ROOT_SRC         83
+#define IMX7D_ENET_AXI_ROOT_CG          84
+#define IMX7D_ENET_AXI_ROOT_DIV         85
+#define IMX7D_NAND_USDHC_BUS_ROOT_CLK   86
+#define IMX7D_NAND_USDHC_BUS_ROOT_SRC   87
+#define IMX7D_NAND_USDHC_BUS_ROOT_CG    88
+#define IMX7D_NAND_USDHC_BUS_ROOT_DIV   89
+#define IMX7D_AHB_CHANNEL_ROOT_CLK      90
+#define IMX7D_AHB_CHANNEL_ROOT_SRC      91
+#define IMX7D_AHB_CHANNEL_ROOT_CG       92
+#define IMX7D_AHB_CHANNEL_ROOT_DIV      93
+#define IMX7D_DRAM_PHYM_ROOT_CLK        94
+#define IMX7D_DRAM_PHYM_ROOT_SRC        95
+#define IMX7D_DRAM_PHYM_ROOT_CG         96
+#define IMX7D_DRAM_PHYM_ROOT_DIV        97
+#define IMX7D_DRAM_ROOT_CLK             98
+#define IMX7D_DRAM_ROOT_SRC             99
+#define IMX7D_DRAM_ROOT_CG              100
+#define IMX7D_DRAM_ROOT_DIV             101
+#define IMX7D_DRAM_PHYM_ALT_ROOT_CLK    102
+#define IMX7D_DRAM_PHYM_ALT_ROOT_SRC    103
+#define IMX7D_DRAM_PHYM_ALT_ROOT_CG     104
+#define IMX7D_DRAM_PHYM_ALT_ROOT_DIV    105
+#define IMX7D_DRAM_ALT_ROOT_CLK         106
+#define IMX7D_DRAM_ALT_ROOT_SRC         107
+#define IMX7D_DRAM_ALT_ROOT_CG          108
+#define IMX7D_DRAM_ALT_ROOT_DIV         109
+#define IMX7D_USB_HSIC_ROOT_CLK         110
+#define IMX7D_USB_HSIC_ROOT_SRC         111
+#define IMX7D_USB_HSIC_ROOT_CG          112
+#define IMX7D_USB_HSIC_ROOT_DIV         113
+#define IMX7D_PCIE_CTRL_ROOT_CLK        114
+#define IMX7D_PCIE_CTRL_ROOT_SRC        115
+#define IMX7D_PCIE_CTRL_ROOT_CG         116
+#define IMX7D_PCIE_CTRL_ROOT_DIV        117
+#define IMX7D_PCIE_PHY_ROOT_CLK         118
+#define IMX7D_PCIE_PHY_ROOT_SRC         119
+#define IMX7D_PCIE_PHY_ROOT_CG          120
+#define IMX7D_PCIE_PHY_ROOT_DIV         121
+#define IMX7D_EPDC_PIXEL_ROOT_CLK       122
+#define IMX7D_EPDC_PIXEL_ROOT_SRC       123
+#define IMX7D_EPDC_PIXEL_ROOT_CG        124
+#define IMX7D_EPDC_PIXEL_ROOT_DIV       125
+#define IMX7D_LCDIF_PIXEL_ROOT_CLK      126
+#define IMX7D_LCDIF_PIXEL_ROOT_SRC      127
+#define IMX7D_LCDIF_PIXEL_ROOT_CG       128
+#define IMX7D_LCDIF_PIXEL_ROOT_DIV      129
+#define IMX7D_MIPI_DSI_ROOT_CLK         130
+#define IMX7D_MIPI_DSI_ROOT_SRC         131
+#define IMX7D_MIPI_DSI_ROOT_CG          132
+#define IMX7D_MIPI_DSI_ROOT_DIV         133
+#define IMX7D_MIPI_CSI_ROOT_CLK         134
+#define IMX7D_MIPI_CSI_ROOT_SRC         135
+#define IMX7D_MIPI_CSI_ROOT_CG          136
+#define IMX7D_MIPI_CSI_ROOT_DIV         137
+#define IMX7D_MIPI_DPHY_ROOT_CLK        138
+#define IMX7D_MIPI_DPHY_ROOT_SRC        139
+#define IMX7D_MIPI_DPHY_ROOT_CG         140
+#define IMX7D_MIPI_DPHY_ROOT_DIV        141
+#define IMX7D_SAI1_ROOT_CLK             142
+#define IMX7D_SAI1_ROOT_SRC             143
+#define IMX7D_SAI1_ROOT_CG              144
+#define IMX7D_SAI1_ROOT_DIV             145
+#define IMX7D_SAI2_ROOT_CLK             146
+#define IMX7D_SAI2_ROOT_SRC             147
+#define IMX7D_SAI2_ROOT_CG              148
+#define IMX7D_SAI2_ROOT_DIV             149
+#define IMX7D_SAI3_ROOT_CLK             150
+#define IMX7D_SAI3_ROOT_SRC             151
+#define IMX7D_SAI3_ROOT_CG              152
+#define IMX7D_SAI3_ROOT_DIV             153
+#define IMX7D_SPDIF_ROOT_CLK            154
+#define IMX7D_SPDIF_ROOT_SRC            155
+#define IMX7D_SPDIF_ROOT_CG             156
+#define IMX7D_SPDIF_ROOT_DIV            157
+#define IMX7D_ENET1_REF_ROOT_CLK        158
+#define IMX7D_ENET1_REF_ROOT_SRC        159
+#define IMX7D_ENET1_REF_ROOT_CG         160
+#define IMX7D_ENET1_REF_ROOT_DIV        161
+#define IMX7D_ENET1_TIME_ROOT_CLK       162
+#define IMX7D_ENET1_TIME_ROOT_SRC       163
+#define IMX7D_ENET1_TIME_ROOT_CG        164
+#define IMX7D_ENET1_TIME_ROOT_DIV       165
+#define IMX7D_ENET2_REF_ROOT_CLK        166
+#define IMX7D_ENET2_REF_ROOT_SRC        167