diff options
| author | Ram Amrani <Ram.Amrani@cavium.com> | 2016-10-10 06:15:30 -0400 |
|---|---|---|
| committer | Doug Ledford <dledford@redhat.com> | 2016-10-14 15:00:10 -0400 |
| commit | 2e0cbc4dd077aea4f1693583fd68eaed4d60464b (patch) | |
| tree | cb8190e0edbb919e2f13c41f2d63a03454ae9992 /include/uapi/linux | |
| parent | e9f8f48bcac6f6dd37ad89ad63d1d1a497332313 (diff) | |
qedr: Add RoCE driver framework
Adds a skeletal implementation of the qed* RoCE driver -
basically the ability to communicate with the qede driver and
receive notifications from it regarding various init/exit events.
Signed-off-by: Rajesh Borundia <rajesh.borundia@cavium.com>
Signed-off-by: Ram Amrani <Ram.Amrani@cavium.com>
Signed-off-by: Doug Ledford <dledford@redhat.com>
Diffstat (limited to 'include/uapi/linux')
| -rw-r--r-- | include/uapi/linux/pci_regs.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index d812172d1d7b..e5a2e68b2236 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h | |||
| @@ -612,6 +612,8 @@ | |||
| 612 | */ | 612 | */ |
| 613 | #define PCI_EXP_DEVCAP2 36 /* Device Capabilities 2 */ | 613 | #define PCI_EXP_DEVCAP2 36 /* Device Capabilities 2 */ |
| 614 | #define PCI_EXP_DEVCAP2_ARI 0x00000020 /* Alternative Routing-ID */ | 614 | #define PCI_EXP_DEVCAP2_ARI 0x00000020 /* Alternative Routing-ID */ |
| 615 | #define PCI_EXP_DEVCAP2_ATOMIC_ROUTE 0x00000040 /* Atomic Op routing */ | ||
| 616 | #define PCI_EXP_DEVCAP2_ATOMIC_COMP64 0x00000100 /* Atomic 64-bit compare */ | ||
| 615 | #define PCI_EXP_DEVCAP2_LTR 0x00000800 /* Latency tolerance reporting */ | 617 | #define PCI_EXP_DEVCAP2_LTR 0x00000800 /* Latency tolerance reporting */ |
| 616 | #define PCI_EXP_DEVCAP2_OBFF_MASK 0x000c0000 /* OBFF support mechanism */ | 618 | #define PCI_EXP_DEVCAP2_OBFF_MASK 0x000c0000 /* OBFF support mechanism */ |
| 617 | #define PCI_EXP_DEVCAP2_OBFF_MSG 0x00040000 /* New message signaling */ | 619 | #define PCI_EXP_DEVCAP2_OBFF_MSG 0x00040000 /* New message signaling */ |
| @@ -619,6 +621,7 @@ | |||
| 619 | #define PCI_EXP_DEVCTL2 40 /* Device Control 2 */ | 621 | #define PCI_EXP_DEVCTL2 40 /* Device Control 2 */ |
| 620 | #define PCI_EXP_DEVCTL2_COMP_TIMEOUT 0x000f /* Completion Timeout Value */ | 622 | #define PCI_EXP_DEVCTL2_COMP_TIMEOUT 0x000f /* Completion Timeout Value */ |
| 621 | #define PCI_EXP_DEVCTL2_ARI 0x0020 /* Alternative Routing-ID */ | 623 | #define PCI_EXP_DEVCTL2_ARI 0x0020 /* Alternative Routing-ID */ |
| 624 | #define PCI_EXP_DEVCTL2_ATOMIC_REQ 0x0040 /* Set Atomic requests */ | ||
| 622 | #define PCI_EXP_DEVCTL2_IDO_REQ_EN 0x0100 /* Allow IDO for requests */ | 625 | #define PCI_EXP_DEVCTL2_IDO_REQ_EN 0x0100 /* Allow IDO for requests */ |
| 623 | #define PCI_EXP_DEVCTL2_IDO_CMP_EN 0x0200 /* Allow IDO for completions */ | 626 | #define PCI_EXP_DEVCTL2_IDO_CMP_EN 0x0200 /* Allow IDO for completions */ |
| 624 | #define PCI_EXP_DEVCTL2_LTR_EN 0x0400 /* Enable LTR mechanism */ | 627 | #define PCI_EXP_DEVCTL2_LTR_EN 0x0400 /* Enable LTR mechanism */ |
