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authorDaniel Vetter <daniel.vetter@ffwll.ch>2016-08-05 04:36:15 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2016-08-05 04:36:15 -0400
commit94558e265b9539b2ecec98d037bae51c902663c1 (patch)
treee2782bc903759c2a8bf0af9b3a8ec090a3b1bd3e /include/uapi/drm
parent5ac9056753e79ac5ad1ccc3c99b311688e46e8c9 (diff)
parent1cf915d305b6e1d57db6c35c208016f9747ba3c6 (diff)
Merge remote-tracking branch 'airlied/drm-next' into drm-intel-next-queued
Backmerge the 4.8 pull request state from Dave - conflicts were getting out of hand, and Chris has some patches which outright don't apply without everything merged together again. Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Diffstat (limited to 'include/uapi/drm')
-rw-r--r--include/uapi/drm/amdgpu_drm.h32
-rw-r--r--include/uapi/drm/msm_drm.h25
-rw-r--r--include/uapi/drm/vc4_drm.h13
-rw-r--r--include/uapi/drm/vgem_drm.h62
4 files changed, 116 insertions, 16 deletions
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index cdecf87576e8..462246aa200e 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -487,6 +487,22 @@ struct drm_amdgpu_cs_chunk_data {
487#define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 487#define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8
488#define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff 488#define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff
489 489
490struct drm_amdgpu_query_fw {
491 /** AMDGPU_INFO_FW_* */
492 __u32 fw_type;
493 /**
494 * Index of the IP if there are more IPs of
495 * the same type.
496 */
497 __u32 ip_instance;
498 /**
499 * Index of the engine. Whether this is used depends
500 * on the firmware type. (e.g. MEC, SDMA)
501 */
502 __u32 index;
503 __u32 _pad;
504};
505
490/* Input structure for the INFO ioctl */ 506/* Input structure for the INFO ioctl */
491struct drm_amdgpu_info { 507struct drm_amdgpu_info {
492 /* Where the return value will be stored */ 508 /* Where the return value will be stored */
@@ -522,21 +538,7 @@ struct drm_amdgpu_info {
522 __u32 flags; 538 __u32 flags;
523 } read_mmr_reg; 539 } read_mmr_reg;
524 540
525 struct { 541 struct drm_amdgpu_query_fw query_fw;
526 /** AMDGPU_INFO_FW_* */
527 __u32 fw_type;
528 /**
529 * Index of the IP if there are more IPs of
530 * the same type.
531 */
532 __u32 ip_instance;
533 /**
534 * Index of the engine. Whether this is used depends
535 * on the firmware type. (e.g. MEC, SDMA)
536 */
537 __u32 index;
538 __u32 _pad;
539 } query_fw;
540 }; 542 };
541}; 543};
542 544
diff --git a/include/uapi/drm/msm_drm.h b/include/uapi/drm/msm_drm.h
index bf19d2cd9078..49f778de8e06 100644
--- a/include/uapi/drm/msm_drm.h
+++ b/include/uapi/drm/msm_drm.h
@@ -201,6 +201,27 @@ struct drm_msm_wait_fence {
201 struct drm_msm_timespec timeout; /* in */ 201 struct drm_msm_timespec timeout; /* in */
202}; 202};
203 203
204/* madvise provides a way to tell the kernel in case a buffers contents
205 * can be discarded under memory pressure, which is useful for userspace
206 * bo cache where we want to optimistically hold on to buffer allocate
207 * and potential mmap, but allow the pages to be discarded under memory
208 * pressure.
209 *
210 * Typical usage would involve madvise(DONTNEED) when buffer enters BO
211 * cache, and madvise(WILLNEED) if trying to recycle buffer from BO cache.
212 * In the WILLNEED case, 'retained' indicates to userspace whether the
213 * backing pages still exist.
214 */
215#define MSM_MADV_WILLNEED 0 /* backing pages are needed, status returned in 'retained' */
216#define MSM_MADV_DONTNEED 1 /* backing pages not needed */
217#define __MSM_MADV_PURGED 2 /* internal state */
218
219struct drm_msm_gem_madvise {
220 __u32 handle; /* in, GEM handle */
221 __u32 madv; /* in, MSM_MADV_x */
222 __u32 retained; /* out, whether backing store still exists */
223};
224
204#define DRM_MSM_GET_PARAM 0x00 225#define DRM_MSM_GET_PARAM 0x00
205/* placeholder: 226/* placeholder:
206#define DRM_MSM_SET_PARAM 0x01 227#define DRM_MSM_SET_PARAM 0x01
@@ -211,7 +232,8 @@ struct drm_msm_wait_fence {
211#define DRM_MSM_GEM_CPU_FINI 0x05 232#define DRM_MSM_GEM_CPU_FINI 0x05
212#define DRM_MSM_GEM_SUBMIT 0x06 233#define DRM_MSM_GEM_SUBMIT 0x06
213#define DRM_MSM_WAIT_FENCE 0x07 234#define DRM_MSM_WAIT_FENCE 0x07
214#define DRM_MSM_NUM_IOCTLS 0x08 235#define DRM_MSM_GEM_MADVISE 0x08
236#define DRM_MSM_NUM_IOCTLS 0x09
215 237
216#define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param) 238#define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param)
217#define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new) 239#define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new)
@@ -220,6 +242,7 @@ struct drm_msm_wait_fence {
220#define DRM_IOCTL_MSM_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini) 242#define DRM_IOCTL_MSM_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini)
221#define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit) 243#define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit)
222#define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence) 244#define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence)
245#define DRM_IOCTL_MSM_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_MADVISE, struct drm_msm_gem_madvise)
223 246
224#if defined(__cplusplus) 247#if defined(__cplusplus)
225} 248}
diff --git a/include/uapi/drm/vc4_drm.h b/include/uapi/drm/vc4_drm.h
index af12e8a184c8..ad7edc3edf7c 100644
--- a/include/uapi/drm/vc4_drm.h
+++ b/include/uapi/drm/vc4_drm.h
@@ -37,6 +37,7 @@ extern "C" {
37#define DRM_VC4_MMAP_BO 0x04 37#define DRM_VC4_MMAP_BO 0x04
38#define DRM_VC4_CREATE_SHADER_BO 0x05 38#define DRM_VC4_CREATE_SHADER_BO 0x05
39#define DRM_VC4_GET_HANG_STATE 0x06 39#define DRM_VC4_GET_HANG_STATE 0x06
40#define DRM_VC4_GET_PARAM 0x07
40 41
41#define DRM_IOCTL_VC4_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl) 42#define DRM_IOCTL_VC4_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl)
42#define DRM_IOCTL_VC4_WAIT_SEQNO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno) 43#define DRM_IOCTL_VC4_WAIT_SEQNO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno)
@@ -45,6 +46,7 @@ extern "C" {
45#define DRM_IOCTL_VC4_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_MMAP_BO, struct drm_vc4_mmap_bo) 46#define DRM_IOCTL_VC4_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_MMAP_BO, struct drm_vc4_mmap_bo)
46#define DRM_IOCTL_VC4_CREATE_SHADER_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_SHADER_BO, struct drm_vc4_create_shader_bo) 47#define DRM_IOCTL_VC4_CREATE_SHADER_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_SHADER_BO, struct drm_vc4_create_shader_bo)
47#define DRM_IOCTL_VC4_GET_HANG_STATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_HANG_STATE, struct drm_vc4_get_hang_state) 48#define DRM_IOCTL_VC4_GET_HANG_STATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_HANG_STATE, struct drm_vc4_get_hang_state)
49#define DRM_IOCTL_VC4_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_PARAM, struct drm_vc4_get_param)
48 50
49struct drm_vc4_submit_rcl_surface { 51struct drm_vc4_submit_rcl_surface {
50 __u32 hindex; /* Handle index, or ~0 if not present. */ 52 __u32 hindex; /* Handle index, or ~0 if not present. */
@@ -280,6 +282,17 @@ struct drm_vc4_get_hang_state {
280 __u32 pad[16]; 282 __u32 pad[16];
281}; 283};
282 284
285#define DRM_VC4_PARAM_V3D_IDENT0 0
286#define DRM_VC4_PARAM_V3D_IDENT1 1
287#define DRM_VC4_PARAM_V3D_IDENT2 2
288#define DRM_VC4_PARAM_SUPPORTS_BRANCHES 3
289
290struct drm_vc4_get_param {
291 __u32 param;
292 __u32 pad;
293 __u64 value;
294};
295
283#if defined(__cplusplus) 296#if defined(__cplusplus)
284} 297}
285#endif 298#endif
diff --git a/include/uapi/drm/vgem_drm.h b/include/uapi/drm/vgem_drm.h
new file mode 100644
index 000000000000..bf66f5db6da8
--- /dev/null
+++ b/include/uapi/drm/vgem_drm.h
@@ -0,0 +1,62 @@
1/*
2 * Copyright 2016 Intel Corporation
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
15 * of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
20 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 *
25 */
26
27#ifndef _UAPI_VGEM_DRM_H_
28#define _UAPI_VGEM_DRM_H_
29
30#include "drm.h"
31
32#if defined(__cplusplus)
33extern "C" {
34#endif
35
36/* Please note that modifications to all structs defined here are
37 * subject to backwards-compatibility constraints.
38 */
39#define DRM_VGEM_FENCE_ATTACH 0x1
40#define DRM_VGEM_FENCE_SIGNAL 0x2
41
42#define DRM_IOCTL_VGEM_FENCE_ATTACH DRM_IOWR( DRM_COMMAND_BASE + DRM_VGEM_FENCE_ATTACH, struct drm_vgem_fence_attach)
43#define DRM_IOCTL_VGEM_FENCE_SIGNAL DRM_IOW( DRM_COMMAND_BASE + DRM_VGEM_FENCE_SIGNAL, struct drm_vgem_fence_signal)