Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next

Pull networking updates from David Miller:

 1) Add TX fast path in mac80211, from Johannes Berg.

 2) Add TSO/GRO support to ibmveth, from Thomas Falcon

 3) Move away from cached routes in ipv6, just like ipv4, from Martin
    KaFai Lau.

 4) Lots of new rhashtable tests, from Thomas Graf.

 5) Run ingress qdisc lockless, from Alexei Starovoitov.

 6) Allow servers to fetch TCP packet headers for SYN packets of new
    connections, for fingerprinting.  From Eric Dumazet.

 7) Add mode parameter to pktgen, for testing receive.  From Alexei
    Starovoitov.

 8) Cache access optimizations via simplifications of build_skb(), from
    Alexander Duyck.

 9) Move page frag allocator under mm/, also from Alexander.

10) Add xmit_more support to hv_netvsc, from KY Srinivasan.

11) Add a counter guard in case we try to perform endless reclassify
    loops in the packet scheduler.

12) Extern flow dissector to be programmable and use it in new "Flower"
    classifier.  From Jiri Pirko.

13) AF_PACKET fanout rollover fixes, performance improvements, and new
    statistics.  From Willem de Bruijn.

14) Add netdev driver for GENEVE tunnels, from John W Linville.

15) Add ingress netfilter hooks and filtering, from Pablo Neira Ayuso.

16) Fix handling of epoll edge triggers in TCP, from Eric Dumazet.

17) Add an ECN retry fallback for the initial TCP handshake, from Daniel
    Borkmann.

18) Add tail call support to BPF, from Alexei Starovoitov.

19) Add several pktgen helper scripts, from Jesper Dangaard Brouer.

20) Add zerocopy support to AF_UNIX, from Hannes Frederic Sowa.

21) Favor even port numbers for allocation to connect() requests, and
    odd port numbers for bind(0), in an effort to help avoid
    ip_local_port_range exhaustion.  From Eric Dumazet.

22) Add Cavium ThunderX driver, from Sunil Goutham.

23) Allow bpf programs to access skb_iif and dev->ifindex SKB metadata,
    from Alexei Starovoitov.

24) Add support for T6 chips in cxgb4vf driver, from Hariprasad Shenai.

25) Double TCP Small Queues default to 256K to accomodate situations
    like the XEN driver and wireless aggregation.  From Wei Liu.

26) Add more entropy inputs to flow dissector, from Tom Herbert.

27) Add CDG congestion control algorithm to TCP, from Kenneth Klette
    Jonassen.

28) Convert ipset over to RCU locking, from Jozsef Kadlecsik.

29) Track and act upon link status of ipv4 route nexthops, from Andy
    Gospodarek.

* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next: (1670 commits)
  bridge: vlan: flush the dynamically learned entries on port vlan delete
  bridge: multicast: add a comment to br_port_state_selection about blocking state
  net: inet_diag: export IPV6_V6ONLY sockopt
  stmmac: troubleshoot unexpected bits in des0 & des1
  net: ipv4 sysctl option to ignore routes when nexthop link is down
  net: track link-status of ipv4 nexthops
  net: switchdev: ignore unsupported bridge flags
  net: Cavium: Fix MAC address setting in shutdown state
  drivers: net: xgene: fix for ACPI support without ACPI
  ip: report the original address of ICMP messages
  net/mlx5e: Prefetch skb data on RX
  net/mlx5e: Pop cq outside mlx5e_get_cqe
  net/mlx5e: Remove mlx5e_cq.sqrq back-pointer
  net/mlx5e: Remove extra spaces
  net/mlx5e: Avoid TX CQE generation if more xmit packets expected
  net/mlx5e: Avoid redundant dev_kfree_skb() upon NOP completion
  net/mlx5e: Remove re-assignment of wq type in mlx5e_enable_rq()
  net/mlx5e: Use skb_shinfo(skb)->gso_segs rather than counting them
  net/mlx5e: Static mapping of netdev priv resources to/from netdev TX queues
  net/mlx4_en: Use HW counters for rx/tx bytes/packets in PF device
  ...

51 files changed, 7598 insertions, 349 deletions

diff --git a/include/linux/bcma/bcma.h b/include/linux/bcma/bcma.h
index e34f906647d3..2ff4a9961e1d 100644
--- a/include/linux/bcma/bcma.h
+++ b/include/linux/bcma/bcma.h
@@ -305,6 +305,15 @@ int __bcma_driver_register(struct bcma_driver *drv, struct module *owner);
 
 extern void bcma_driver_unregister(struct bcma_driver *drv);
 
+/* module_bcma_driver() - Helper macro for drivers that don't do
+ * anything special in module init/exit.  This eliminates a lot of
+ * boilerplate.  Each module may only use this macro once, and
+ * calling it replaces module_init() and module_exit()
+ */
+#define module_bcma_driver(__bcma_driver) \
+        module_driver(__bcma_driver, bcma_driver_register, \
+                        bcma_driver_unregister)
+
 /* Set a fallback SPROM.
  * See kdoc at the function definition for complete documentation. */
 extern int bcma_arch_register_fallback_sprom(
diff --git a/include/linux/bcma/bcma_driver_pci.h b/include/linux/bcma/bcma_driver_pci.h
index 5ba6918ca20b..9657f11d48a7 100644
--- a/include/linux/bcma/bcma_driver_pci.h
+++ b/include/linux/bcma/bcma_driver_pci.h
@@ -246,7 +246,18 @@ static inline void bcma_core_pci_power_save(struct bcma_bus *bus, bool up)
 }
 #endif
 
+#ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
 extern int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev);
 extern int bcma_core_pci_plat_dev_init(struct pci_dev *dev);
+#else
+static inline int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev)
+{
+        return -ENOTSUPP;
+}
+static inline int bcma_core_pci_plat_dev_init(struct pci_dev *dev)
+{
+        return -ENOTSUPP;
+}
+#endif
 
 #endif /* LINUX_BCMA_DRIVER_PCI_H_ */
diff --git a/include/linux/bpf.h b/include/linux/bpf.h
index d5cda067115a..4383476a0d48 100644
--- a/include/linux/bpf.h
+++ b/include/linux/bpf.h
@@ -105,7 +105,8 @@ struct bpf_verifier_ops {
          */
         bool (*is_valid_access)(int off, int size, enum bpf_access_type type);
 
-        u32 (*convert_ctx_access)(int dst_reg, int src_reg, int ctx_off,
+        u32 (*convert_ctx_access)(enum bpf_access_type type, int dst_reg,
+                                  int src_reg, int ctx_off,
                                   struct bpf_insn *insn);
 };
 
@@ -123,15 +124,41 @@ struct bpf_prog_aux {
         const struct bpf_verifier_ops *ops;
         struct bpf_map **used_maps;
         struct bpf_prog *prog;
-        struct work_struct work;
+        union {
+                struct work_struct work;
+                struct rcu_head rcu;
+        };
 };
 
+struct bpf_array {
+        struct bpf_map map;
+        u32 elem_size;
+        /* 'ownership' of prog_array is claimed by the first program that
+         * is going to use this map or by the first program which FD is stored
+         * in the map to make sure that all callers and callees have the same
+         * prog_type and JITed flag
+         */
+        enum bpf_prog_type owner_prog_type;
+        bool owner_jited;
+        union {
+                char value[0] __aligned(8);
+                struct bpf_prog *prog[0] __aligned(8);
+        };
+};
+#define MAX_TAIL_CALL_CNT 32
+
+u64 bpf_tail_call(u64 ctx, u64 r2, u64 index, u64 r4, u64 r5);
+void bpf_prog_array_map_clear(struct bpf_map *map);
+bool bpf_prog_array_compatible(struct bpf_array *array, const struct bpf_prog *fp);
+const struct bpf_func_proto *bpf_get_trace_printk_proto(void);
+
 #ifdef CONFIG_BPF_SYSCALL
 void bpf_register_prog_type(struct bpf_prog_type_list *tl);
 void bpf_register_map_type(struct bpf_map_type_list *tl);
 
 struct bpf_prog *bpf_prog_get(u32 ufd);
 void bpf_prog_put(struct bpf_prog *prog);
+void bpf_prog_put_rcu(struct bpf_prog *prog);
 
 struct bpf_map *bpf_map_get(struct fd f);
 void bpf_map_put(struct bpf_map *map);
@@ -160,5 +187,10 @@ extern const struct bpf_func_proto bpf_map_delete_elem_proto;
 
 extern const struct bpf_func_proto bpf_get_prandom_u32_proto;
 extern const struct bpf_func_proto bpf_get_smp_processor_id_proto;
+extern const struct bpf_func_proto bpf_tail_call_proto;
+extern const struct bpf_func_proto bpf_ktime_get_ns_proto;
+extern const struct bpf_func_proto bpf_get_current_pid_tgid_proto;
+extern const struct bpf_func_proto bpf_get_current_uid_gid_proto;
+extern const struct bpf_func_proto bpf_get_current_comm_proto;
 
 #endif /* _LINUX_BPF_H */
diff --git a/include/linux/brcmphy.h b/include/linux/brcmphy.h
index 656da2a12ffe..697ca7795bd9 100644
--- a/include/linux/brcmphy.h
+++ b/include/linux/brcmphy.h
@@ -1,6 +1,13 @@
 #ifndef _LINUX_BRCMPHY_H
 #define _LINUX_BRCMPHY_H
 
+#include <linux/phy.h>
+
+/* All Broadcom Ethernet switches have a pseudo-PHY at address 30 which is used
+ * to configure the switch internal registers via MDIO accesses.
+ */
+#define BRCM_PSEUDO_PHY_ADDR           30
+
 #define PHY_ID_BCM50610                 0x0143bd60
 #define PHY_ID_BCM50610M                0x0143bd70
 #define PHY_ID_BCM5241                  0x0143bc30
diff --git a/include/linux/etherdevice.h b/include/linux/etherdevice.h
index 606563ef8a72..9012f8775208 100644
--- a/include/linux/etherdevice.h
+++ b/include/linux/etherdevice.h
@@ -110,7 +110,29 @@ static inline bool is_zero_ether_addr(const u8 *addr)
  */
 static inline bool is_multicast_ether_addr(const u8 *addr)
 {
-        return 0x01 & addr[0];
+#if defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
+        u32 a = *(const u32 *)addr;
+#else
+        u16 a = *(const u16 *)addr;
+#endif
+#ifdef __BIG_ENDIAN
+        return 0x01 & (a >> ((sizeof(a) * 8) - 8));
+#else
+        return 0x01 & a;
+#endif
+}
+
+static inline bool is_multicast_ether_addr_64bits(const u8 addr[6+2])
+{
+#if defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS) && BITS_PER_LONG == 64
+#ifdef __BIG_ENDIAN
+        return 0x01 & ((*(const u64 *)addr) >> 56);
+#else
+        return 0x01 & (*(const u64 *)addr);
+#endif
+#else
+        return is_multicast_ether_addr(addr);
+#endif
 }
 
 /**
@@ -169,6 +191,24 @@ static inline bool is_valid_ether_addr(const u8 *addr)
 }
 
 /**
+ * eth_proto_is_802_3 - Determine if a given Ethertype/length is a protocol
+ * @proto: Ethertype/length value to be tested
+ *
+ * Check that the value from the Ethertype/length field is a valid Ethertype.
+ *
+ * Return true if the valid is an 802.3 supported Ethertype.
+ */
+static inline bool eth_proto_is_802_3(__be16 proto)
+{
+#ifndef __BIG_ENDIAN
+        /* if CPU is little endian mask off bits representing LSB */
+        proto &= htons(0xFF00);
+#endif
+        /* cast both to u16 and compare since LSB can be ignored */
+        return (__force u16)proto >= (__force u16)htons(ETH_P_802_3_MIN);
+}
+
+/**
  * eth_random_addr - Generate software assigned random Ethernet address
  * @addr: Pointer to a six-byte array containing the Ethernet address
  *
diff --git a/include/linux/filter.h b/include/linux/filter.h
index fa11b3a367be..17724f6ea983 100644
--- a/include/linux/filter.h
+++ b/include/linux/filter.h
@@ -207,6 +207,16 @@ struct bpf_prog_aux;
                 .off   = OFF,                                   \
                 .imm   = 0 })
 
+/* Atomic memory add, *(uint *)(dst_reg + off16) += src_reg */
+
+#define BPF_STX_XADD(SIZE, DST, SRC, OFF)                       \
+        ((struct bpf_insn) {                                    \
+                .code  = BPF_STX | BPF_SIZE(SIZE) | BPF_XADD,   \
+                .dst_reg = DST,                                 \
+                .src_reg = SRC,                                 \
+                .off   = OFF,                                   \
+                .imm   = 0 })
+
 /* Memory store, *(uint *) (dst_reg + off16) = imm32 */
 
 #define BPF_ST_MEM(SIZE, DST, OFF, IMM)                         \
@@ -267,6 +277,14 @@ struct bpf_prog_aux;
                 .off   = 0,                                     \
                 .imm   = 0 })
 
+/* Internal classic blocks for direct assignment */
+
+#define __BPF_STMT(CODE, K)                                     \
+        ((struct sock_filter) BPF_STMT(CODE, K))
+
+#define __BPF_JUMP(CODE, K, JT, JF)                             \
+        ((struct sock_filter) BPF_JUMP(CODE, K, JT, JF))
+
 #define bytes_to_bpf_size(bytes)                                \
 ({                                                              \
         int bpf_size = -EINVAL;                                 \
@@ -360,12 +378,9 @@ static inline void bpf_prog_unlock_ro(struct bpf_prog *fp)
 
 int sk_filter(struct sock *sk, struct sk_buff *skb);
 
-void bpf_prog_select_runtime(struct bpf_prog *fp);
+int bpf_prog_select_runtime(struct bpf_prog *fp);
 void bpf_prog_free(struct bpf_prog *fp);
 
-int bpf_convert_filter(struct sock_filter *prog, int len,
-                       struct bpf_insn *new_prog, int *new_len);
-
 struct bpf_prog *bpf_prog_alloc(unsigned int size, gfp_t gfp_extra_flags);
 struct bpf_prog *bpf_prog_realloc(struct bpf_prog *fp_old, unsigned int size,
                                   gfp_t gfp_extra_flags);
@@ -377,14 +392,17 @@ static inline void bpf_prog_unlock_free(struct bpf_prog *fp)
         __bpf_prog_free(fp);
 }
 
+typedef int (*bpf_aux_classic_check_t)(struct sock_filter *filter,
+                                       unsigned int flen);
+
 int bpf_prog_create(struct bpf_prog **pfp, struct sock_fprog_kern *fprog);
+int bpf_prog_create_from_user(struct bpf_prog **pfp, struct sock_fprog *fprog,
+                              bpf_aux_classic_check_t trans);
 void bpf_prog_destroy(struct bpf_prog *fp);
 
 int sk_attach_filter(struct sock_fprog *fprog, struct sock *sk);
 int sk_attach_bpf(u32 ufd, struct sock *sk);
 int sk_detach_filter(struct sock *sk);
-
-int bpf_check_classic(const struct sock_filter *filter, unsigned int flen);
 int sk_get_filter(struct sock *sk, struct sock_filter __user *filter,
                   unsigned int len);
 
diff --git a/include/linux/gfp.h b/include/linux/gfp.h
index 15928f0647e4..6ba7cf23748f 100644
--- a/include/linux/gfp.h
+++ b/include/linux/gfp.h
@@ -368,6 +368,11 @@ extern void free_pages(unsigned long addr, unsigned int order);
 extern void free_hot_cold_page(struct page *page, bool cold);
 extern void free_hot_cold_page_list(struct list_head *list, bool cold);
 
+struct page_frag_cache;
+extern void *__alloc_page_frag(struct page_frag_cache *nc,
+                               unsigned int fragsz, gfp_t gfp_mask);
+extern void __free_page_frag(void *addr);
+
 extern void __free_kmem_pages(struct page *page, unsigned int order);
 extern void free_kmem_pages(unsigned long addr, unsigned int order);
 
diff --git a/include/linux/ieee802154.h b/include/linux/ieee802154.h
index 8872ca103d06..1dc1f4ed4001 100644
--- a/include/linux/ieee802154.h
+++ b/include/linux/ieee802154.h
@@ -225,15 +225,13 @@ static inline bool ieee802154_is_valid_psdu_len(const u8 len)
  * ieee802154_is_valid_psdu_len - check if extended addr is valid
  * @addr: extended addr to check
  */
-static inline bool ieee802154_is_valid_extended_addr(const __le64 addr)
+static inline bool ieee802154_is_valid_extended_unicast_addr(const __le64 addr)
 {
-        /* These EUI-64 addresses are reserved by IEEE. 0xffffffffffffffff
-         * is used internally as extended to short address broadcast mapping.
-         * This is currently a workaround because neighbor discovery can't
-         * deal with short addresses types right now.
+        /* Bail out if the address is all zero, or if the group
+         * address bit is set.
          */
         return ((addr != cpu_to_le64(0x0000000000000000ULL)) &&
-                (addr != cpu_to_le64(0xffffffffffffffffULL)));
+                !(addr & cpu_to_le64(0x0100000000000000ULL)));
 }
 
 /**
@@ -244,9 +242,9 @@ static inline void ieee802154_random_extended_addr(__le64 *addr)
 {
         get_random_bytes(addr, IEEE802154_EXTENDED_ADDR_LEN);
 
-        /* toggle some bit if we hit an invalid extended addr */
-        if (!ieee802154_is_valid_extended_addr(*addr))
-                ((u8 *)addr)[IEEE802154_EXTENDED_ADDR_LEN - 1] ^= 0x01;
+        /* clear the group bit, and set the locally administered bit */
+        ((u8 *)addr)[IEEE802154_EXTENDED_ADDR_LEN - 1] &= ~0x01;
+        ((u8 *)addr)[IEEE802154_EXTENDED_ADDR_LEN - 1] |= 0x02;
 }
 
 #endif /* LINUX_IEEE802154_H */
diff --git a/include/linux/if_link.h b/include/linux/if_link.h
index da4929927f69..ae5d0d22955d 100644
--- a/include/linux/if_link.h
+++ b/include/linux/if_link.h
@@ -5,6 +5,15 @@
 
 
 /* We don't want this structure exposed to user space */
+struct ifla_vf_stats {
+        __u64 rx_packets;
+        __u64 tx_packets;
+        __u64 rx_bytes;
+        __u64 tx_bytes;
+        __u64 broadcast;
+        __u64 multicast;
+};
+
 struct ifla_vf_info {
         __u32 vf;
         __u8 mac[32];
diff --git a/include/linux/if_macvlan.h b/include/linux/if_macvlan.h
index 6f6929ea8a0c..a4ccc3122f93 100644
--- a/include/linux/if_macvlan.h
+++ b/include/linux/if_macvlan.h
@@ -29,7 +29,7 @@ struct macvtap_queue;
  * Maximum times a macvtap device can be opened. This can be used to
  * configure the number of receive queue, e.g. for multiqueue virtio.
  */
-#define MAX_MACVTAP_QUEUES      16
+#define MAX_MACVTAP_QUEUES      256
 
 #define MACVLAN_MC_FILTER_BITS  8
 #define MACVLAN_MC_FILTER_SZ    (1 << MACVLAN_MC_FILTER_BITS)
diff --git a/include/linux/if_pppox.h b/include/linux/if_pppox.h
index 66a7d7600f43..b49cf923becc 100644
--- a/include/linux/if_pppox.h
+++ b/include/linux/if_pppox.h
@@ -74,7 +74,7 @@ static inline struct sock *sk_pppox(struct pppox_sock *po)
 struct module;
 
 struct pppox_proto {
-        int             (*create)(struct net *net, struct socket *sock);
+        int             (*create)(struct net *net, struct socket *sock, int kern);
         int             (*ioctl)(struct socket *sock, unsigned int cmd,
                                  unsigned long arg);
         struct module   *owner;
diff --git a/include/linux/if_vlan.h b/include/linux/if_vlan.h
index 920e4457ce6e..67ce5bd3b56a 100644
--- a/include/linux/if_vlan.h
+++ b/include/linux/if_vlan.h
@@ -416,7 +416,7 @@ static inline void __vlan_hwaccel_put_tag(struct sk_buff *skb,
 /**
  * __vlan_get_tag - get the VLAN ID that is part of the payload
  * @skb: skbuff to query
- * @vlan_tci: buffer to store vlaue
+ * @vlan_tci: buffer to store value
  *
  * Returns error if the skb is not of VLAN type
  */
@@ -435,7 +435,7 @@ static inline int __vlan_get_tag(const struct sk_buff *skb, u16 *vlan_tci)
 /**
  * __vlan_hwaccel_get_tag - get the VLAN ID that is in @skb->cb[]
  * @skb: skbuff to query
- * @vlan_tci: buffer to store vlaue
+ * @vlan_tci: buffer to store value
  *
  * Returns error if @skb->vlan_tci is not set correctly
  */
@@ -456,7 +456,7 @@ static inline int __vlan_hwaccel_get_tag(const struct sk_buff *skb,
 /**
  * vlan_get_tag - get the VLAN ID from the skb
  * @skb: skbuff to query
- * @vlan_tci: buffer to store vlaue
+ * @vlan_tci: buffer to store value
  *
  * Returns error if the skb is not VLAN tagged
  */
@@ -539,7 +539,7 @@ static inline void vlan_set_encap_proto(struct sk_buff *skb,
          */
 
         proto = vhdr->h_vlan_encapsulated_proto;
-        if (ntohs(proto) >= ETH_P_802_3_MIN) {
+        if (eth_proto_is_802_3(proto)) {
                 skb->protocol = proto;
                 return;
         }
@@ -628,4 +628,24 @@ static inline netdev_features_t vlan_features_check(const struct sk_buff *skb,
         return features;
 }
 
+/**
+ * compare_vlan_header - Compare two vlan headers
+ * @h1: Pointer to vlan header
+ * @h2: Pointer to vlan header
+ *
+ * Compare two vlan headers, returns 0 if equal.
+ *
+ * Please note that alignment of h1 & h2 are only guaranteed to be 16 bits.
+ */
+static inline unsigned long compare_vlan_header(const struct vlan_hdr *h1,
+                                                const struct vlan_hdr *h2)
+{
+#if defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
+        return *(u32 *)h1 ^ *(u32 *)h2;
+#else
+        return ((__force u32)h1->h_vlan_TCI ^ (__force u32)h2->h_vlan_TCI) |
+               ((__force u32)h1->h_vlan_encapsulated_proto ^
+                (__force u32)h2->h_vlan_encapsulated_proto);
+#endif
+}
 #endif /* !(_LINUX_IF_VLAN_H_) */
diff --git a/include/linux/igmp.h b/include/linux/igmp.h
index 2c677afeea47..193ad488d3e2 100644
--- a/include/linux/igmp.h
+++ b/include/linux/igmp.h
@@ -130,5 +130,6 @@ extern void ip_mc_unmap(struct in_device *);
 extern void ip_mc_remap(struct in_device *);
 extern void ip_mc_dec_group(struct in_device *in_dev, __be32 addr);
 extern void ip_mc_inc_group(struct in_device *in_dev, __be32 addr);
+int ip_mc_check_igmp(struct sk_buff *skb, struct sk_buff **skb_trimmed);
 
 #endif
diff --git a/include/linux/inet_diag.h b/include/linux/inet_diag.h
index ac48b10c9395..0e707f0c1a3e 100644
--- a/include/linux/inet_diag.h
+++ b/include/linux/inet_diag.h
@@ -24,6 +24,7 @@ struct inet_diag_handler {
                                           struct inet_diag_msg *r,
                                           void *info);
         __u16           idiag_type;
+        __u16           idiag_info_size;
 };
 
 struct inet_connection_sock;
diff --git a/include/linux/inetdevice.h b/include/linux/inetdevice.h
index 0a21fbefdfbe..a4328cea376a 100644
--- a/include/linux/inetdevice.h
+++ b/include/linux/inetdevice.h
@@ -120,6 +120,9 @@ static inline void ipv4_devconf_setall(struct in_device *in_dev)
          || (!IN_DEV_FORWARD(in_dev) && \
           IN_DEV_ORCONF((in_dev), ACCEPT_REDIRECTS)))
 
+#define IN_DEV_IGNORE_ROUTES_WITH_LINKDOWN(in_dev) \
+        IN_DEV_CONF_GET((in_dev), IGNORE_ROUTES_WITH_LINKDOWN)
+
 #define IN_DEV_ARPFILTER(in_dev)        IN_DEV_ORCONF((in_dev), ARPFILTER)
 #define IN_DEV_ARP_ACCEPT(in_dev)       IN_DEV_ORCONF((in_dev), ARP_ACCEPT)
 #define IN_DEV_ARP_ANNOUNCE(in_dev)     IN_DEV_MAXCONF((in_dev), ARP_ANNOUNCE)
diff --git a/include/linux/mdio-gpio.h b/include/linux/mdio-gpio.h
index 66c30a763b10..11f00cdabe3d 100644
--- a/include/linux/mdio-gpio.h
+++ b/include/linux/mdio-gpio.h
@@ -23,7 +23,8 @@ struct mdio_gpio_platform_data {
         bool mdio_active_low;
         bool mdo_active_low;
 
-        unsigned int phy_mask;
+        u32 phy_mask;
+        u32 phy_ignore_ta_mask;
         int irqs[PHY_MAX_ADDR];
         /* reset callback */
         int (*reset)(struct mii_bus *bus);
diff --git a/include/linux/mlx4/cmd.h b/include/linux/mlx4/cmd.h
index f62e7cf227c6..58391f2e0414 100644
--- a/include/linux/mlx4/cmd.h
+++ b/include/linux/mlx4/cmd.h
@@ -35,6 +35,8 @@
 
 #include <linux/dma-mapping.h>
 #include <linux/if_link.h>
+#include <linux/mlx4/device.h>
+#include <linux/netdevice.h>
 
 enum {
         /* initialization and general commands */
@@ -300,6 +302,10 @@ static inline int mlx4_cmd_imm(struct mlx4_dev *dev, u64 in_param, u64 *out_para
 struct mlx4_cmd_mailbox *mlx4_alloc_cmd_mailbox(struct mlx4_dev *dev);
 void mlx4_free_cmd_mailbox(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox);
 
+int mlx4_get_counter_stats(struct mlx4_dev *dev, int counter_index,
+                           struct mlx4_counter *counter_stats, int reset);
+int mlx4_get_vf_stats(struct mlx4_dev *dev, int port, int vf_idx,
+                      struct ifla_vf_stats *vf_stats);
 u32 mlx4_comm_get_version(void);
 int mlx4_set_vf_mac(struct mlx4_dev *dev, int port, int vf, u64 mac);
 int mlx4_set_vf_vlan(struct mlx4_dev *dev, int port, int vf, u16 vlan, u8 qos);
diff --git a/include/linux/mlx4/device.h b/include/linux/mlx4/device.h
index f94984fb8bb2..fd13c1ce3b4a 100644
--- a/include/linux/mlx4/device.h
+++ b/include/linux/mlx4/device.h
@@ -46,8 +46,9 @@
 
 #define MAX_MSIX_P_PORT         17
 #define MAX_MSIX                64
-#define MSIX_LEGACY_SZ          4
 #define MIN_MSIX_P_PORT         5
+#define MLX4_IS_LEGACY_EQ_MODE(dev_cap) ((dev_cap).num_comp_vectors < \
+                                         (dev_cap).num_ports * MIN_MSIX_P_PORT)
 
 #define MLX4_MAX_100M_UNITS_VAL         255     /*
                                                  * work around: can't set values
@@ -528,7 +529,6 @@ struct mlx4_caps {
         int                     num_eqs;
         int                     reserved_eqs;
         int                     num_comp_vectors;
-        int                     comp_pool;
         int                     num_mpts;
         int                     max_fmr_maps;
         int                     num_mtts;
@@ -771,6 +771,14 @@ union mlx4_ext_av {
         struct mlx4_eth_av      eth;
 };
 
+/* Counters should be saturate once they reach their maximum value */
+#define ASSIGN_32BIT_COUNTER(counter, value) do {       \
+        if ((value) > U32_MAX)                          \
+                counter = cpu_to_be32(U32_MAX);         \
+        else                                            \
+                counter = cpu_to_be32(value);           \
+} while (0)
+
 struct mlx4_counter {
         u8      reserved1[3];
         u8      counter_mode;
@@ -963,6 +971,7 @@ struct mlx4_mad_ifc {
                         ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
 
 #define MLX4_INVALID_SLAVE_ID   0xFF
+#define MLX4_SINK_COUNTER_INDEX(dev)    (dev->caps.max_counters - 1)
 
 void handle_port_mgmt_change_event(struct work_struct *work);
 
@@ -1338,10 +1347,13 @@ void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
 int mlx4_SYNC_TPT(struct mlx4_dev *dev);
 int mlx4_test_interrupts(struct mlx4_dev *dev);
-int mlx4_assign_eq(struct mlx4_dev *dev, char *name, struct cpu_rmap *rmap,
-                   int *vector);
+u32 mlx4_get_eqs_per_port(struct mlx4_dev *dev, u8 port);
+bool mlx4_is_eq_vector_valid(struct mlx4_dev *dev, u8 port, int vector);
+struct cpu_rmap *mlx4_get_cpu_rmap(struct mlx4_dev *dev, int port);
+int mlx4_assign_eq(struct mlx4_dev *dev, u8 port, int *vector);
 void mlx4_release_eq(struct mlx4_dev *dev, int vec);
 
+int mlx4_is_eq_shared(struct mlx4_dev *dev, int vector);
 int mlx4_eq_get_irq(struct mlx4_dev *dev, int vec);
 
 int mlx4_get_phys_port_id(struct mlx4_dev *dev);
@@ -1350,6 +1362,7 @@ int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port);
 
 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
+int mlx4_get_default_counter_index(struct mlx4_dev *dev, int port);
 
 void mlx4_set_admin_guid(struct mlx4_dev *dev, __be64 guid, int entry,
                          int port);
diff --git a/include/linux/mlx5/cq.h b/include/linux/mlx5/cq.h
index 2695ced222df..abc4767695e4 100644
--- a/include/linux/mlx5/cq.h
+++ b/include/linux/mlx5/cq.h
@@ -169,6 +169,9 @@ int mlx5_core_query_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq,
                        struct mlx5_query_cq_mbox_out *out);
 int mlx5_core_modify_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq,
                         struct mlx5_modify_cq_mbox_in *in, int in_sz);
+int mlx5_core_modify_cq_moderation(struct mlx5_core_dev *dev,
+                                   struct mlx5_core_cq *cq, u16 cq_period,
+                                   u16 cq_max_count);
 int mlx5_debug_cq_add(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq);
 void mlx5_debug_cq_remove(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq);
 
diff --git a/include/linux/mlx5/device.h b/include/linux/mlx5/device.h
index abf65c790421..b943cd9e2097 100644
--- a/include/linux/mlx5/device.h
+++ b/include/linux/mlx5/device.h
@@ -35,6 +35,7 @@
 
 #include <linux/types.h>
 #include <rdma/ib_verbs.h>
+#include <linux/mlx5/mlx5_ifc.h>
 
 #if defined(__LITTLE_ENDIAN)
 #define MLX5_SET_HOST_ENDIANNESS        0
@@ -58,6 +59,8 @@
 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
+#define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
+#define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32)
 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
 
@@ -70,6 +73,14 @@
                      << __mlx5_dw_bit_off(typ, fld))); \
 } while (0)
 
+#define MLX5_SET_TO_ONES(typ, p, fld) do { \
+        BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32);             \
+        *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
+        cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
+                     (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \
+                     << __mlx5_dw_bit_off(typ, fld))); \
+} while (0)
+
 #define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\
 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
 __mlx5_mask(typ, fld))
@@ -88,6 +99,12 @@ __mlx5_mask(typ, fld))
 
 #define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld)))
 
+#define MLX5_GET64_PR(typ, p, fld) ({ \
+        u64 ___t = MLX5_GET64(typ, p, fld); \
+        pr_debug(#fld " = 0x%llx\n", ___t); \
+        ___t; \
+})
+
 enum {
         MLX5_MAX_COMMANDS               = 32,
         MLX5_CMD_DATA_BLOCK_SIZE        = 512,
@@ -115,6 +132,10 @@ enum {
 };
 
 enum {
+        MLX5_HW_START_PADDING = MLX5_INLINE_SEG,
+};
+
+enum {
         MLX5_MIN_PKEY_TABLE_SIZE = 128,
         MLX5_MAX_LOG_PKEY_TABLE  = 5,
 };
@@ -264,6 +285,7 @@ enum {
         MLX5_OPCODE_RDMA_WRITE_IMM      = 0x09,
         MLX5_OPCODE_SEND                = 0x0a,
         MLX5_OPCODE_SEND_IMM            = 0x0b,
+        MLX5_OPCODE_LSO                 = 0x0e,
         MLX5_OPCODE_RDMA_READ           = 0x10,
         MLX5_OPCODE_ATOMIC_CS           = 0x11,
         MLX5_OPCODE_ATOMIC_FA           = 0x12,
@@ -312,13 +334,6 @@ enum {
         MLX5_CAP_OFF_CMDIF_CSUM         = 46,
 };
 
-enum {
-        HCA_CAP_OPMOD_GET_MAX   = 0,
-        HCA_CAP_OPMOD_GET_CUR   = 1,
-        HCA_CAP_OPMOD_GET_ODP_MAX = 4,
-        HCA_CAP_OPMOD_GET_ODP_CUR = 5
-};
-
 struct mlx5_inbox_hdr {
         __be16          opcode;
         u8              rsvd[4];
@@ -541,6 +556,10 @@ struct mlx5_cmd_prot_block {
         u8              sig;
 };
 
+enum {
+        MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5,
+};
+
 struct mlx5_err_cqe {
         u8      rsvd0[32];
         __be32  srqn;
@@ -554,13 +573,22 @@ struct mlx5_err_cqe {
 };
 
 struct mlx5_cqe64 {
-        u8              rsvd0[17];
+        u8              rsvd0[4];
+        u8              lro_tcppsh_abort_dupack;
+        u8              lro_min_ttl;
+        __be16          lro_tcp_win;
+        __be32          lro_ack_seq_num;
+        __be32          rss_hash_result;
+        u8              rss_hash_type;
         u8              ml_path;
-        u8              rsvd20[4];
+        u8              rsvd20[2];
+        __be16          check_sum;
         __be16          slid;
         __be32          flags_rqpn;
-        u8              rsvd28[4];
-        __be32          srqn;
+        u8              hds_ip_ext;
+        u8              l4_hdr_type_etc;
+        __be16          vlan_info;
+        __be32          srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */
         __be32          imm_inval_pkey;
         u8              rsvd40[4];
         __be32          byte_cnt;
@@ -571,6 +599,40 @@ struct mlx5_cqe64 {
         u8              op_own;
 };
 
+static inline int get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe)
+{
+        return (cqe->lro_tcppsh_abort_dupack >> 6) & 1;
+}
+
+static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe)
+{
+        return (cqe->l4_hdr_type_etc >> 4) & 0x7;
+}
+
+static inline int cqe_has_vlan(struct mlx5_cqe64 *cqe)
+{
+        return !!(cqe->l4_hdr_type_etc & 0x1);
+}
+
+enum {
+        CQE_L4_HDR_TYPE_NONE                    = 0x0,
+        CQE_L4_HDR_TYPE_TCP_NO_ACK              = 0x1,
+        CQE_L4_HDR_TYPE_UDP                     = 0x2,
+        CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA         = 0x3,
+        CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA        = 0x4,
+};
+
+enum {
+        CQE_RSS_HTYPE_IP        = 0x3 << 6,
+        CQE_RSS_HTYPE_L4        = 0x3 << 2,
+};
+
+enum {
+        CQE_L2_OK       = 1 << 0,
+        CQE_L3_OK       = 1 << 1,
+        CQE_L4_OK       = 1 << 2,
+};
+
 struct mlx5_sig_err_cqe {
         u8              rsvd0[16];
         __be32          expected_trans_sig;
@@ -996,4 +1058,135 @@ struct mlx5_destroy_psv_out {
         u8                      rsvd[8];
 };
 
+#define MLX5_CMD_OP_MAX 0x920
+
+enum {
+        VPORT_STATE_DOWN                = 0x0,
+        VPORT_STATE_UP                  = 0x1,
+};
+
+enum {
+        MLX5_L3_PROT_TYPE_IPV4          = 0,
+        MLX5_L3_PROT_TYPE_IPV6          = 1,
+};
+
+enum {
+        MLX5_L4_PROT_TYPE_TCP           = 0,
+        MLX5_L4_PROT_TYPE_UDP           = 1,
+};
+
+enum {
+        MLX5_HASH_FIELD_SEL_SRC_IP      = 1 << 0,
+        MLX5_HASH_FIELD_SEL_DST_IP      = 1 << 1,
+        MLX5_HASH_FIELD_SEL_L4_SPORT    = 1 << 2,
+        MLX5_HASH_FIELD_SEL_L4_DPORT    = 1 << 3,
+        MLX5_HASH_FIELD_SEL_IPSEC_SPI   = 1 << 4,
+};
+
+enum {
+        MLX5_MATCH_OUTER_HEADERS        = 1 << 0,
+        MLX5_MATCH_MISC_PARAMETERS      = 1 << 1,
+        MLX5_MATCH_INNER_HEADERS        = 1 << 2,
+
+};
+
+enum {
+        MLX5_FLOW_TABLE_TYPE_NIC_RCV    = 0,
+        MLX5_FLOW_TABLE_TYPE_ESWITCH    = 4,
+};
+
+enum {
+        MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT       = 0,
+        MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE  = 1,
+        MLX5_FLOW_CONTEXT_DEST_TYPE_TIR         = 2,
+};
+
+enum {
+        MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
+        MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM    = 0x1,
+};
+
+/* MLX5 DEV CAPs */
+
+/* TODO: EAT.ME */
+enum mlx5_cap_mode {
+        HCA_CAP_OPMOD_GET_MAX   = 0,
+        HCA_CAP_OPMOD_GET_CUR   = 1,
+};
+
+enum mlx5_cap_type {
+        MLX5_CAP_GENERAL = 0,
+        MLX5_CAP_ETHERNET_OFFLOADS,
+        MLX5_CAP_ODP,
+        MLX5_CAP_ATOMIC,
+        MLX5_CAP_ROCE,
+        MLX5_CAP_IPOIB_OFFLOADS,
+        MLX5_CAP_EOIB_OFFLOADS,
+        MLX5_CAP_FLOW_TABLE,
+        /* NUM OF CAP Types */
+        MLX5_CAP_NUM
+};
+
+/* GET Dev Caps macros */
+#define MLX5_CAP_GEN(mdev, cap) \
+        MLX5_GET(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap)
+
+#define MLX5_CAP_GEN_MAX(mdev, cap) \
+        MLX5_GET(cmd_hca_cap, mdev->hca_caps_max[MLX5_CAP_GENERAL], cap)
+
+#define MLX5_CAP_ETH(mdev, cap) \
+        MLX5_GET(per_protocol_networking_offload_caps,\
+                 mdev->hca_caps_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap)
+
+#define MLX5_CAP_ETH_MAX(mdev, cap) \
+        MLX5_GET(per_protocol_networking_offload_caps,\
+                 mdev->hca_caps_max[MLX5_CAP_ETHERNET_OFFLOADS], cap)
+
+#define MLX5_CAP_ROCE(mdev, cap) \
+        MLX5_GET(roce_cap, mdev->hca_caps_cur[MLX5_CAP_ROCE], cap)
+
+#define MLX5_CAP_ROCE_MAX(mdev, cap) \
+        MLX5_GET(roce_cap, mdev->hca_caps_max[MLX5_CAP_ROCE], cap)
+
+#define MLX5_CAP_ATOMIC(mdev, cap) \
+        MLX5_GET(atomic_caps, mdev->hca_caps_cur[MLX5_CAP_ATOMIC], cap)
+
+#define MLX5_CAP_ATOMIC_MAX(mdev, cap) \
+        MLX5_GET(atomic_caps, mdev->hca_caps_max[MLX5_CAP_ATOMIC], cap)
+
+#define MLX5_CAP_FLOWTABLE(mdev, cap) \
+        MLX5_GET(flow_table_nic_cap, mdev->hca_caps_cur[MLX5_CAP_FLOW_TABLE], cap)
+
+#define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \
+        MLX5_GET(flow_table_nic_cap, mdev->hca_caps_max[MLX5_CAP_FLOW_TABLE], cap)
+
+#define MLX5_CAP_ODP(mdev, cap)\
+        MLX5_GET(odp_cap, mdev->hca_caps_cur[MLX5_CAP_ODP], cap)
+
+enum {
+        MLX5_CMD_STAT_OK                        = 0x0,
+        MLX5_CMD_STAT_INT_ERR                   = 0x1,
+        MLX5_CMD_STAT_BAD_OP_ERR                = 0x2,
+        MLX5_CMD_STAT_BAD_PARAM_ERR             = 0x3,
+        MLX5_CMD_STAT_BAD_SYS_STATE_ERR         = 0x4,
+        MLX5_CMD_STAT_BAD_RES_ERR               = 0x5,
+        MLX5_CMD_STAT_RES_BUSY                  = 0x6,
+        MLX5_CMD_STAT_LIM_ERR                   = 0x8,
+        MLX5_CMD_STAT_BAD_RES_STATE_ERR         = 0x9,
+        MLX5_CMD_STAT_IX_ERR                    = 0xa,
+        MLX5_CMD_STAT_NO_RES_ERR                = 0xf,
+        MLX5_CMD_STAT_BAD_INP_LEN_ERR           = 0x50,
+        MLX5_CMD_STAT_BAD_OUTP_LEN_ERR          = 0x51,
+        MLX5_CMD_STAT_BAD_QP_STATE_ERR          = 0x10,
+        MLX5_CMD_STAT_BAD_PKT_ERR               = 0x30,
+        MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR    = 0x40,
+};
+
+static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz)
+{
+        if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE)
+                return 0;
+        return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz;
+}
+
 #endif /* MLX5_DEVICE_H */
diff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h
index 9ec7c93d6fa3..5722d88c2429 100644
--- a/include/linux/mlx5/driver.h
+++ b/include/linux/mlx5/driver.h
@@ -44,7 +44,6 @@
 
 #include <linux/mlx5/device.h>
 #include <linux/mlx5/doorbell.h>
-#include <linux/mlx5/mlx5_ifc.h>
 
 enum {
         MLX5_BOARD_ID_LEN = 64,
@@ -85,7 +84,7 @@ enum {
 };
 
 enum {
-        MLX5_MAX_EQ_NAME        = 32
+        MLX5_MAX_IRQ_NAME       = 32
 };
 
 enum {
@@ -108,6 +107,7 @@ enum {
         MLX5_REG_PUDE            = 0x5009,
         MLX5_REG_PMPE            = 0x5010,
         MLX5_REG_PELC            = 0x500e,
+        MLX5_REG_PVLC            = 0x500f,
         MLX5_REG_PMLP            = 0, /* TBD */
         MLX5_REG_NODE_DESC       = 0x6001,
         MLX5_REG_HOST_ENDIANNESS = 0x7004,
@@ -150,6 +150,11 @@ enum mlx5_dev_event {
         MLX5_DEV_EVENT_CLIENT_REREG,
 };
 
+enum mlx5_port_status {
+        MLX5_PORT_UP        = 1 << 1,
+        MLX5_PORT_DOWN      = 1 << 2,
+};
+
 struct mlx5_uuar_info {
         struct mlx5_uar        *uars;
         int                     num_uars;
@@ -269,56 +274,7 @@ struct mlx5_cmd {
 struct mlx5_port_caps {
         int     gid_table_len;
         int     pkey_table_len;
-};
-
-struct mlx5_general_caps {
-        u8      log_max_eq;
-        u8      log_max_cq;
-        u8      log_max_qp;
-        u8      log_max_mkey;
-        u8      log_max_pd;
-        u8      log_max_srq;
-        u8      log_max_strq;
-        u8      log_max_mrw_sz;
-        u8      log_max_bsf_list_size;
-        u8      log_max_klm_list_size;
-        u32     max_cqes;
-        int     max_wqes;
-        u32     max_eqes;
-        u32     max_indirection;
-        int     max_sq_desc_sz;
-        int     max_rq_desc_sz;
-        int     max_dc_sq_desc_sz;
-        u64     flags;
-        u16     stat_rate_support;
-        int     log_max_msg;
-        int     num_ports;
-        u8      log_max_ra_res_qp;
-        u8      log_max_ra_req_qp;
-        int     max_srq_wqes;
-        int     bf_reg_size;
-        int     bf_regs_per_page;
-        struct mlx5_port_caps   port[MLX5_MAX_PORTS];
-        u8                      ext_port_cap[MLX5_MAX_PORTS];
-        int     max_vf;
-        u32     reserved_lkey;
-        u8      local_ca_ack_delay;
-        u8      log_max_mcg;
-        u32     max_qp_mcg;
-        int     min_page_sz;
-        int     pd_cap;
-        u32     max_qp_counters;
-        u32     pkey_table_size;
-        u8      log_max_ra_req_dc;
-        u8      log_max_ra_res_dc;
-        u32     uar_sz;
-        u8      min_log_pg_sz;
-        u8      log_max_xrcd;
-        u16     log_uar_page_sz;
-};
-
-struct mlx5_caps {
-        struct mlx5_general_caps gen;
+        u8      ext_port_cap;
 };
 
 struct mlx5_cmd_mailbox {
@@ -334,8 +290,6 @@ struct mlx5_buf_list {
 
 struct mlx5_buf {
         struct mlx5_buf_list    direct;
-        struct mlx5_buf_list   *page_list;
-        int                     nbufs;
         int                     npages;
         int                     size;
         u8                      page_shift;
@@ -351,7 +305,6 @@ struct mlx5_eq {
         u8                      eqn;
         int                     nent;
         u64                     mask;
-        char                    name[MLX5_MAX_EQ_NAME];
         struct list_head        list;
         int                     index;
         struct mlx5_rsc_debug   *dbg;
@@ -387,6 +340,8 @@ struct mlx5_core_mr {
 
 enum mlx5_res_type {
         MLX5_RES_QP,
+        MLX5_RES_SRQ,
+        MLX5_RES_XSRQ,
 };
 
 struct mlx5_core_rsc_common {
@@ -396,6 +351,7 @@ struct mlx5_core_rsc_common {
 };
 
 struct mlx5_core_srq {
+        struct mlx5_core_rsc_common     common; /* must be first */
         u32             srqn;
         int             max;
         int             max_gs;
@@ -414,7 +370,6 @@ struct mlx5_eq_table {
         struct mlx5_eq          pages_eq;
         struct mlx5_eq          async_eq;
         struct mlx5_eq          cmd_eq;
-        struct msix_entry       *msix_arr;
         int                     num_comp_vectors;
         /* protect EQs list
          */
@@ -467,9 +422,16 @@ struct mlx5_mr_table {
         struct radix_tree_root  tree;
 };
 
+struct mlx5_irq_info {
+        cpumask_var_t mask;
+        char name[MLX5_MAX_IRQ_NAME];
+};
+
 struct mlx5_priv {
         char                    name[MLX5_MAX_NAME_LEN];
         struct mlx5_eq_table    eq_table;
+        struct msix_entry       *msix_arr;
+        struct mlx5_irq_info    *irq_info;
         struct mlx5_uuar_info   uuari;
         MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock);
 
@@ -520,7 +482,9 @@ struct mlx5_core_dev {
         u8                      rev_id;
         char                    board_id[MLX5_BOARD_ID_LEN];
         struct mlx5_cmd         cmd;
-        struct mlx5_caps        caps;
+        struct mlx5_port_caps   port_caps[MLX5_MAX_PORTS];
+        u32 hca_caps_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
+        u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
         phys_addr_t             iseg_base;
         struct mlx5_init_seg __iomem *iseg;
         void                    (*event) (struct mlx5_core_dev *dev,
@@ -529,6 +493,7 @@ struct mlx5_core_dev {
         struct mlx5_priv        priv;
         struct mlx5_profile     *profile;
         atomic_t                num_qps;
+        u32                     issi;
 };
 
 struct mlx5_db {
@@ -549,6 +514,11 @@ enum {
         MLX5_COMP_EQ_SIZE = 1024,
 };
 
+enum {
+        MLX5_PTYS_IB = 1 << 0,
+        MLX5_PTYS_EN = 1 << 2,
+};
+
 struct mlx5_db_pgdir {
         struct list_head        list;
         DECLARE_BITMAP(bitmap, MLX5_DB_PER_PAGE);
@@ -584,13 +554,44 @@ struct mlx5_pas {
         u8      log_sz;
 };
 
+enum port_state_policy {
+        MLX5_AAA_000
+};
+
+enum phy_port_state {
+        MLX5_AAA_111
+};
+
+struct mlx5_hca_vport_context {
+        u32                     field_select;
+        bool                    sm_virt_aware;
+        bool                    has_smi;
+        bool                    has_raw;
+        enum port_state_policy  policy;
+        enum phy_port_state     phys_state;
+        enum ib_port_state      vport_state;
+        u8                      port_physical_state;
+        u64                     sys_image_guid;
+        u64                     port_guid;
+        u64                     node_guid;
+        u32                     cap_mask1;
+        u32                     cap_mask1_perm;
+        u32                     cap_mask2;
+        u32                     cap_mask2_perm;
+        u16                     lid;
+        u8                      init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
+        u8                      lmc;
+        u8                      subnet_timeout;
+        u16                     sm_lid;
+        u8                      sm_sl;
+        u16                     qkey_violation_counter;
+        u16                     pkey_violation_counter;
+        bool                    grh_required;
+};
+
 static inline void *mlx5_buf_offset(struct mlx5_buf *buf, int offset)
 {
-        if (likely(BITS_PER_LONG == 64 || buf->nbufs == 1))
                 return buf->direct.buf + offset;
-        else
-                return buf->page_list[offset >> PAGE_SHIFT].buf +
-                        (offset & (PAGE_SIZE - 1));
 }
 
 extern struct workqueue_struct *mlx5_core_wq;
@@ -654,8 +655,8 @@ void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
 int mlx5_cmd_status_to_err(struct mlx5_outbox_hdr *hdr);
 int mlx5_cmd_status_to_err_v2(void *ptr);
-int mlx5_core_get_caps(struct mlx5_core_dev *dev, struct mlx5_caps *caps,
-                       u16 opmod);
+int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type,
+                       enum mlx5_cap_mode cap_mode);
 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
                   int out_size);
 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
@@ -665,19 +666,21 @@ int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
 int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
 int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
+int mlx5_alloc_map_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar);
+void mlx5_unmap_free_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar);
 void mlx5_health_cleanup(void);
 void  __init mlx5_health_init(void);
 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
 void mlx5_stop_health_poll(struct mlx5_core_dev *dev);
-int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, int max_direct,
-                   struct mlx5_buf *buf);
+int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, struct mlx5_buf *buf);
 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf);
 struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev,
                                                       gfp_t flags, int npages);
 void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev,
                                  struct mlx5_cmd_mailbox *head);
 int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
-                         struct mlx5_create_srq_mbox_in *in, int inlen);
+                         struct mlx5_create_srq_mbox_in *in, int inlen,
+                         int is_xrc);
 int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq);
 int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
                         struct mlx5_query_srq_mbox_out *out);
@@ -734,7 +737,32 @@ void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
                          int size_in, void *data_out, int size_out,
                          u16 reg_num, int arg, int write);
+
 int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps);
+int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys,
+                         int ptys_size, int proto_mask, u8 local_port);
+int mlx5_query_port_proto_cap(struct mlx5_core_dev *dev,
+                              u32 *proto_cap, int proto_mask);
+int mlx5_query_port_proto_admin(struct mlx5_core_dev *dev,
+                                u32 *proto_admin, int proto_mask);
+int mlx5_query_port_link_width_oper(struct mlx5_core_dev *dev,
+                                    u8 *link_width_oper, u8 local_port);
+int mlx5_query_port_proto_oper(struct mlx5_core_dev *dev,
+                               u8 *proto_oper, int proto_mask,
+                               u8 local_port);
+int mlx5_set_port_proto(struct mlx5_core_dev *dev, u32 proto_admin,
+                        int proto_mask);
+int mlx5_set_port_status(struct mlx5_core_dev *dev,
+                         enum mlx5_port_status status);
+int mlx5_query_port_status(struct mlx5_core_dev *dev, u8 *status);
+
+int mlx5_set_port_mtu(struct mlx5_core_dev *dev, int mtu, u8 port);
+void mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, int *max_mtu, u8 port);
+void mlx5_query_port_oper_mtu(struct mlx5_core_dev *dev, int *oper_mtu,
+                              u8 port);
+
+int mlx5_query_port_vl_hw_cap(struct mlx5_core_dev *dev,
+                              u8 *vl_hw_cap, u8 local_port);
 
 int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
 void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
@@ -799,6 +827,7 @@ struct mlx5_interface {
 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol);
 int mlx5_register_interface(struct mlx5_interface *intf);
 void mlx5_unregister_interface(struct mlx5_interface *intf);
+int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
 
 struct mlx5_profile {
         u64     mask;
@@ -809,4 +838,14 @@ struct mlx5_profile {
         } mr_cache[MAX_MR_CACHE_ENTRIES];
 };
 
+static inline int mlx5_get_gid_table_len(u16 param)
+{
+        if (param > 4) {
+                pr_warn("gid table length is zero\n");
+                return 0;
+        }
+
+        return 8 * (1 << param);
+}
+
 #endif /* MLX5_DRIVER_H */
diff --git a/include/linux/mlx5/flow_table.h b/include/linux/mlx5/flow_table.h
new file mode 100644
index 000000000000..5f922c6d4fc2
--- /dev/null
+++ b/include/linux/mlx5/flow_table.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the
+ * OpenIB.org BSD license below:
+ *
+ *     Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *      - Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *
+ *      - Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#ifndef MLX5_FLOW_TABLE_H
+#define MLX5_FLOW_TABLE_H
+
+#include <linux/mlx5/driver.h>
+
+struct mlx5_flow_table_group {
+        u8      log_sz;
+        u8      match_criteria_enable;
+        u32     match_criteria[MLX5_ST_SZ_DW(fte_match_param)];
+};
+
+void *mlx5_create_flow_table(struct mlx5_core_dev *dev, u8 level, u8 table_type,
+                             u16 num_groups,
+                             struct mlx5_flow_table_group *group);
+void mlx5_destroy_flow_table(void *flow_table);
+int mlx5_add_flow_table_entry(void *flow_table, u8 match_criteria_enable,
+                              void *match_criteria, void *flow_context,
+                              u32 *flow_index);
+void mlx5_del_flow_table_entry(void *flow_table, u32 flow_index);
+u32 mlx5_get_flow_table_id(void *flow_table);
+
+#endif /* MLX5_FLOW_TABLE_H */
diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h
index cb3ad17edd1f..6d2f6fee041c 100644
--- a/include/linux/mlx5/mlx5_ifc.h
+++ b/include/linux/mlx5/mlx5_ifc.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
+ * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
  *
  * This software is available to you under a choice of one of two
  * licenses.  You may choose to be licensed under the terms of the GNU
@@ -28,12 +28,45 @@
  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  * SOFTWARE.
- */
-
+*/
 #ifndef MLX5_IFC_H
 #define MLX5_IFC_H
 
 enum {
+        MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
+        MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
+        MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
+        MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
+        MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
+        MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
+        MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
+        MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
+        MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
+        MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
+        MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
+        MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
+        MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
+        MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
+        MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
+        MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
+        MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
+        MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
+        MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
+        MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
+        MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
+        MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
+        MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
+        MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb
+};
+
+enum {
+        MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
+        MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
+        MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
+        MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
+};
+
+enum {
         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
         MLX5_CMD_OP_INIT_HCA                      = 0x102,
@@ -43,6 +76,8 @@ enum {
         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
+        MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
+        MLX5_CMD_OP_SET_ISSI                      = 0x10b,
         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
@@ -66,6 +101,7 @@ enum {
         MLX5_CMD_OP_2ERR_QP                       = 0x507,
         MLX5_CMD_OP_2RST_QP                       = 0x50a,
         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
+        MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
@@ -73,7 +109,10 @@ enum {
         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
         MLX5_CMD_OP_ARM_RQ                        = 0x703,
-        MLX5_CMD_OP_RESIZE_SRQ                    = 0x704,
+        MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
+        MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
+        MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
+        MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
@@ -85,8 +124,12 @@ enum {
         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
-        MLX5_CMD_OP_QUERY_RCOE_ADDRESS            = 0x760,
+        MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
+        MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
+        MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
+        MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
+        MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
@@ -98,7 +141,7 @@ enum {
         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
-        MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
+        MLX5_CMD_OP_DETTACH_FROM_MCG              = 0x807,
         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
@@ -106,23 +149,22 @@ enum {
         MLX5_CMD_OP_NOP                           = 0x80d,
         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
-        MLX5_CMD_OP_SET_BURST_SIZE                = 0x812,
-        MLX5_CMD_OP_QUERY_BURST_SZIE              = 0x813,
-        MLX5_CMD_OP_ACTIVATE_TRACER               = 0x814,
-        MLX5_CMD_OP_DEACTIVATE_TRACER             = 0x815,
-        MLX5_CMD_OP_CREATE_SNIFFER_RULE           = 0x820,
-        MLX5_CMD_OP_DESTROY_SNIFFER_RULE          = 0x821,
-        MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x822,
-        MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x823,
-        MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x824,
+        MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
+        MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
+        MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
+        MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
+        MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
+        MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
+        MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
+        MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
+        MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
+        MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
+        MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
+        MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
-        MLX5_CMD_OP_CREATE_TIS                    = 0x912,
-        MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
-        MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
-        MLX5_CMD_OP_QUERY_TIS                     = 0x915,
         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
@@ -135,9 +177,430 @@ enum {
         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
-        MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x910,
-        MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x911,
-        MLX5_CMD_OP_MAX                           = 0x911
+        MLX5_CMD_OP_CREATE_TIS                    = 0x912,
+        MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
+        MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
+        MLX5_CMD_OP_QUERY_TIS                     = 0x915,
+        MLX5_CMD_OP_CREATE_RQT                    = 0x916,
+        MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
+        MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
+        MLX5_CMD_OP_QUERY_RQT                     = 0x919,
+        MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
+        MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
+        MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
+        MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
+        MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
+        MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
+        MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
+        MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
+        MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938
+};
+
+struct mlx5_ifc_flow_table_fields_supported_bits {
+        u8         outer_dmac[0x1];
+        u8         outer_smac[0x1];
+        u8         outer_ether_type[0x1];
+        u8         reserved_0[0x1];
+        u8         outer_first_prio[0x1];
+        u8         outer_first_cfi[0x1];
+        u8         outer_first_vid[0x1];
+        u8         reserved_1[0x1];
+        u8         outer_second_prio[0x1];
+        u8         outer_second_cfi[0x1];
+        u8         outer_second_vid[0x1];
+        u8         reserved_2[0x1];
+        u8         outer_sip[0x1];
+        u8         outer_dip[0x1];
+        u8         outer_frag[0x1];
+        u8         outer_ip_protocol[0x1];
+        u8         outer_ip_ecn[0x1];
+        u8         outer_ip_dscp[0x1];
+        u8         outer_udp_sport[0x1];
+        u8         outer_udp_dport[0x1];
+        u8         outer_tcp_sport[0x1];
+        u8         outer_tcp_dport[0x1];
+        u8         outer_tcp_flags[0x1];
+        u8         outer_gre_protocol[0x1];
+        u8         outer_gre_key[0x1];
+        u8         outer_vxlan_vni[0x1];
+        u8         reserved_3[0x5];
+        u8         source_eswitch_port[0x1];
+
+        u8         inner_dmac[0x1];
+        u8         inner_smac[0x1];
+        u8         inner_ether_type[0x1];
+        u8         reserved_4[0x1];
+        u8         inner_first_prio[0x1];
+        u8         inner_first_cfi[0x1];
+        u8         inner_first_vid[0x1];
+        u8         reserved_5[0x1];
+        u8         inner_second_prio[0x1];
+        u8         inner_second_cfi[0x1];
+        u8         inner_second_vid[0x1];
+        u8         reserved_6[0x1];
+        u8         inner_sip[0x1];
+        u8         inner_dip[0x1];
+        u8         inner_frag[0x1];
+        u8         inner_ip_protocol[0x1];
+        u8         inner_ip_ecn[0x1];
+        u8         inner_ip_dscp[0x1];
+        u8         inner_udp_sport[0x1];
+        u8         inner_udp_dport[0x1];
+        u8         inner_tcp_sport[0x1];
+        u8         inner_tcp_dport[0x1];
+        u8         inner_tcp_flags[0x1];
+        u8         reserved_7[0x9];
+
+        u8         reserved_8[0x40];
+};
+
+struct mlx5_ifc_flow_table_prop_layout_bits {
+        u8         ft_support[0x1];
+        u8         reserved_0[0x1f];
+
+        u8         reserved_1[0x2];
+        u8         log_max_ft_size[0x6];
+        u8         reserved_2[0x10];
+        u8         max_ft_level[0x8];
+
+        u8         reserved_3[0x20];
+
+        u8         reserved_4[0x18];
+        u8         log_max_ft_num[0x8];
+
+        u8         reserved_5[0x18];
+        u8         log_max_destination[0x8];
+
+        u8         reserved_6[0x18];
+        u8         log_max_flow[0x8];
+
+        u8         reserved_7[0x40];
+
+        struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
+
+        struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
+};
+
+struct mlx5_ifc_odp_per_transport_service_cap_bits {
+        u8         send[0x1];
+        u8         receive[0x1];
+        u8         write[0x1];
+        u8         read[0x1];
+        u8         reserved_0[0x1];
+        u8         srq_receive[0x1];
+        u8         reserved_1[0x1a];
+};
+
+struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
+        u8         smac_47_16[0x20];
+
+        u8         smac_15_0[0x10];
+        u8         ethertype[0x10];
+
+        u8         dmac_47_16[0x20];
+
+        u8         dmac_15_0[0x10];
+        u8         first_prio[0x3];
+        u8         first_cfi[0x1];
+        u8         first_vid[0xc];
+
+        u8         ip_protocol[0x8];
+        u8         ip_dscp[0x6];
+        u8         ip_ecn[0x2];
+        u8         vlan_tag[0x1];
+        u8         reserved_0[0x1];
+        u8         frag[0x1];
+        u8         reserved_1[0x4];
+        u8         tcp_flags[0x9];
+
+        u8         tcp_sport[0x10];
+        u8         tcp_dport[0x10];
+
+        u8         reserved_2[0x20];
+
+        u8         udp_sport[0x10];
+        u8         udp_dport[0x10];
+
+        u8         src_ip[4][0x20];
+
+        u8         dst_ip[4][0x20];
+};
+
+struct mlx5_ifc_fte_match_set_misc_bits {
+        u8         reserved_0[0x20];
+
+        u8         reserved_1[0x10];
+        u8         source_port[0x10];
+
+        u8         outer_second_prio[0x3];
+        u8         outer_second_cfi[0x1];
+        u8         outer_second_vid[0xc];
+        u8         inner_second_prio[0x3];
+        u8         inner_second_cfi[0x1];
+        u8         inner_second_vid[0xc];
+
+        u8         outer_second_vlan_tag[0x1];
+        u8         inner_second_vlan_tag[0x1];
+        u8         reserved_2[0xe];
+        u8         gre_protocol[0x10];
+
+        u8         gre_key_h[0x18];
+        u8         gre_key_l[0x8];
+
+        u8         vxlan_vni[0x18];
+        u8         reserved_3[0x8];
+
+        u8         reserved_4[0x20];
+
+        u8         reserved_5[0xc];
+        u8         outer_ipv6_flow_label[0x14];
+
+        u8         reserved_6[0xc];
+        u8         inner_ipv6_flow_label[0x14];
+
+        u8         reserved_7[0xe0];
+};
+
+struct mlx5_ifc_cmd_pas_bits {
+        u8         pa_h[0x20];
+
+        u8         pa_l[0x14];
+        u8         reserved_0[0xc];
+};
+
+struct mlx5_ifc_uint64_bits {
+        u8         hi[0x20];
+
+        u8         lo[0x20];
+};
+
+enum {
+        MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
+        MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
+        MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
+        MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
+        MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
+        MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
+        MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
+        MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
+        MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
+        MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
+};
+
+struct mlx5_ifc_ads_bits {
+        u8         fl[0x1];
+        u8         free_ar[0x1];
+        u8         reserved_0[0xe];
+        u8         pkey_index[0x10];
+
+        u8         reserved_1[0x8];
+        u8         grh[0x1];
+        u8         mlid[0x7];
+        u8         rlid[0x10];
+
+        u8         ack_timeout[0x5];
+        u8         reserved_2[0x3];
+        u8         src_addr_index[0x8];
+        u8         reserved_3[0x4];
+        u8         stat_rate[0x4];
+        u8         hop_limit[0x8];
+
+        u8         reserved_4[0x4];
+        u8         tclass[0x8];
+        u8         flow_label[0x14];
+
+        u8         rgid_rip[16][0x8];
+
+        u8         reserved_5[0x4];
+        u8         f_dscp[0x1];
+        u8         f_ecn[0x1];
+        u8         reserved_6[0x1];
+        u8         f_eth_prio[0x1];
+        u8         ecn[0x2];
+        u8         dscp[0x6];
+        u8         udp_sport[0x10];
+
+        u8         dei_cfi[0x1];
+        u8         eth_prio[0x3];
+        u8         sl[0x4];
+        u8         port[0x8];
+        u8         rmac_47_32[0x10];
+
+        u8         rmac_31_0[0x20];
+};
+
+struct mlx5_ifc_flow_table_nic_cap_bits {
+        u8         reserved_0[0x200];
+
+        struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
+
+        u8         reserved_1[0x200];
+
+        struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
+
+        struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
+
+        u8         reserved_2[0x200];
+
+        struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
+
+        u8         reserved_3[0x7200];
+};
+
+struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
+        u8         csum_cap[0x1];
+        u8         vlan_cap[0x1];
+        u8         lro_cap[0x1];
+        u8         lro_psh_flag[0x1];
+        u8         lro_time_stamp[0x1];
+        u8         reserved_0[0x6];
+        u8         max_lso_cap[0x5];
+        u8         reserved_1[0x4];
+        u8         rss_ind_tbl_cap[0x4];
+        u8         reserved_2[0x3];
+        u8         tunnel_lso_const_out_ip_id[0x1];
+        u8         reserved_3[0x2];
+        u8         tunnel_statless_gre[0x1];
+        u8         tunnel_stateless_vxlan[0x1];
+
+        u8         reserved_4[0x20];
+
+        u8         reserved_5[0x10];
+        u8         lro_min_mss_size[0x10];
+
+        u8         reserved_6[0x120];
+
+        u8         lro_timer_supported_periods[4][0x20];
+
+        u8         reserved_7[0x600];
+};
+
+struct mlx5_ifc_roce_cap_bits {
+        u8         roce_apm[0x1];
+        u8         reserved_0[0x1f];
+
+        u8         reserved_1[0x60];
+
+        u8         reserved_2[0xc];
+        u8         l3_type[0x4];
+        u8         reserved_3[0x8];
+        u8         roce_version[0x8];
+
+        u8         reserved_4[0x10];
+        u8         r_roce_dest_udp_port[0x10];
+
+        u8         r_roce_max_src_udp_port[0x10];
+        u8         r_roce_min_src_udp_port[0x10];
+
+        u8         reserved_5[0x10];
+        u8         roce_address_table_size[0x10];
+
+        u8         reserved_6[0x700];
+};
+
+enum {
+        MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
+        MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
+        MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
+        MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
+        MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
+        MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
+        MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
+        MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
+        MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
+};
+
+enum {
+        MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
+        MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
+        MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
+        MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
+        MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
+        MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
+        MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
+        MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
+        MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
+};
+
+struct mlx5_ifc_atomic_caps_bits {
+        u8         reserved_0[0x40];
+
+        u8         atomic_req_endianness[0x1];
+        u8         reserved_1[0x1f];
+
+        u8         reserved_2[0x20];
+
+        u8         reserved_3[0x10];
+        u8         atomic_operations[0x10];
+
+        u8         reserved_4[0x10];
+        u8         atomic_size_qp[0x10];
+
+        u8         reserved_5[0x10];
+        u8         atomic_size_dc[0x10];
+
+        u8         reserved_6[0x720];
+};
+
+struct mlx5_ifc_odp_cap_bits {
+        u8         reserved_0[0x40];
+
+        u8         sig[0x1];
+        u8         reserved_1[0x1f];
+
+        u8         reserved_2[0x20];
+
+        struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
+
+        struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
+
+        struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
+
+        u8         reserved_3[0x720];
+};
+
+enum {
+        MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
+        MLX5_WQ_TYPE_CYCLIC       = 0x1,
+        MLX5_WQ_TYPE_STRQ         = 0x2,
+};
+
+enum {
+        MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
+        MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
+};
+
+enum {
+        MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
+        MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
+        MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
+        MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
+        MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
+};
+
+enum {
+        MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
+        MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
+        MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
+        MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
+        MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
+        MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
+};
+
+enum {
+        MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
+        MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
+};
+
+enum {
+        MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
+        MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
+        MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
+};
+
+enum {
+        MLX5_CAP_PORT_TYPE_IB  = 0x0,
+        MLX5_CAP_PORT_TYPE_ETH = 0x1,
 };
 
 struct mlx5_ifc_cmd_hca_cap_bits {
@@ -148,9 +611,8 @@ struct mlx5_ifc_cmd_hca_cap_bits {
         u8         reserved_1[0xb];
         u8         log_max_qp[0x5];
 
-        u8         log_max_strq_sz[0x8];
-        u8         reserved_2[0x3];
-        u8         log_max_srqs[0x5];
+        u8         reserved_2[0xb];
+        u8         log_max_srq[0x5];
         u8         reserved_3[0x10];
 
         u8         reserved_4[0x8];
@@ -185,123 +647,2112 @@ struct mlx5_ifc_cmd_hca_cap_bits {
         u8         pad_cap[0x1];
         u8         cc_query_allowed[0x1];
         u8         cc_modify_allowed[0x1];
-        u8         reserved_15[0x1d];
+        u8         reserved_15[0xd];
+        u8         gid_table_size[0x10];
 
-        u8         reserved_16[0x6];
+        u8         out_of_seq_cnt[0x1];
+        u8         vport_counters[0x1];
+        u8         reserved_16[0x4];
         u8         max_qp_cnt[0xa];
         u8         pkey_table_size[0x10];
 
-        u8         eswitch_owner[0x1];
-        u8         reserved_17[0xa];
+        u8         vport_group_manager[0x1];
+        u8         vhca_group_manager[0x1];
+        u8         ib_virt[0x1];
+        u8         eth_virt[0x1];
+        u8         reserved_17[0x1];
+        u8         ets[0x1];
+        u8         nic_flow_table[0x1];
+        u8         reserved_18[0x4];
         u8         local_ca_ack_delay[0x5];
-        u8         reserved_18[0x8];
+        u8         reserved_19[0x6];
+        u8         port_type[0x2];
         u8         num_ports[0x8];
 
-        u8         reserved_19[0x3];
+        u8         reserved_20[0x3];
         u8         log_max_msg[0x5];
-        u8         reserved_20[0x18];
+        u8         reserved_21[0x18];
 
         u8         stat_rate_support[0x10];
-        u8         reserved_21[0x10];
+        u8         reserved_22[0xc];
+        u8         cqe_version[0x4];
 
-        u8         reserved_22[0x10];
+        u8         compact_address_vector[0x1];
+        u8         reserved_23[0xe];
+        u8         drain_sigerr[0x1];
         u8         cmdif_checksum[0x2];
         u8         sigerr_cqe[0x1];
-        u8         reserved_23[0x1];
+        u8         reserved_24[0x1];
         u8         wq_signature[0x1];
         u8         sctr_data_cqe[0x1];
-        u8         reserved_24[0x1];
+        u8         reserved_25[0x1];
         u8         sho[0x1];
         u8         tph[0x1];
         u8         rf[0x1];
-        u8         dc[0x1];
-        u8         reserved_25[0x2];
+        u8         dct[0x1];
+        u8         reserved_26[0x1];
+        u8         eth_net_offloads[0x1];
         u8         roce[0x1];
         u8         atomic[0x1];
-        u8         rsz_srq[0x1];
+        u8         reserved_27[0x1];
 
         u8         cq_oi[0x1];
         u8         cq_resize[0x1];
         u8         cq_moderation[0x1];
-        u8         sniffer_rule_flow[0x1];
-        u8         sniffer_rule_vport[0x1];
-        u8         sniffer_rule_phy[0x1];
-        u8         reserved_26[0x1];
+        u8         reserved_28[0x3];
+        u8         cq_eq_remap[0x1];
         u8         pg[0x1];
         u8         block_lb_mc[0x1];
-        u8         reserved_27[0x3];
+        u8         reserved_29[0x1];
+        u8         scqe_break_moderation[0x1];
+        u8         reserved_30[0x1];
         u8         cd[0x1];
-        u8         reserved_28[0x1];
+        u8         reserved_31[0x1];
         u8         apm[0x1];
-        u8         reserved_29[0x7];
+        u8         reserved_32[0x7];
         u8         qkv[0x1];
         u8         pkv[0x1];
-        u8         reserved_30[0x4];
+        u8         reserved_33[0x4];
         u8         xrc[0x1];
         u8         ud[0x1];
         u8         uc[0x1];
         u8         rc[0x1];
 
-        u8         reserved_31[0xa];
+        u8         reserved_34[0xa];
         u8         uar_sz[0x6];
-        u8         reserved_32[0x8];
+        u8         reserved_35[0x8];
         u8         log_pg_sz[0x8];
 
         u8         bf[0x1];
-        u8         reserved_33[0xa];
+        u8         reserved_36[0x1];
+        u8         pad_tx_eth_packet[0x1];
+        u8         reserved_37[0x8];
         u8         log_bf_reg_size[0x5];
-        u8         reserved_34[0x10];
+        u8         reserved_38[0x10];
 
-        u8         reserved_35[0x10];
+        u8         reserved_39[0x10];
         u8         max_wqe_sz_sq[0x10];
 
-        u8         reserved_36[0x10];
+        u8         reserved_40[0x10];
         u8         max_wqe_sz_rq[0x10];
 
-        u8         reserved_37[0x10];
+        u8         reserved_41[0x10];
         u8         max_wqe_sz_sq_dc[0x10];
 
-        u8         reserved_38[0x7];
+        u8         reserved_42[0x7];
         u8         max_qp_mcg[0x19];
 
-        u8         reserved_39[0x18];
+        u8         reserved_43[0x18];
         u8         log_max_mcg[0x8];
 
-        u8         reserved_40[0xb];
+        u8         reserved_44[0x3];
+        u8         log_max_transport_domain[0x5];
+        u8         reserved_45[0x3];
         u8         log_max_pd[0x5];
-        u8         reserved_41[0xb];
+        u8         reserved_46[0xb];
         u8         log_max_xrcd[0x5];
 
-        u8         reserved_42[0x20];
+        u8         reserved_47[0x20];
 
-        u8         reserved_43[0x3];
+        u8         reserved_48[0x3];
         u8         log_max_rq[0x5];
-        u8         reserved_44[0x3];
+        u8         reserved_49[0x3];
         u8         log_max_sq[0x5];
-        u8         reserved_45[0x3];
+        u8         reserved_50[0x3];
         u8         log_max_tir[0x5];
-        u8         reserved_46[0x3];
+        u8         reserved_51[0x3];
         u8         log_max_tis[0x5];
 
-        u8         reserved_47[0x13];
-        u8         log_max_rq_per_tir[0x5];
-        u8         reserved_48[0x3];
+        u8         basic_cyclic_rcv_wqe[0x1];
+        u8         reserved_52[0x2];
+        u8         log_max_rmp[0x5];
+        u8         reserved_53[0x3];
+        u8         log_max_rqt[0x5];
+        u8         reserved_54[0x3];
+        u8         log_max_rqt_size[0x5];
+        u8         reserved_55[0x3];
         u8         log_max_tis_per_sq[0x5];
 
-        u8         reserved_49[0xe0];
+        u8         reserved_56[0x3];
+        u8         log_max_stride_sz_rq[0x5];
+        u8         reserved_57[0x3];
+        u8         log_min_stride_sz_rq[0x5];
+        u8         reserved_58[0x3];
+        u8         log_max_stride_sz_sq[0x5];
+        u8         reserved_59[0x3];
+        u8         log_min_stride_sz_sq[0x5];
 
-        u8         reserved_50[0x10];
+        u8         reserved_60[0x1b];
+        u8         log_max_wq_sz[0x5];
+
+        u8         reserved_61[0xa0];
+
+        u8         reserved_62[0x3];
+        u8         log_max_l2_table[0x5];
+        u8         reserved_63[0x8];
         u8         log_uar_page_sz[0x10];
 
-        u8         reserved_51[0x100];
+        u8         reserved_64[0x100];
 
-        u8         reserved_52[0x1f];
+        u8         reserved_65[0x1f];
         u8         cqe_zip[0x1];
 
         u8         cqe_zip_timeout[0x10];
         u8         cqe_zip_max_num[0x10];
 
-        u8         reserved_53[0x220];
+        u8         reserved_66[0x220];
+};
+
+enum {
+        MLX5_DEST_FORMAT_STRUCT_DESTINATION_TYPE_FLOW_TABLE_  = 0x1,
+        MLX5_DEST_FORMAT_STRUCT_DESTINATION_TYPE_TIR          = 0x2,
+};
+
+struct mlx5_ifc_dest_format_struct_bits {
+        u8         destination_type[0x8];
+        u8         destination_id[0x18];
+
+        u8         reserved_0[0x20];
+};
+
+struct mlx5_ifc_fte_match_param_bits {
+        struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
+
+        struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
+
+        struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
+
+        u8         reserved_0[0xa00];
+};
+
+enum {
+        MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
+        MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
+        MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
+        MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
+        MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
+};
+
+struct mlx5_ifc_rx_hash_field_select_bits {
+        u8         l3_prot_type[0x1];
+        u8         l4_prot_type[0x1];
+        u8         selected_fields[0x1e];
+};
+
+enum {
+        MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
+        MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
+};
+
+enum {
+        MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
+        MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
+};
+
+struct mlx5_ifc_wq_bits {
+        u8         wq_type[0x4];
+        u8         wq_signature[0x1];
+        u8         end_padding_mode[0x2];
+        u8         cd_slave[0x1];
+        u8         reserved_0[0x18];
+
+        u8         hds_skip_first_sge[0x1];
+        u8         log2_hds_buf_size[0x3];
+        u8         reserved_1[0x7];
+        u8         page_offset[0x5];
+        u8         lwm[0x10];
+
+        u8         reserved_2[0x8];
+        u8         pd[0x18];
+
+        u8         reserved_3[0x8];
+        u8         uar_page[0x18];
+
+        u8         dbr_addr[0x40];
+
+        u8         hw_counter[0x20];
+
+        u8         sw_counter[0x20];
+
+        u8         reserved_4[0xc];
+        u8         log_wq_stride[0x4];
+        u8         reserved_5[0x3];
+        u8         log_wq_pg_sz[0x5];
+        u8         reserved_6[0x3];
+        u8         log_wq_sz[0x5];
+
+        u8         reserved_7[0x4e0];
+
+        struct mlx5_ifc_cmd_pas_bits pas[0];
+};
+
+struct mlx5_ifc_rq_num_bits {
+        u8         reserved_0[0x8];
+        u8         rq_num[0x18];
+};
+
+struct mlx5_ifc_mac_address_layout_bits {
+        u8         reserved_0[0x10];
+        u8         mac_addr_47_32[0x10];
+
+        u8         mac_addr_31_0[0x20];
+};
+
+struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
+        u8         reserved_0[0xa0];
+
+        u8         min_time_between_cnps[0x20];
+
+        u8         reserved_1[0x12];
+        u8         cnp_dscp[0x6];
+        u8         reserved_2[0x5];
+        u8         cnp_802p_prio[0x3];
+
+        u8         reserved_3[0x720];
+};
+
+struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
+        u8         reserved_0[0x60];
+
+        u8         reserved_1[0x4];
+        u8         clamp_tgt_rate[0x1];
+        u8         reserved_2[0x3];
+        u8         clamp_tgt_rate_after_time_inc[0x1];
+        u8         reserved_3[0x17];
+
+        u8         reserved_4[0x20];
+
+        u8         rpg_time_reset[0x20];
+
+        u8         rpg_byte_reset[0x20];
+
+        u8         rpg_threshold[0x20];
+
+        u8         rpg_max_rate[0x20];
+
+        u8         rpg_ai_rate[0x20];
+
+        u8         rpg_hai_rate[0x20];
+
+        u8         rpg_gd[0x20];
+
+        u8         rpg_min_dec_fac[0x20];
+
+        u8         rpg_min_rate[0x20];
+
+        u8         reserved_5[0xe0];
+
+        u8         rate_to_set_on_first_cnp[0x20];
+
+        u8         dce_tcp_g[0x20];
+
+        u8         dce_tcp_rtt[0x20];
+
+        u8         rate_reduce_monitor_period[0x20];
+
+        u8         reserved_6[0x20];
+
+        u8         initial_alpha_value[0x20];
+
+        u8         reserved_7[0x4a0];
+};
+
+struct mlx5_ifc_cong_control_802_1qau_rp_bits {
+        u8         reserved_0[0x80];
+
+        u8         rppp_max_rps[0x20];
+
+        u8         rpg_time_reset[0x20];
+
+        u8         rpg_byte_reset[0x20];
+
+        u8         rpg_threshold[0x20];
+
+        u8         rpg_max_rate[0x20];
+
+        u8         rpg_ai_rate[0x20];
+
+        u8         rpg_hai_rate[0x20];
+
+        u8         rpg_gd[0x20];
+
+        u8         rpg_min_dec_fac[0x20];
+
+        u8         rpg_min_rate[0x20];
+
+        u8         reserved_1[0x640];
+};
+
+enum {
+        MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
+        MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
+        MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
+};
+
+struct mlx5_ifc_resize_field_select_bits {
+        u8         resize_field_select[0x20];
+};
+
+enum {
+        MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
+        MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
+        MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
+        MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
+};
+
+struct mlx5_ifc_modify_field_select_bits {
+        u8         modify_field_select[0x20];
+};
+
+struct mlx5_ifc_field_select_r_roce_np_bits {
+        u8         field_select_r_roce_np[0x20];
+};
+
+struct mlx5_ifc_field_select_r_roce_rp_bits {
+        u8         field_select_r_roce_rp[0x20];
+};
+
+enum {
+        MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
+        MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
+        MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
+        MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
+        MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
+        MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
+        MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
+        MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
+        MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
+        MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
+};
+
+struct mlx5_ifc_field_select_802_1qau_rp_bits {
+        u8         field_select_8021qaurp[0x20];
+};
+
+struct mlx5_ifc_phys_layer_cntrs_bits {
+        u8         time_since_last_clear_high[0x20];
+
+        u8         time_since_last_clear_low[0x20];
+
+        u8         symbol_errors_high[0x20];
+
+        u8         symbol_errors_low[0x20];
+
+        u8         sync_headers_errors_high[0x20];
+
+        u8         sync_headers_errors_low[0x20];
+
+        u8         edpl_bip_errors_lane0_high[0x20];
+
+        u8         edpl_bip_errors_lane0_low[0x20];
+
+        u8         edpl_bip_errors_lane1_high[0x20];
+
+        u8         edpl_bip_errors_lane1_low[0x20];
+
+        u8         edpl_bip_errors_lane2_high[0x20];
+
+        u8         edpl_bip_errors_lane2_low[0x20];
+
+        u8         edpl_bip_errors_lane3_high[0x20];
+
+        u8         edpl_bip_errors_lane3_low[0x20];
+
+        u8         fc_fec_corrected_blocks_lane0_high[0x20];
+
+        u8         fc_fec_corrected_blocks_lane0_low[0x20];
+
+        u8         fc_fec_corrected_blocks_lane1_high[0x20];
+
+        u8         fc_fec_corrected_blocks_lane1_low[0x20];
+
+        u8         fc_fec_corrected_blocks_lane2_high[0x20];
+
+        u8         fc_fec_corrected_blocks_lane2_low[0x20];
+
+        u8         fc_fec_corrected_blocks_lane3_high[0x20];
+
+        u8         fc_fec_corrected_blocks_lane3_low[0x20];
+
+        u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
+
+        u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
+
+        u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
+
+        u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
+
+        u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
+
+        u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
+
+        u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
+
+        u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
+
+        u8         rs_fec_corrected_blocks_high[0x20];
+
+        u8         rs_fec_corrected_blocks_low[0x20];
+
+        u8         rs_fec_uncorrectable_blocks_high[0x20];
+
+        u8         rs_fec_uncorrectable_blocks_low[0x20];
+
+        u8         rs_fec_no_errors_blocks_high[0x20];
+
+        u8         rs_fec_no_errors_blocks_low[0x20];
+
+        u8         rs_fec_single_error_blocks_high[0x20];
+
+        u8         rs_fec_single_error_blocks_low[0x20];
+
+        u8         rs_fec_corrected_symbols_total_high[0x20];
+
+        u8         rs_fec_corrected_symbols_total_low[0x20];
+
+        u8         rs_fec_corrected_symbols_lane0_high[0x20];
+
+        u8         rs_fec_corrected_symbols_lane0_low[0x20];
+
+        u8         rs_fec_corrected_symbols_lane1_high[0x20];
+
+        u8         rs_fec_corrected_symbols_lane1_low[0x20];
+
+        u8         rs_fec_corrected_symbols_lane2_high[0x20];
+
+        u8         rs_fec_corrected_symbols_lane2_low[0x20];
+
+        u8         rs_fec_corrected_symbols_lane3_high[0x20];
+
+        u8         rs_fec_corrected_symbols_lane3_low[0x20];
+
+        u8         link_down_events[0x20];
+
+        u8         successful_recovery_events[0x20];
+
+        u8         reserved_0[0x180];
+};
+
+struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
+        u8         transmit_queue_high[0x20];
+
+        u8         transmit_queue_low[0x20];
+
+        u8         reserved_0[0x780];
+};
+
+struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
+        u8         rx_octets_high[0x20];
+
+        u8         rx_octets_low[0x20];
+
+        u8         reserved_0[0xc0];
+
+        u8         rx_frames_high[0x20];
+
+        u8         rx_frames_low[0x20];
+
+        u8         tx_octets_high[0x20];
+
+        u8         tx_octets_low[0x20];
+
+        u8         reserved_1[0xc0];
+
+        u8         tx_frames_high[0x20];
+
+        u8         tx_frames_low[0x20];
+
+        u8         rx_pause_high[0x20];
+
+        u8         rx_pause_low[0x20];
+
+        u8         rx_pause_duration_high[0x20];
+
+        u8         rx_pause_duration_low[0x20];
+
+        u8         tx_pause_high[0x20];
+
+        u8         tx_pause_low[0x20];
+
+        u8         tx_pause_duration_high[0x20];
+
+        u8         tx_pause_duration_low[0x20];
+
+        u8         rx_pause_transition_high[0x20];
+
+        u8         rx_pause_transition_low[0x20];
+
+        u8         reserved_2[0x400];
+};
+
+struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
+        u8         port_transmit_wait_high[0x20];
+
+        u8         port_transmit_wait_low[0x20];
+
+        u8         reserved_0[0x780];
+};
+
+struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
+        u8         dot3stats_alignment_errors_high[0x20];
+
+        u8         dot3stats_alignment_errors_low[0x20];
+
+        u8         dot3stats_fcs_errors_high[0x20];
+
+        u8         dot3stats_fcs_errors_low[0x20];
+
+        u8         dot3stats_single_collision_frames_high[0x20];
+
+        u8         dot3stats_single_collision_frames_low[0x20];
+
+        u8         dot3stats_multiple_collision_frames_high[0x20];
+
+        u8         dot3stats_multiple_collision_frames_low[0x20];
+
+        u8         dot3stats_sqe_test_errors_high[0x20];
+
+        u8         dot3stats_sqe_test_errors_low[0x20];
+
+        u8         dot3stats_deferred_transmissions_high[0x20];
+
+        u8         dot3stats_deferred_transmissions_low[0x20];
+
+        u8         dot3stats_late_collisions_high[0x20];
+
+        u8         dot3stats_late_collisions_low[0x20];
+
+        u8         dot3stats_excessive_collisions_high[0x20];
+
+        u8         dot3stats_excessive_collisions_low[0x20];
+
+        u8         dot3stats_internal_mac_transmit_errors_high[0x20];
+
+        u8         dot3stats_internal_mac_transmit_errors_low[0x20];
+
+        u8         dot3stats_carrier_sense_errors_high[0x20];
+
+        u8         dot3stats_carrier_sense_errors_low[0x20];
+
+        u8         dot3stats_frame_too_longs_high[0x20];
+
+        u8         dot3stats_frame_too_longs_low[0x20];
+
+        u8         dot3stats_internal_mac_receive_errors_high[0x20];
+
+        u8         dot3stats_internal_mac_receive_errors_low[0x20];
+
+        u8         dot3stats_symbol_errors_high[0x20];
+
+        u8         dot3stats_symbol_errors_low[0x20];
+
+        u8         dot3control_in_unknown_opcodes_high[0x20];
+
+        u8         dot3control_in_unknown_opcodes_low[0x20];
+
+        u8         dot3in_pause_frames_high[0x20];
+
+        u8         dot3in_pause_frames_low[0x20];
+
+        u8         dot3out_pause_frames_high[0x20];
+
+        u8         dot3out_pause_frames_low[0x20];
+
+        u8         reserved_0[0x3c0];
+};
+
+struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
+        u8         ether_stats_drop_events_high[0x20];
+
+        u8         ether_stats_drop_events_low[0x20];
+
+        u8         ether_stats_octets_high[0x20];
+
+        u8         ether_stats_octets_low[0x20];
+
+        u8         ether_stats_pkts_high[0x20];
+
+        u8         ether_stats_pkts_low[0x20];
+
+        u8         ether_stats_broadcast_pkts_high[0x20];
+
+        u8         ether_stats_broadcast_pkts_low[0x20];
+
+        u8         ether_stats_multicast_pkts_high[0x20];
+
+        u8         ether_stats_multicast_pkts_low[0x20];
+
+        u8         ether_stats_crc_align_errors_high[0x20];
+
+        u8         ether_stats_crc_align_errors_low[0x20];
+
+        u8         ether_stats_undersize_pkts_high[0x20];
+
+        u8         ether_stats_undersize_pkts_low[0x20];
+
+        u8         ether_stats_oversize_pkts_high[0x20];
+
+        u8         ether_stats_oversize_pkts_low[0x20];
+
+        u8         ether_stats_fragments_high[0x20];
+
+        u8         ether_stats_fragments_low[0x20];
+
+        u8         ether_stats_jabbers_high[0x20];
+
+        u8         ether_stats_jabbers_low[0x20];
+
+        u8         ether_stats_collisions_high[0x20];
+
+        u8         ether_stats_collisions_low[0x20];
+
+        u8         ether_stats_pkts64octets_high[0x20];
+
+        u8         ether_stats_pkts64octets_low[0x20];
+
+        u8         ether_stats_pkts65to127octets_high[0x20];
+
+        u8         ether_stats_pkts65to127octets_low[0x20];
+
+        u8         ether_stats_pkts128to255octets_high[0x20];
+
+        u8         ether_stats_pkts128to255octets_low[0x20];
+
+        u8         ether_stats_pkts256to511octets_high[0x20];
+
+        u8         ether_stats_pkts256to511octets_low[0x20];
+
+        u8         ether_stats_pkts512to1023octets_high[0x20];
+
+        u8         ether_stats_pkts512to1023octets_low[0x20];
+
+        u8         ether_stats_pkts1024to1518octets_high[0x20];
+
+        u8         ether_stats_pkts1024to1518octets_low[0x20];
+
+        u8         ether_stats_pkts1519to2047octets_high[0x20];
+
+        u8         ether_stats_pkts1519to2047octets_low[0x20];
+
+        u8         ether_stats_pkts2048to4095octets_high[0x20];
+
+        u8         ether_stats_pkts2048to4095octets_low[0x20];
+
+        u8         ether_stats_pkts4096to8191octets_high[0x20];
+
+        u8         ether_stats_pkts4096to8191octets_low[0x20];
+
+        u8         ether_stats_pkts8192to10239octets_high[0x20];
+
+        u8         ether_stats_pkts8192to10239octets_low[0x20];
+
+        u8         reserved_0[0x280];
+};
+
+struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
+        u8         if_in_octets_high[0x20];
+
+        u8         if_in_octets_low[0x20];
+
+        u8         if_in_ucast_pkts_high[0x20];
+
+        u8         if_in_ucast_pkts_low[0x20];
+
+        u8         if_in_discards_high[0x20];
+
+        u8         if_in_discards_low[0x20];
+
+        u8         if_in_errors_high[0x20];
+
+        u8         if_in_errors_low[0x20];
+
+        u8         if_in_unknown_protos_high[0x20];
+
+        u8         if_in_unknown_protos_low[0x20];
+
+        u8         if_out_octets_high[0x20];
+
+        u8         if_out_octets_low[0x20];
+
+        u8         if_out_ucast_pkts_high[0x20];
+
+        u8         if_out_ucast_pkts_low[0x20];
+
+        u8         if_out_discards_high[0x20];
+
+        u8         if_out_discards_low[0x20];
+
+        u8         if_out_errors_high[0x20];
+
+        u8         if_out_errors_low[0x20];
+
+        u8         if_in_multicast_pkts_high[0x20];
+
+        u8         if_in_multicast_pkts_low[0x20];
+
+        u8         if_in_broadcast_pkts_high[0x20];
+
+        u8         if_in_broadcast_pkts_low[0x20];
+
+        u8         if_out_multicast_pkts_high[0x20];
+
+        u8         if_out_multicast_pkts_low[0x20];
+
+        u8         if_out_broadcast_pkts_high[0x20];
+
+        u8         if_out_broadcast_pkts_low[0x20];
+
+        u8         reserved_0[0x480];
+};
+
+struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
+        u8         a_frames_transmitted_ok_high[0x20];
+
+        u8         a_frames_transmitted_ok_low[0x20];
+
+        u8         a_frames_received_ok_high[0x20];
+
+        u8         a_frames_received_ok_low[0x20];
+
+        u8         a_frame_check_sequence_errors_high[0x20];
+
+        u8         a_frame_check_sequence_errors_low[0x20];
+
+        u8         a_alignment_errors_high[0x20];
+
+        u8         a_alignment_errors_low[0x20];
+
+        u8         a_octets_transmitted_ok_high[0x20];
+
+        u8         a_octets_transmitted_ok_low[0x20];
+
+        u8         a_octets_received_ok_high[0x20];
+
+        u8         a_octets_received_ok_low[0x20];
+
+        u8         a_multicast_frames_xmitted_ok_high[0x20];
+
+        u8         a_multicast_frames_xmitted_ok_low[0x20];
+
+        u8         a_broadcast_frames_xmitted_ok_high[0x20];
+
+        u8         a_broadcast_frames_xmitted_ok_low[0x20];
+
+        u8         a_multicast_frames_received_ok_high[0x20];
+
+        u8         a_multicast_frames_received_ok_low[0x20];
+
+        u8         a_broadcast_frames_received_ok_high[0x20];
+
+        u8         a_broadcast_frames_received_ok_low[0x20];
+
+        u8         a_in_range_length_errors_high[0x20];
+
+        u8         a_in_range_length_errors_low[0x20];
+
+        u8         a_out_of_range_length_field_high[0x20];
+
+        u8         a_out_of_range_length_field_low[0x20];
+
+        u8         a_frame_too_long_errors_high[0x20];
+
+        u8         a_frame_too_long_errors_low[0x20];
+
+        u8         a_symbol_error_during_carrier_high[0x20];
+
+        u8         a_symbol_error_during_carrier_low[0x20];
+
+        u8         a_mac_control_frames_transmitted_high[0x20];
+
+        u8         a_mac_control_frames_transmitted_low[0x20];
+
+        u8         a_mac_control_frames_received_high[0x20];
+
+        u8         a_mac_control_frames_received_low[0x20];
+
+        u8         a_unsupported_opcodes_received_high[0x20];
+
+        u8         a_unsupported_opcodes_received_low[0x20];
+
+        u8         a_pause_mac_ctrl_frames_received_high[0x20];
+
+        u8         a_pause_mac_ctrl_frames_received_low[0x20];
+
+        u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
+
+        u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
+
+        u8         reserved_0[0x300];
+};
+
+struct mlx5_ifc_cmd_inter_comp_event_bits {
+        u8         command_completion_vector[0x20];
+
+        u8         reserved_0[0xc0];
+};
+
+struct mlx5_ifc_stall_vl_event_bits {
+        u8         reserved_0[0x18];
+        u8         port_num[0x1];
+        u8         reserved_1[0x3];
+        u8         vl[0x4];
+
+        u8         reserved_2[0xa0];
+};
+
+struct mlx5_ifc_db_bf_congestion_event_bits {
+        u8         event_subtype[0x8];
+        u8         reserved_0[0x8];
+        u8         congestion_level[0x8];
+        u8         reserved_1[0x8];
+
+        u8         reserved_2[0xa0];
+};
+
+struct mlx5_ifc_gpio_event_bits {
+        u8         reserved_0[0x60];
+
+        u8         gpio_event_hi[0x20];
+
+        u8         gpio_event_lo[0x20];
+
+        u8         reserved_1[0x40];
+};
+
+struct mlx5_ifc_port_state_change_event_bits {
+        u8         reserved_0[0x40];
+
+        u8         port_num[0x4];
+        u8         reserved_1[0x1c];
+
+        u8         reserved_2[0x80];
+};
+
+struct mlx5_ifc_dropped_packet_logged_bits {
+        u8         reserved_0[0xe0];
+};
+
+enum {
+        MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
+        MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
+};
+
+struct mlx5_ifc_cq_error_bits {
+        u8         reserved_0[0x8];
+        u8         cqn[0x18];
+
+        u8         reserved_1[0x20];
+
+        u8         reserved_2[0x18];
+        u8         syndrome[0x8];
+
+        u8         reserved_3[0x80];
+};
+
+struct mlx5_ifc_rdma_page_fault_event_bits {
+        u8         bytes_committed[0x20];
+
+        u8         r_key[0x20];
+
+        u8         reserved_0[0x10];
+        u8         packet_len[0x10];
+
+        u8         rdma_op_len[0x20];
+
+        u8         rdma_va[0x40];
+
+        u8         reserved_1[0x5];
+        u8         rdma[0x1];
+        u8         write[0x1];
+        u8         requestor[0x1];
+        u8         qp_number[0x18];
+};
+
+struct mlx5_ifc_wqe_associated_page_fault_event_bits {
+        u8         bytes_committed[0x20];
+
+        u8         reserved_0[0x10];
+        u8         wqe_index[0x10];
+
+        u8         reserved_1[0x10];
+        u8         len[0x10];
+
+        u8         reserved_2[0x60];
+
+        u8         reserved_3[0x5];
+        u8         rdma[0x1];
+        u8         write_read[0x1];
+        u8         requestor[0x1];
+        u8         qpn[0x18];
+};
+
+struct mlx5_ifc_qp_events_bits {
+        u8         reserved_0[0xa0];
+
+        u8         type[0x8];
+        u8         reserved_1[0x18];
+
+        u8         reserved_2[0x8];
+        u8         qpn_rqn_sqn[0x18];
+};
+
+struct mlx5_ifc_dct_events_bits {
+        u8         reserved_0[0xc0];
+
+        u8         reserved_1[0x8];
+        u8         dct_number[0x18];
+};
+
+struct mlx5_ifc_comp_event_bits {
+        u8         reserved_0[0xc0];
+
+        u8         reserved_1[0x8];
+        u8         cq_number[0x18];
+};
+
+enum {
+        MLX5_QPC_STATE_RST        = 0x0,
+        MLX5_QPC_STATE_INIT       = 0x1,
+        MLX5_QPC_STATE_RTR        = 0x2,
+        MLX5_QPC_STATE_RTS        = 0x3,
+        MLX5_QPC_STATE_SQER       = 0x4,
+        MLX5_QPC_STATE_ERR        = 0x6,
+        MLX5_QPC_STATE_SQD        = 0x7,
+        MLX5_QPC_STATE_SUSPENDED  = 0x9,
+};
+
+enum {
+        MLX5_QPC_ST_RC            = 0x0,
+        MLX5_QPC_ST_UC            = 0x1,
+        MLX5_QPC_ST_UD            = 0x2,
+        MLX5_QPC_ST_XRC           = 0x3,
+        MLX5_QPC_ST_DCI           = 0x5,
+        MLX5_QPC_ST_QP0           = 0x7,
+        MLX5_QPC_ST_QP1           = 0x8,
+        MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
+        MLX5_QPC_ST_REG_UMR       = 0xc,
+};
+
+enum {
+        MLX5_QPC_PM_STATE_ARMED     = 0x0,
+        MLX5_QPC_PM_STATE_REARM     = 0x1,
+        MLX5_QPC_PM_STATE_RESERVED  = 0x2,
+        MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
+};
+
+enum {
+        MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
+        MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
+};
+
+enum {
+        MLX5_QPC_MTU_256_BYTES        = 0x1,
+        MLX5_QPC_MTU_512_BYTES        = 0x2,
+        MLX5_QPC_MTU_1K_BYTES         = 0x3,
+        MLX5_QPC_MTU_2K_BYTES         = 0x4,
+        MLX5_QPC_MTU_4K_BYTES         = 0x5,
+        MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
+};
+
+enum {
+        MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
+        MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
+        MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
+        MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
+        MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
+        MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
+        MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
+        MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
+};
+
+enum {
+        MLX5_QPC_CS_REQ_DISABLE    = 0x0,
+        MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
+        MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
+};
+
+enum {
+        MLX5_QPC_CS_RES_DISABLE    = 0x0,
+        MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
+        MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
+};
+
+struct mlx5_ifc_qpc_bits {
+        u8         state[0x4];
+        u8         reserved_0[0x4];
+        u8         st[0x8];
+        u8         reserved_1[0x3];
+        u8         pm_state[0x2];
+        u8         reserved_2[0x7];
+        u8         end_padding_mode[0x2];
+        u8         reserved_3[0x2];
+
+        u8         wq_signature[0x1];
+        u8         block_lb_mc[0x1];
+        u8         atomic_like_write_en[0x1];
+        u8         latency_sensitive[0x1];
+        u8         reserved_4[0x1];
+        u8         drain_sigerr[0x1];
+        u8         reserved_5[0x2];
+        u8         pd[0x18];
+
+        u8         mtu[0x3];
+        u8         log_msg_max[0x5];
+        u8         reserved_6[0x1];
+        u8         log_rq_size[0x4];
+        u8         log_rq_stride[0x3];
+        u8         no_sq[0x1];
+        u8         log_sq_size[0x4];
+        u8         reserved_7[0x6];
+        u8         rlky[0x1];
+        u8         reserved_8[0x4];
+
+        u8         counter_set_id[0x8];
+        u8         uar_page[0x18];
+
+        u8         reserved_9[0x8];
+        u8         user_index[0x18];
+
+        u8         reserved_10[0x3];
+        u8         log_page_size[0x5];
+        u8         remote_qpn[0x18];
+
+        struct mlx5_ifc_ads_bits primary_address_path;
+
+        struct mlx5_ifc_ads_bits secondary_address_path;
+
+        u8         log_ack_req_freq[0x4];
+        u8         reserved_11[0x4];
+        u8         log_sra_max[0x3];
+        u8         reserved_12[0x2];
+        u8         retry_count[0x3];
+        u8         rnr_retry[0x3];
+        u8         reserved_13[0x1];
+        u8         fre[0x1];
+        u8         cur_rnr_retry[0x3];
+        u8         cur_retry_count[0x3];
+        u8         reserved_14[0x5];
+
+        u8         reserved_15[0x20];
+
+        u8         reserved_16[0x8];
+        u8         next_send_psn[0x18];
+
+        u8         reserved_17[0x8];
+        u8         cqn_snd[0x18];
+
+        u8         reserved_18[0x40];
+
+        u8         reserved_19[0x8];
+        u8         last_acked_psn[0x18];
+
+        u8         reserved_20[0x8];
+        u8         ssn[0x18];
+
+        u8         reserved_21[0x8];
+        u8         log_rra_max[0x3];
+        u8         reserved_22[0x1];
+        u8         atomic_mode[0x4];
+        u8         rre[0x1];
+        u8         rwe[0x1];
+        u8         rae[0x1];
+        u8         reserved_23[0x1];
+        u8         page_offset[0x6];
+        u8         reserved_24[0x3];
+        u8         cd_slave_receive[0x1];
+        u8         cd_slave_send[0x1];
+        u8         cd_master[0x1];
+
+        u8         reserved_25[0x3];
+        u8         min_rnr_nak[0x5];
+        u8         next_rcv_psn[0x18];
+
+        u8         reserved_26[0x8];
+        u8         xrcd[0x18];
+
+        u8         reserved_27[0x8];
+        u8         cqn_rcv[0x18];
+
+        u8         dbr_addr[0x40];
+
+        u8         q_key[0x20];
+
+        u8         reserved_28[0x5];
+        u8         rq_type[0x3];
+        u8         srqn_rmpn[0x18];
+
+        u8         reserved_29[0x8];
+        u8         rmsn[0x18];
+
+        u8         hw_sq_wqebb_counter[0x10];
+        u8         sw_sq_wqebb_counter[0x10];
+
+        u8         hw_rq_counter[0x20];
+
+        u8         sw_rq_counter[0x20];
+
+        u8         reserved_30[0x20];
+
+        u8         reserved_31[0xf];
+        u8         cgs[0x1];
+        u8         cs_req[0x8];
+        u8         cs_res[0x8];
+
+        u8         dc_access_key[0x40];
+
+        u8         reserved_32[0xc0];
+};
+
+struct mlx5_ifc_roce_addr_layout_bits {
+        u8         source_l3_address[16][0x8];
+
+        u8         reserved_0[0x3];
+        u8         vlan_valid[0x1];
+        u8         vlan_id[0xc];
+        u8         source_mac_47_32[0x10];
+
+        u8         source_mac_31_0[0x20];
+
+        u8         reserved_1[0x14];
+        u8         roce_l3_type[0x4];
+        u8         roce_version[0x8];
+
+        u8         reserved_2[0x20];
+};
+
+union mlx5_ifc_hca_cap_union_bits {
+        struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
+        struct mlx5_ifc_odp_cap_bits odp_cap;
+        struct mlx5_ifc_atomic_caps_bits atomic_caps;
+        struct mlx5_ifc_roce_cap_bits roce_cap;
+        struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
+        struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
+        u8         reserved_0[0x8000];
+};
+
+enum {
+        MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
+        MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
+        MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
+};
+
+struct mlx5_ifc_flow_context_bits {
+        u8         reserved_0[0x20];
+
+        u8         group_id[0x20];
+
+        u8         reserved_1[0x8];
+        u8         flow_tag[0x18];
+
+        u8         reserved_2[0x10];
+        u8         action[0x10];
+
+        u8         reserved_3[0x8];
+        u8         destination_list_size[0x18];
+
+        u8         reserved_4[0x160];
+
+        struct mlx5_ifc_fte_match_param_bits match_value;
+
+        u8         reserved_5[0x600];
+
+        struct mlx5_ifc_dest_format_struct_bits destination[0];
+};
+
+enum {
+        MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
+        MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
+};
+
+struct mlx5_ifc_xrc_srqc_bits {
+        u8         state[0x4];
+        u8         log_xrc_srq_size[0x4];
+        u8         reserved_0[0x18];
+
+        u8         wq_signature[0x1];
+        u8         cont_srq[0x1];
+        u8         reserved_1[0x1];
+        u8         rlky[0x1];
+        u8         basic_cyclic_rcv_wqe[0x1];
+        u8         log_rq_stride[0x3];
+        u8         xrcd[0x18];
+
+        u8         page_offset[0x6];
+        u8         reserved_2[0x2];
+        u8         cqn[0x18];
+
+        u8         reserved_3[0x20];
+
+        u8         user_index_equal_xrc_srqn[0x1];
+        u8         reserved_4[0x1];
+        u8         log_page_size[0x6];
+        u8         user_index[0x18];
+
+        u8         reserved_5[0x20];
+
+        u8         reserved_6[0x8];
+        u8         pd[0x18];
+
+        u8         lwm[0x10];
+        u8         wqe_cnt[0x10];
+
+        u8         reserved_7[0x40];
+
+        u8         db_record_addr_h[0x20];
+
+        u8         db_record_addr_l[0x1e];
+        u8         reserved_8[0x2];
+
+        u8         reserved_9[0x80];
+};
+
+struct mlx5_ifc_traffic_counter_bits {
+        u8         packets[0x40];
+
+        u8         octets[0x40];
+};
+
+struct mlx5_ifc_tisc_bits {
+        u8         reserved_0[0xc];
+        u8         prio[0x4];
+        u8         reserved_1[0x10];
+
+        u8         reserved_2[0x100];
+
+        u8         reserved_3[0x8];
+        u8         transport_domain[0x18];
+
+        u8         reserved_4[0x3c0];
+};
+
+enum {
+        MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
+        MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
+};
+
+enum {
+        MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
+        MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
+};
+
+enum {
+        MLX5_TIRC_RX_HASH_FN_HASH_NONE           = 0x0,
+        MLX5_TIRC_RX_HASH_FN_HASH_INVERTED_XOR8  = 0x1,
+        MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ       = 0x2,
+};
+
+enum {
+        MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_    = 0x1,
+        MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_  = 0x2,
+};
+
+struct mlx5_ifc_tirc_bits {
+        u8         reserved_0[0x20];
+
+        u8         disp_type[0x4];
+        u8         reserved_1[0x1c];
+
+        u8         reserved_2[0x40];
+
+        u8         reserved_3[0x4];
+        u8         lro_timeout_period_usecs[0x10];
+        u8         lro_enable_mask[0x4];
+        u8         lro_max_ip_payload_size[0x8];
+
+        u8         reserved_4[0x40];
+
+        u8         reserved_5[0x8];
+        u8         inline_rqn[0x18];
+
+        u8         rx_hash_symmetric[0x1];
+        u8         reserved_6[0x1];
+        u8         tunneled_offload_en[0x1];
+        u8         reserved_7[0x5];
+        u8         indirect_table[0x18];
+
+        u8         rx_hash_fn[0x4];
+        u8         reserved_8[0x2];
+        u8         self_lb_block[0x2];
+        u8         transport_domain[0x18];
+
+        u8         rx_hash_toeplitz_key[10][0x20];
+
+        struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
+
+        struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
+
+        u8         reserved_9[0x4c0];
+};
+
+enum {
+        MLX5_SRQC_STATE_GOOD   = 0x0,
+        MLX5_SRQC_STATE_ERROR  = 0x1,
+};
+
+struct mlx5_ifc_srqc_bits {
+        u8         state[0x4];
+        u8         log_srq_size[0x4];
+        u8         reserved_0[0x18];
+
+        u8         wq_signature[0x1];
+        u8         cont_srq[0x1];
+        u8         reserved_1[0x1];
+        u8         rlky[0x1];
+        u8         reserved_2[0x1];
+        u8         log_rq_stride[0x3];
+        u8         xrcd[0x18];
+
+        u8         page_offset[0x6];
+        u8         reserved_3[0x2];
+        u8         cqn[0x18];
+
+        u8         reserved_4[0x20];
+
+        u8         reserved_5[0x2];
+        u8         log_page_size[0x6];
+        u8         reserved_6[0x18];
+
+        u8         reserved_7[0x20];
+
+        u8         reserved_8[0x8];
+        u8         pd[0x18];
+
+        u8         lwm[0x10];
+        u8         wqe_cnt[0x10];
+
+        u8         reserved_9[0x40];
+
+        u8         dbr_addr[0x40];
+
+        u8         reserved_10[0x80];
+};
+
+enum {
+        MLX5_SQC_STATE_RST  = 0x0,
+        MLX5_SQC_STATE_RDY  = 0x1,
+        MLX5_SQC_STATE_ERR  = 0x3,
+};
+
+struct mlx5_ifc_sqc_bits {
+        u8         rlky[0x1];
+        u8         cd_master[0x1];
+        u8         fre[0x1];
+        u8         flush_in_error_en[0x1];
+        u8         reserved_0[0x4];
+        u8         state[0x4];
+        u8         reserved_1[0x14];
+
+        u8         reserved_2[0x8];
+        u8         user_index[0x18];
+
+        u8         reserved_3[0x8];
+        u8         cqn[0x18];
+
+        u8         reserved_4[0xa0];
+
+        u8         tis_lst_sz[0x10];
+        u8         reserved_5[0x10];
+
+        u8         reserved_6[0x40];
+
+        u8         reserved_7[0x8];
+        u8         tis_num_0[0x18];
+
+        struct mlx5_ifc_wq_bits wq;
+};
+
+struct mlx5_ifc_rqtc_bits {
+        u8         reserved_0[0xa0];
+
+        u8         reserved_1[0x10];
+        u8         rqt_max_size[0x10];
+
+        u8         reserved_2[0x10];
+        u8         rqt_actual_size[0x10];
+
+        u8         reserved_3[0x6a0];
+
+        struct mlx5_ifc_rq_num_bits rq_num[0];
+};
+
+enum {
+        MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
+        MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
+};
+
+enum {
+        MLX5_RQC_STATE_RST  = 0x0,
+        MLX5_RQC_STATE_RDY  = 0x1,
+        MLX5_RQC_STATE_ERR  = 0x3,
+};
+
+struct mlx5_ifc_rqc_bits {
+        u8         rlky[0x1];
+        u8         reserved_0[0x2];
+        u8         vsd[0x1];
+        u8         mem_rq_type[0x4];
+        u8         state[0x4];
+        u8         reserved_1[0x1];
+        u8         flush_in_error_en[0x1];
+        u8         reserved_2[0x12];
+
+        u8         reserved_3[0x8];
+        u8         user_index[0x18];
+
+        u8         reserved_4[0x8];
+        u8         cqn[0x18];
+
+        u8         counter_set_id[0x8];
+        u8         reserved_5[0x18];
+
+        u8         reserved_6[0x8];
+        u8         rmpn[0x18];
+
+        u8         reserved_7[0xe0];
+
+        struct mlx5_ifc_wq_bits wq;
+};
+
+enum {
+        MLX5_RMPC_STATE_RDY  = 0x1,
+        MLX5_RMPC_STATE_ERR  = 0x3,
+};
+
+struct mlx5_ifc_rmpc_bits {
+        u8         reserved_0[0x8];
+        u8         state[0x4];
+        u8         reserved_1[0x14];
+
+        u8         basic_cyclic_rcv_wqe[0x1];
+        u8         reserved_2[0x1f];
+
+        u8         reserved_3[0x140];
+
+        struct mlx5_ifc_wq_bits wq;
+};
+
+enum {
+        MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_UC_MAC_ADDRESS  = 0x0,
+};
+
+struct mlx5_ifc_nic_vport_context_bits {
+        u8         reserved_0[0x1f];
+        u8         roce_en[0x1];
+
+        u8         reserved_1[0x760];
+
+        u8         reserved_2[0x5];
+        u8         allowed_list_type[0x3];
+        u8         reserved_3[0xc];
+        u8         allowed_list_size[0xc];
+
+        struct mlx5_ifc_mac_address_layout_bits permanent_address;
+
+        u8         reserved_4[0x20];
+
+        u8         current_uc_mac_address[0][0x40];
+};
+
+enum {
+        MLX5_MKC_ACCESS_MODE_PA    = 0x0,
+        MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
+        MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
+};
+
+struct mlx5_ifc_mkc_bits {
+        u8         reserved_0[0x1];
+        u8         free[0x1];
+        u8         reserved_1[0xd];
+        u8         small_fence_on_rdma_read_response[0x1];
+        u8         umr_en[0x1];
+        u8         a[0x1];
+        u8         rw[0x1];
+        u8         rr[0x1];
+        u8         lw[0x1];
+        u8         lr[0x1];
+        u8         access_mode[0x2];
+        u8         reserved_2[0x8];
+
+        u8         qpn[0x18];
+        u8         mkey_7_0[0x8];
+
+        u8         reserved_3[0x20];
+
+        u8         length64[0x1];
+        u8         bsf_en[0x1];
+        u8         sync_umr[0x1];
+        u8         reserved_4[0x2];
+        u8         expected_sigerr_count[0x1];
+        u8         reserved_5[0x1];
+        u8         en_rinval[0x1];
+        u8         pd[0x18];
+
+        u8         start_addr[0x40];
+
+        u8         len[0x40];
+
+        u8         bsf_octword_size[0x20];
+
+        u8         reserved_6[0x80];
+
+        u8         translations_octword_size[0x20];
+
+        u8         reserved_7[0x1b];
+        u8         log_page_size[0x5];
+
+        u8         reserved_8[0x20];
+};
+
+struct mlx5_ifc_pkey_bits {
+        u8         reserved_0[0x10];
+        u8         pkey[0x10];
+};
+
+struct mlx5_ifc_array128_auto_bits {
+        u8         array128_auto[16][0x8];
+};
+
+struct mlx5_ifc_hca_vport_context_bits {
+        u8         field_select[0x20];
+
+        u8         reserved_0[0xe0];
+
+        u8         sm_virt_aware[0x1];
+        u8         has_smi[0x1];
+        u8         has_raw[0x1];
+        u8         grh_required[0x1];
+        u8         reserved_1[0xc];
+        u8         port_physical_state[0x4];
+        u8         vport_state_policy[0x4];
+        u8         port_state[0x4];
+        u8         vport_state[0x4];
+
+        u8         reserved_2[0x20];
+
+        u8         system_image_guid[0x40];
+
+        u8         port_guid[0x40];
+
+        u8         node_guid[0x40];
+
+        u8         cap_mask1[0x20];
+
+        u8         cap_mask1_field_select[0x20];
+
+        u8         cap_mask2[0x20];
+
+        u8         cap_mask2_field_select[0x20];
+
+        u8         reserved_3[0x80];
+
+        u8         lid[0x10];
+        u8         reserved_4[0x4];
+        u8         init_type_reply[0x4];
+        u8         lmc[0x3];
+        u8         subnet_timeout[0x5];
+
+        u8         sm_lid[0x10];
+        u8         sm_sl[0x4];
+        u8         reserved_5[0xc];
+
+        u8         qkey_violation_counter[0x10];
+        u8         pkey_violation_counter[0x10];
+
+        u8         reserved_6[0xca0];
+};
+
+enum {
+        MLX5_EQC_STATUS_OK                = 0x0,
+        MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
+};
+
+enum {
+        MLX5_EQC_ST_ARMED  = 0x9,
+        MLX5_EQC_ST_FIRED  = 0xa,
+};
+
+struct mlx5_ifc_eqc_bits {
+        u8         status[0x4];
+        u8         reserved_0[0x9];
+        u8         ec[0x1];
+        u8         oi[0x1];
+        u8         reserved_1[0x5];
+        u8         st[0x4];
+        u8         reserved_2[0x8];
+
+        u8         reserved_3[0x20];
+
+        u8         reserved_4[0x14];
+        u8         page_offset[0x6];
+        u8         reserved_5[0x6];
+
+        u8         reserved_6[0x3];
+        u8         log_eq_size[0x5];
+        u8         uar_page[0x18];
+
+        u8         reserved_7[0x20];
+
+        u8         reserved_8[0x18];
+        u8         intr[0x8];
+
+        u8         reserved_9[0x3];
+        u8         log_page_size[0x5];
+        u8         reserved_10[0x18];
+
+        u8         reserved_11[0x60];
+
+        u8         reserved_12[0x8];
+        u8         consumer_counter[0x18];
+
+        u8         reserved_13[0x8];
+        u8         producer_counter[0x18];
+
+        u8         reserved_14[0x80];
+};
+
+enum {
+        MLX5_DCTC_STATE_ACTIVE    = 0x0,
+        MLX5_DCTC_STATE_DRAINING  = 0x1,
+        MLX5_DCTC_STATE_DRAINED   = 0x2,
+};
+
+enum {
+        MLX5_DCTC_CS_RES_DISABLE    = 0x0,
+        MLX5_DCTC_CS_RES_NA         = 0x1,
+        MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
+};
+
+enum {
+        MLX5_DCTC_MTU_256_BYTES  = 0x1,
+        MLX5_DCTC_MTU_512_BYTES  = 0x2,
+        MLX5_DCTC_MTU_1K_BYTES   = 0x3,
+        MLX5_DCTC_MTU_2K_BYTES   = 0x4,
+        MLX5_DCTC_MTU_4K_BYTES   = 0x5,
+};
+
+struct mlx5_ifc_dctc_bits {
+        u8         reserved_0[0x4];
+        u8         state[0x4];
+        u8         reserved_1[0x18];
+
+        u8         reserved_2[0x8];
+        u8         user_index[0x18];
+
+        u8         reserved_3[0x8];
+        u8         cqn[0x18];
+
+        u8         counter_set_id[0x8];
+        u8         atomic_mode[0x4];
+        u8         rre[0x1];
+        u8         rwe[0x1];
+        u8         rae[0x1];
+        u8         atomic_like_write_en[0x1];
+        u8         latency_sensitive[0x1];
+        u8         rlky[0x1];
+        u8         free_ar[0x1];
+        u8         reserved_4[0xd];
+
+        u8         reserved_5[0x8];
+        u8         cs_res[0x8];
+        u8         reserved_6[0x3];
+        u8         min_rnr_nak[0x5];
+        u8         reserved_7[0x8];
+
+        u8         reserved_8[0x8];
+        u8         srqn[0x18];
+
+        u8         reserved_9[0x8];
+        u8         pd[0x18];
+
+        u8         tclass[0x8];
+        u8         reserved_10[0x4];
+        u8         flow_label[0x14];
+
+        u8         dc_access_key[0x40];
+
+        u8         reserved_11[0x5];
+        u8         mtu[0x3];
+        u8         port[0x8];
+        u8         pkey_index[0x10];
+
+        u8         reserved_12[0x8];
+        u8         my_addr_index[0x8];
+        u8         reserved_13[0x8];
+        u8         hop_limit[0x8];
+
+        u8         dc_access_key_violation_count[0x20];
+
+        u8         reserved_14[0x14];
+        u8         dei_cfi[0x1];
+        u8         eth_prio[0x3];
+        u8         ecn[0x2];
+        u8         dscp[0x6];
+
+        u8         reserved_15[0x40];
+};
+
+enum {
+        MLX5_CQC_STATUS_OK             = 0x0,
+        MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
+        MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
+};
+
+enum {
+        MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
+        MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
+};
+
+enum {
+        MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
+        MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
+        MLX5_CQC_ST_FIRED                                 = 0xa,
+};
+
+struct mlx5_ifc_cqc_bits {
+        u8         status[0x4];
+        u8         reserved_0[0x4];
+        u8         cqe_sz[0x3];
+        u8         cc[0x1];
+        u8         reserved_1[0x1];
+        u8         scqe_break_moderation_en[0x1];
+        u8         oi[0x1];
+        u8         reserved_2[0x2];
+        u8         cqe_zip_en[0x1];
+        u8         mini_cqe_res_format[0x2];
+        u8         st[0x4];
+        u8         reserved_3[0x8];
+
+        u8         reserved_4[0x20];
+
+        u8         reserved_5[0x14];
+        u8         page_offset[0x6];
+        u8         reserved_6[0x6];
+
+        u8         reserved_7[0x3];
+        u8         log_cq_size[0x5];
+        u8         uar_page[0x18];
+
+        u8         reserved_8[0x4];
+        u8         cq_period[0xc];
+        u8         cq_max_count[0x10];
+
+        u8         reserved_9[0x18];
+        u8         c_eqn[0x8];
+
+        u8         reserved_10[0x3];
+        u8         log_page_size[0x5];
+        u8         reserved_11[0x18];
+
+        u8         reserved_12[0x20];
+
+        u8         reserved_13[0x8];
+        u8         last_notified_index[0x18];
+
+        u8         reserved_14[0x8];
+        u8         last_solicit_index[0x18];
+
+        u8         reserved_15[0x8];
+        u8         consumer_counter[0x18];
+
+        u8         reserved_16[0x8];
+        u8         producer_counter[0x18];
+
+        u8         reserved_17[0x40];
+
+        u8         dbr_addr[0x40];
+};
+
+union mlx5_ifc_cong_control_roce_ecn_auto_bits {
+        struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
+        struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
+        struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
+        u8         reserved_0[0x800];
+};
+
+struct mlx5_ifc_query_adapter_param_block_bits {
+        u8         reserved_0[0xc0];
+
+        u8         reserved_1[0x8];
+        u8         ieee_vendor_id[0x18];
+
+        u8         reserved_2[0x10];
+        u8         vsd_vendor_id[0x10];
+
+        u8         vsd[208][0x8];
+
+        u8         vsd_contd_psid[16][0x8];
+};
+
+union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
+        struct mlx5_ifc_modify_field_select_bits modify_field_select;
+        struct mlx5_ifc_resize_field_select_bits resize_field_select;
+        u8         reserved_0[0x20];
+};
+
+union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
+        struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
+        struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
+        struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
+        u8         reserved_0[0x20];
+};
+
+union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
+        struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
+        struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
+        struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
+        struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
+        struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
+        struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
+        struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
+        struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
+        u8         reserved_0[0x7c0];
+};
+
+union mlx5_ifc_event_auto_bits {
+        struct mlx5_ifc_comp_event_bits comp_event;
+        struct mlx5_ifc_dct_events_bits dct_events;
+        struct mlx5_ifc_qp_events_bits qp_events;
+        struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
+        struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
+        struct mlx5_ifc_cq_error_bits cq_error;
+        struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
+        struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
+        struct mlx5_ifc_gpio_event_bits gpio_event;
+        struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
+        struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
+        struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
+        u8         reserved_0[0xe0];
+};
+
+struct mlx5_ifc_health_buffer_bits {
+        u8         reserved_0[0x100];
+
+        u8         assert_existptr[0x20];
+
+        u8         assert_callra[0x20];
+
+        u8         reserved_1[0x40];
+
+        u8         fw_version[0x20];
+
+        u8         hw_id[0x20];
+
+        u8         reserved_2[0x20];
+
+        u8         irisc_index[0x8];
+        u8         synd[0x8];
+        u8         ext_synd[0x10];
+};
+
+struct mlx5_ifc_register_loopback_control_bits {
+        u8         no_lb[0x1];
+        u8         reserved_0[0x7];
+        u8         port[0x8];
+        u8         reserved_1[0x10];
+
+        u8         reserved_2[0x60];
+};
+
+struct mlx5_ifc_teardown_hca_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+};
+
+enum {
+        MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
+        MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE     = 0x1,
+};
+
+struct mlx5_ifc_teardown_hca_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x10];
+        u8         profile[0x10];
+
+        u8         reserved_3[0x20];
+};
+
+struct mlx5_ifc_sqerr2rts_qp_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+};
+
+struct mlx5_ifc_sqerr2rts_qp_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x8];
+        u8         qpn[0x18];
+
+        u8         reserved_3[0x20];
+
+        u8         opt_param_mask[0x20];
+
+        u8         reserved_4[0x20];
+
+        struct mlx5_ifc_qpc_bits qpc;
+
+        u8         reserved_5[0x80];
+};
+
+struct mlx5_ifc_sqd2rts_qp_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+};
+
+struct mlx5_ifc_sqd2rts_qp_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x8];
+        u8         qpn[0x18];
+
+        u8         reserved_3[0x20];
+
+        u8         opt_param_mask[0x20];
+
+        u8         reserved_4[0x20];
+
+        struct mlx5_ifc_qpc_bits qpc;
+
+        u8         reserved_5[0x80];
+};
+
+struct mlx5_ifc_set_roce_address_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+};
+
+struct mlx5_ifc_set_roce_address_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         roce_address_index[0x10];
+        u8         reserved_2[0x10];
+
+        u8         reserved_3[0x20];
+
+        struct mlx5_ifc_roce_addr_layout_bits roce_address;
+};
+
+struct mlx5_ifc_set_mad_demux_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+};
+
+enum {
+        MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
+        MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
+};
+
+struct mlx5_ifc_set_mad_demux_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x20];
+
+        u8         reserved_3[0x6];
+        u8         demux_mode[0x2];
+        u8         reserved_4[0x18];
+};
+
+struct mlx5_ifc_set_l2_table_entry_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+};
+
+struct mlx5_ifc_set_l2_table_entry_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x60];
+
+        u8         reserved_3[0x8];
+        u8         table_index[0x18];
+
+        u8         reserved_4[0x20];
+
+        u8         reserved_5[0x13];
+        u8         vlan_valid[0x1];
+        u8         vlan[0xc];
+
+        struct mlx5_ifc_mac_address_layout_bits mac_address;
+
+        u8         reserved_6[0xc0];
+};
+
+struct mlx5_ifc_set_issi_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+};
+
+struct mlx5_ifc_set_issi_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x10];
+        u8         current_issi[0x10];
+
+        u8         reserved_3[0x20];
+};
+
+struct mlx5_ifc_set_hca_cap_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_set_hca_cap_in_bits {
@@ -313,10 +2764,653 @@ struct mlx5_ifc_set_hca_cap_in_bits {
 
         u8         reserved_2[0x40];
 
-        struct mlx5_ifc_cmd_hca_cap_bits hca_capability_struct;
+        union mlx5_ifc_hca_cap_union_bits capability;
 };
 
-struct mlx5_ifc_query_hca_cap_in_bits {
+struct mlx5_ifc_set_fte_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+};
+
+struct mlx5_ifc_set_fte_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x40];
+
+        u8         table_type[0x8];
+        u8         reserved_3[0x18];
+
+        u8         reserved_4[0x8];
+        u8         table_id[0x18];
+
+        u8         reserved_5[0x40];
+
+        u8         flow_index[0x20];
+
+        u8         reserved_6[0xe0];
+
+        struct mlx5_ifc_flow_context_bits flow_context;
+};
+
+struct mlx5_ifc_rts2rts_qp_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+};
+
+struct mlx5_ifc_rts2rts_qp_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x8];
+        u8         qpn[0x18];
+
+        u8         reserved_3[0x20];
+
+        u8         opt_param_mask[0x20];
+
+        u8         reserved_4[0x20];
+
+        struct mlx5_ifc_qpc_bits qpc;
+
+        u8         reserved_5[0x80];
+};
+
+struct mlx5_ifc_rtr2rts_qp_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+};
+
+struct mlx5_ifc_rtr2rts_qp_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x8];
+        u8         qpn[0x18];
+
+        u8         reserved_3[0x20];
+
+        u8         opt_param_mask[0x20];
+
+        u8         reserved_4[0x20];
+
+        struct mlx5_ifc_qpc_bits qpc;
+
+        u8         reserved_5[0x80];
+};
+
+struct mlx5_ifc_rst2init_qp_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+};
+
+struct mlx5_ifc_rst2init_qp_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x8];
+        u8         qpn[0x18];
+
+        u8         reserved_3[0x20];
+
+        u8         opt_param_mask[0x20];
+
+        u8         reserved_4[0x20];
+
+        struct mlx5_ifc_qpc_bits qpc;
+
+        u8         reserved_5[0x80];
+};
+
+struct mlx5_ifc_query_xrc_srq_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+
+        struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
+
+        u8         reserved_2[0x600];
+
+        u8         pas[0][0x40];
+};
+
+struct mlx5_ifc_query_xrc_srq_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x8];
+        u8         xrc_srqn[0x18];
+
+        u8         reserved_3[0x20];
+};
+
+enum {
+        MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
+        MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
+};
+
+struct mlx5_ifc_query_vport_state_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x20];
+
+        u8         reserved_2[0x18];
+        u8         admin_state[0x4];
+        u8         state[0x4];
+};
+
+enum {
+        MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT  = 0x0,
+};
+
+struct mlx5_ifc_query_vport_state_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         other_vport[0x1];
+        u8         reserved_2[0xf];
+        u8         vport_number[0x10];
+
+        u8         reserved_3[0x20];
+};
+
+struct mlx5_ifc_query_vport_counter_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+
+        struct mlx5_ifc_traffic_counter_bits received_errors;
+
+        struct mlx5_ifc_traffic_counter_bits transmit_errors;
+
+        struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
+
+        struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
+
+        struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
+
+        struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
+
+        struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
+
+        struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
+
+        struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
+
+        struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
+
+        struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
+
+        struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
+
+        u8         reserved_2[0xa00];
+};
+
+enum {
+        MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
+};
+
+struct mlx5_ifc_query_vport_counter_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         other_vport[0x1];
+        u8         reserved_2[0xf];
+        u8         vport_number[0x10];
+
+        u8         reserved_3[0x60];
+
+        u8         clear[0x1];
+        u8         reserved_4[0x1f];
+
+        u8         reserved_5[0x20];
+};
+
+struct mlx5_ifc_query_tis_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+
+        struct mlx5_ifc_tisc_bits tis_context;
+};
+
+struct mlx5_ifc_query_tis_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x8];
+        u8         tisn[0x18];
+
+        u8         reserved_3[0x20];
+};
+
+struct mlx5_ifc_query_tir_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0xc0];
+
+        struct mlx5_ifc_tirc_bits tir_context;
+};
+
+struct mlx5_ifc_query_tir_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x8];
+        u8         tirn[0x18];
+
+        u8         reserved_3[0x20];
+};
+
+struct mlx5_ifc_query_srq_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+
+        struct mlx5_ifc_srqc_bits srq_context_entry;
+
+        u8         reserved_2[0x600];
+
+        u8         pas[0][0x40];
+};
+
+struct mlx5_ifc_query_srq_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x8];
+        u8         srqn[0x18];
+
+        u8         reserved_3[0x20];
+};
+
+struct mlx5_ifc_query_sq_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0xc0];
+
+        struct mlx5_ifc_sqc_bits sq_context;
+};
+
+struct mlx5_ifc_query_sq_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x8];
+        u8         sqn[0x18];
+
+        u8         reserved_3[0x20];
+};
+
+struct mlx5_ifc_query_special_contexts_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x20];
+
+        u8         resd_lkey[0x20];
+};
+
+struct mlx5_ifc_query_special_contexts_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x40];
+};
+
+struct mlx5_ifc_query_rqt_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0xc0];
+
+        struct mlx5_ifc_rqtc_bits rqt_context;
+};
+
+struct mlx5_ifc_query_rqt_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x8];
+        u8         rqtn[0x18];
+
+        u8         reserved_3[0x20];
+};
+
+struct mlx5_ifc_query_rq_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0xc0];
+
+        struct mlx5_ifc_rqc_bits rq_context;
+};
+
+struct mlx5_ifc_query_rq_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x8];
+        u8         rqn[0x18];
+
+        u8         reserved_3[0x20];
+};
+
+struct mlx5_ifc_query_roce_address_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+
+        struct mlx5_ifc_roce_addr_layout_bits roce_address;
+};
+
+struct mlx5_ifc_query_roce_address_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         roce_address_index[0x10];
+        u8         reserved_2[0x10];
+
+        u8         reserved_3[0x20];
+};
+
+struct mlx5_ifc_query_rmp_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0xc0];
+
+        struct mlx5_ifc_rmpc_bits rmp_context;
+};
+
+struct mlx5_ifc_query_rmp_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x8];
+        u8         rmpn[0x18];
+
+        u8         reserved_3[0x20];
+};
+
+struct mlx5_ifc_query_qp_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+
+        u8         opt_param_mask[0x20];
+
+        u8         reserved_2[0x20];
+
+        struct mlx5_ifc_qpc_bits qpc;
+
+        u8         reserved_3[0x80];
+
+        u8         pas[0][0x40];
+};
+
+struct mlx5_ifc_query_qp_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x8];
+        u8         qpn[0x18];
+
+        u8         reserved_3[0x20];
+};
+
+struct mlx5_ifc_query_q_counter_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+
+        u8         rx_write_requests[0x20];
+
+        u8         reserved_2[0x20];
+
+        u8         rx_read_requests[0x20];
+
+        u8         reserved_3[0x20];
+
+        u8         rx_atomic_requests[0x20];
+
+        u8         reserved_4[0x20];
+
+        u8         rx_dct_connect[0x20];
+
+        u8         reserved_5[0x20];
+
+        u8         out_of_buffer[0x20];
+
+        u8         reserved_6[0x20];
+
+        u8         out_of_sequence[0x20];
+
+        u8         reserved_7[0x620];
+};
+
+struct mlx5_ifc_query_q_counter_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x80];
+
+        u8         clear[0x1];
+        u8         reserved_3[0x1f];
+
+        u8         reserved_4[0x18];
+        u8         counter_set_id[0x8];
+};
+
+struct mlx5_ifc_query_pages_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x10];
+        u8         function_id[0x10];
+
+        u8         num_pages[0x20];
+};
+
+enum {
+        MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
+        MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
+        MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
+};
+
+struct mlx5_ifc_query_pages_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x10];
+        u8         function_id[0x10];
+
+        u8         reserved_3[0x20];
+};
+
+struct mlx5_ifc_query_nic_vport_context_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+
+        struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
+};
+
+struct mlx5_ifc_query_nic_vport_context_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         other_vport[0x1];
+        u8         reserved_2[0xf];
+        u8         vport_number[0x10];
+
+        u8         reserved_3[0x5];
+        u8         allowed_list_type[0x3];
+        u8         reserved_4[0x18];
+};
+
+struct mlx5_ifc_query_mkey_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+
+        struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
+
+        u8         reserved_2[0x600];
+
+        u8         bsf0_klm0_pas_mtt0_1[16][0x8];
+
+        u8         bsf1_klm1_pas_mtt2_3[16][0x8];
+};
+
+struct mlx5_ifc_query_mkey_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x8];
+        u8         mkey_index[0x18];
+
+        u8         pg_access[0x1];
+        u8         reserved_3[0x1f];
+};
+
+struct mlx5_ifc_query_mad_demux_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+
+        u8         mad_dumux_parameters_block[0x20];
+};
+
+struct mlx5_ifc_query_mad_demux_in_bits {
         u8         opcode[0x10];
         u8         reserved_0[0x10];
 
@@ -326,6 +3420,146 @@ struct mlx5_ifc_query_hca_cap_in_bits {
         u8         reserved_2[0x40];
 };
 
+struct mlx5_ifc_query_l2_table_entry_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0xa0];
+
+        u8         reserved_2[0x13];
+        u8         vlan_valid[0x1];
+        u8         vlan[0xc];
+
+        struct mlx5_ifc_mac_address_layout_bits mac_address;
+
+        u8         reserved_3[0xc0];
+};
+
+struct mlx5_ifc_query_l2_table_entry_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x60];
+
+        u8         reserved_3[0x8];
+        u8         table_index[0x18];
+
+        u8         reserved_4[0x140];
+};
+
+struct mlx5_ifc_query_issi_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x10];
+        u8         current_issi[0x10];
+
+        u8         reserved_2[0xa0];
+
+        u8         supported_issi_reserved[76][0x8];
+        u8         supported_issi_dw0[0x20];
+};
+
+struct mlx5_ifc_query_issi_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x40];
+};
+
+struct mlx5_ifc_query_hca_vport_pkey_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+
+        struct mlx5_ifc_pkey_bits pkey[0];
+};
+
+struct mlx5_ifc_query_hca_vport_pkey_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         other_vport[0x1];
+        u8         reserved_2[0xb];
+        u8         port_num[0x4];
+        u8         vport_number[0x10];
+
+        u8         reserved_3[0x10];
+        u8         pkey_index[0x10];
+};
+
+struct mlx5_ifc_query_hca_vport_gid_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x20];
+
+        u8         gids_num[0x10];
+        u8         reserved_2[0x10];
+
+        struct mlx5_ifc_array128_auto_bits gid[0];
+};
+
+struct mlx5_ifc_query_hca_vport_gid_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         other_vport[0x1];
+        u8         reserved_2[0xb];
+        u8         port_num[0x4];
+        u8         vport_number[0x10];
+
+        u8         reserved_3[0x10];
+        u8         gid_index[0x10];
+};
+
+struct mlx5_ifc_query_hca_vport_context_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+
+        struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
+};
+
+struct mlx5_ifc_query_hca_vport_context_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         other_vport[0x1];
+        u8         reserved_2[0xb];
+        u8         port_num[0x4];
+        u8         vport_number[0x10];
+
+        u8         reserved_3[0x20];
+};
+
 struct mlx5_ifc_query_hca_cap_out_bits {
         u8         status[0x8];
         u8         reserved_0[0x18];
@@ -334,16 +3568,3216 @@ struct mlx5_ifc_query_hca_cap_out_bits {
 
         u8         reserved_1[0x40];
 
-        u8         capability_struct[256][0x8];
+        union mlx5_ifc_hca_cap_union_bits capability;
 };
 
-struct mlx5_ifc_set_hca_cap_out_bits {
+struct mlx5_ifc_query_hca_cap_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x40];
+};
+
+struct mlx5_ifc_query_flow_table_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x80];
+
+        u8         reserved_2[0x8];
+        u8         level[0x8];
+        u8         reserved_3[0x8];
+        u8         log_size[0x8];
+
+        u8         reserved_4[0x120];
+};
+
+struct mlx5_ifc_query_flow_table_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x40];
+
+        u8         table_type[0x8];
+        u8         reserved_3[0x18];
+
+        u8         reserved_4[0x8];
+        u8         table_id[0x18];
+
+        u8         reserved_5[0x140];
+};
+
+struct mlx5_ifc_query_fte_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x1c0];
+
+        struct mlx5_ifc_flow_context_bits flow_context;
+};
+
+struct mlx5_ifc_query_fte_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x40];
+
+        u8         table_type[0x8];
+        u8         reserved_3[0x18];
+
+        u8         reserved_4[0x8];
+        u8         table_id[0x18];
+
+        u8         reserved_5[0x40];
+
+        u8         flow_index[0x20];
+
+        u8         reserved_6[0xe0];
+};
+
+enum {
+        MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
+        MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
+        MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
+};
+
+struct mlx5_ifc_query_flow_group_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0xa0];
+
+        u8         start_flow_index[0x20];
+
+        u8         reserved_2[0x20];
+
+        u8         end_flow_index[0x20];
+
+        u8         reserved_3[0xa0];
+
+        u8         reserved_4[0x18];
+        u8         match_criteria_enable[0x8];
+
+        struct mlx5_ifc_fte_match_param_bits match_criteria;
+
+        u8         reserved_5[0xe00];
+};
+
+struct mlx5_ifc_query_flow_group_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x40];
+
+        u8         table_type[0x8];
+        u8         reserved_3[0x18];
+
+        u8         reserved_4[0x8];
+        u8         table_id[0x18];
+
+        u8         group_id[0x20];
+
+        u8         reserved_5[0x120];
+};
+
+struct mlx5_ifc_query_eq_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+
+        struct mlx5_ifc_eqc_bits eq_context_entry;
+
+        u8         reserved_2[0x40];
+
+        u8         event_bitmask[0x40];
+
+        u8         reserved_3[0x580];
+
+        u8         pas[0][0x40];
+};
+
+struct mlx5_ifc_query_eq_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x18];
+        u8         eq_number[0x8];
+
+        u8         reserved_3[0x20];
+};
+
+struct mlx5_ifc_query_dct_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+
+        struct mlx5_ifc_dctc_bits dct_context_entry;
+
+        u8         reserved_2[0x180];
+};
+
+struct mlx5_ifc_query_dct_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x8];
+        u8         dctn[0x18];
+
+        u8         reserved_3[0x20];
+};
+
+struct mlx5_ifc_query_cq_out_bits {
         u8         status[0x8];
         u8         reserved_0[0x18];
 
         u8         syndrome[0x20];
 
         u8         reserved_1[0x40];
+
+        struct mlx5_ifc_cqc_bits cq_context;
+
+        u8         reserved_2[0x600];
+
+        u8         pas[0][0x40];
+};
+
+struct mlx5_ifc_query_cq_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x8];
+        u8         cqn[0x18];
+
+        u8         reserved_3[0x20];
+};
+
+struct mlx5_ifc_query_cong_status_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x20];
+
+        u8         enable[0x1];
+        u8         tag_enable[0x1];
+        u8         reserved_2[0x1e];
+};
+
+struct mlx5_ifc_query_cong_status_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x18];
+        u8         priority[0x4];
+        u8         cong_protocol[0x4];
+
+        u8         reserved_3[0x20];
+};
+
+struct mlx5_ifc_query_cong_statistics_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+
+        u8         cur_flows[0x20];
+
+        u8         sum_flows[0x20];
+
+        u8         cnp_ignored_high[0x20];
+
+        u8         cnp_ignored_low[0x20];
+
+        u8         cnp_handled_high[0x20];
+
+        u8         cnp_handled_low[0x20];
+
+        u8         reserved_2[0x100];
+
+        u8         time_stamp_high[0x20];
+
+        u8         time_stamp_low[0x20];
+
+        u8         accumulators_period[0x20];
+
+        u8         ecn_marked_roce_packets_high[0x20];
+
+        u8         ecn_marked_roce_packets_low[0x20];
+
+        u8         cnps_sent_high[0x20];
+
+        u8         cnps_sent_low[0x20];
+
+        u8         reserved_3[0x560];
+};
+
+struct mlx5_ifc_query_cong_statistics_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         clear[0x1];
+        u8         reserved_2[0x1f];
+
+        u8         reserved_3[0x20];
+};
+
+struct mlx5_ifc_query_cong_params_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+
+        union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
+};
+
+struct mlx5_ifc_query_cong_params_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x1c];
+        u8         cong_protocol[0x4];
+
+        u8         reserved_3[0x20];
+};
+
+struct mlx5_ifc_query_adapter_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+
+        struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
+};
+
+struct mlx5_ifc_query_adapter_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x40];
+};
+
+struct mlx5_ifc_qp_2rst_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+};
+
+struct mlx5_ifc_qp_2rst_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x8];
+        u8         qpn[0x18];
+
+        u8         reserved_3[0x20];
+};
+
+struct mlx5_ifc_qp_2err_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+};
+
+struct mlx5_ifc_qp_2err_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x8];
+        u8         qpn[0x18];
+
+        u8         reserved_3[0x20];
+};
+
+struct mlx5_ifc_page_fault_resume_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+};
+
+struct mlx5_ifc_page_fault_resume_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         error[0x1];
+        u8         reserved_2[0x4];
+        u8         rdma[0x1];
+        u8         read_write[0x1];
+        u8         req_res[0x1];
+        u8         qpn[0x18];
+
+        u8         reserved_3[0x20];
+};
+
+struct mlx5_ifc_nop_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+};
+
+struct mlx5_ifc_nop_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x40];
+};
+
+struct mlx5_ifc_modify_vport_state_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+};
+
+struct mlx5_ifc_modify_vport_state_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         other_vport[0x1];
+        u8         reserved_2[0xf];
+        u8         vport_number[0x10];
+
+        u8         reserved_3[0x18];
+        u8         admin_state[0x4];
+        u8         reserved_4[0x4];
+};
+
+struct mlx5_ifc_modify_tis_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+};
+
+struct mlx5_ifc_modify_tis_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x8];
+        u8         tisn[0x18];
+
+        u8         reserved_3[0x20];
+
+        u8         modify_bitmask[0x40];
+
+        u8         reserved_4[0x40];
+
+        struct mlx5_ifc_tisc_bits ctx;
+};
+
+struct mlx5_ifc_modify_tir_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+};
+
+struct mlx5_ifc_modify_tir_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x8];
+        u8         tirn[0x18];
+
+        u8         reserved_3[0x20];
+
+        u8         modify_bitmask[0x40];
+
+        u8         reserved_4[0x40];
+
+        struct mlx5_ifc_tirc_bits ctx;
+};
+
+struct mlx5_ifc_modify_sq_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+};
+
+struct mlx5_ifc_modify_sq_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         sq_state[0x4];
+        u8         reserved_2[0x4];
+        u8         sqn[0x18];
+
+        u8         reserved_3[0x20];
+
+        u8         modify_bitmask[0x40];
+
+        u8         reserved_4[0x40];
+
+        struct mlx5_ifc_sqc_bits ctx;
+};
+
+struct mlx5_ifc_modify_rqt_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+};
+
+struct mlx5_ifc_modify_rqt_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x8];
+        u8         rqtn[0x18];
+
+        u8         reserved_3[0x20];
+
+        u8         modify_bitmask[0x40];
+
+        u8         reserved_4[0x40];
+
+        struct mlx5_ifc_rqtc_bits ctx;
+};
+
+struct mlx5_ifc_modify_rq_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+};
+
+struct mlx5_ifc_modify_rq_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         rq_state[0x4];
+        u8         reserved_2[0x4];
+        u8         rqn[0x18];
+
+        u8         reserved_3[0x20];
+
+        u8         modify_bitmask[0x40];
+
+        u8         reserved_4[0x40];
+
+        struct mlx5_ifc_rqc_bits ctx;
+};
+
+struct mlx5_ifc_modify_rmp_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+};
+
+struct mlx5_ifc_rmp_bitmask_bits {
+        u8         reserved[0x20];
+
+        u8         reserved1[0x1f];
+        u8         lwm[0x1];
+};
+
+struct mlx5_ifc_modify_rmp_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         rmp_state[0x4];
+        u8         reserved_2[0x4];
+        u8         rmpn[0x18];
+
+        u8         reserved_3[0x20];
+
+        struct mlx5_ifc_rmp_bitmask_bits bitmask;
+
+        u8         reserved_4[0x40];
+
+        struct mlx5_ifc_rmpc_bits ctx;
+};
+
+struct mlx5_ifc_modify_nic_vport_context_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+};
+
+struct mlx5_ifc_modify_nic_vport_field_select_bits {
+        u8         reserved_0[0x1c];
+        u8         permanent_address[0x1];
+        u8         addresses_list[0x1];
+        u8         roce_en[0x1];
+        u8         reserved_1[0x1];
+};
+
+struct mlx5_ifc_modify_nic_vport_context_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         other_vport[0x1];
+        u8         reserved_2[0xf];
+        u8         vport_number[0x10];
+
+        struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
+
+        u8         reserved_3[0x780];
+
+        struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
+};
+
+struct mlx5_ifc_modify_hca_vport_context_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+};
+
+struct mlx5_ifc_modify_hca_vport_context_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         other_vport[0x1];
+        u8         reserved_2[0xb];
+        u8         port_num[0x4];
+        u8         vport_number[0x10];
+
+        u8         reserved_3[0x20];
+
+        struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
+};
+
+struct mlx5_ifc_modify_cq_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+};
+
+enum {
+        MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
+        MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
+};
+
+struct mlx5_ifc_modify_cq_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x8];
+        u8         cqn[0x18];
+
+        union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
+
+        struct mlx5_ifc_cqc_bits cq_context;
+
+        u8         reserved_3[0x600];
+
+        u8         pas[0][0x40];
+};
+
+struct mlx5_ifc_modify_cong_status_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+};
+
+struct mlx5_ifc_modify_cong_status_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x18];
+        u8         priority[0x4];
+        u8         cong_protocol[0x4];
+
+        u8         enable[0x1];
+        u8         tag_enable[0x1];
+        u8         reserved_3[0x1e];
+};
+
+struct mlx5_ifc_modify_cong_params_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+};
+
+struct mlx5_ifc_modify_cong_params_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x1c];
+        u8         cong_protocol[0x4];
+
+        union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
+
+        u8         reserved_3[0x80];
+
+        union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
+};
+
+struct mlx5_ifc_manage_pages_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         output_num_entries[0x20];
+
+        u8         reserved_1[0x20];
+
+        u8         pas[0][0x40];
+};
+
+enum {
+        MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
+        MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
+        MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
+};
+
+struct mlx5_ifc_manage_pages_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x10];
+        u8         function_id[0x10];
+
+        u8         input_num_entries[0x20];
+
+        u8         pas[0][0x40];
+};
+
+struct mlx5_ifc_mad_ifc_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+
+        u8         response_mad_packet[256][0x8];
+};
+
+struct mlx5_ifc_mad_ifc_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         remote_lid[0x10];
+        u8         reserved_2[0x8];
+        u8         port[0x8];
+
+        u8         reserved_3[0x20];
+
+        u8         mad[256][0x8];
+};
+
+struct mlx5_ifc_init_hca_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+};
+
+struct mlx5_ifc_init_hca_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x40];
+};
+
+struct mlx5_ifc_init2rtr_qp_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+};
+
+struct mlx5_ifc_init2rtr_qp_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x8];
+        u8         qpn[0x18];
+
+        u8         reserved_3[0x20];
+
+        u8         opt_param_mask[0x20];
+
+        u8         reserved_4[0x20];
+
+        struct mlx5_ifc_qpc_bits qpc;
+
+        u8         reserved_5[0x80];
+};
+
+struct mlx5_ifc_init2init_qp_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+};
+
+struct mlx5_ifc_init2init_qp_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x8];
+        u8         qpn[0x18];
+
+        u8         reserved_3[0x20];
+
+        u8         opt_param_mask[0x20];
+
+        u8         reserved_4[0x20];
+
+        struct mlx5_ifc_qpc_bits qpc;
+
+        u8         reserved_5[0x80];
+};
+
+struct mlx5_ifc_get_dropped_packet_log_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+
+        u8         packet_headers_log[128][0x8];
+
+        u8         packet_syndrome[64][0x8];
+};
+
+struct mlx5_ifc_get_dropped_packet_log_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x40];
+};
+
+struct mlx5_ifc_gen_eqe_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x18];
+        u8         eq_number[0x8];
+
+        u8         reserved_3[0x20];
+
+        u8         eqe[64][0x8];
+};
+
+struct mlx5_ifc_gen_eq_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+};
+
+struct mlx5_ifc_enable_hca_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x20];
+};
+
+struct mlx5_ifc_enable_hca_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x10];
+        u8         function_id[0x10];
+
+        u8         reserved_3[0x20];
+};
+
+struct mlx5_ifc_drain_dct_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+};
+
+struct mlx5_ifc_drain_dct_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x8];
+        u8         dctn[0x18];
+
+        u8         reserved_3[0x20];
+};
+
+struct mlx5_ifc_disable_hca_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x20];
+};
+
+struct mlx5_ifc_disable_hca_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x10];
+        u8         function_id[0x10];
+
+        u8         reserved_3[0x20];
+};
+
+struct mlx5_ifc_detach_from_mcg_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+};
+
+struct mlx5_ifc_detach_from_mcg_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x8];
+        u8         qpn[0x18];
+
+        u8         reserved_3[0x20];
+
+        u8         multicast_gid[16][0x8];
+};
+
+struct mlx5_ifc_destroy_xrc_srq_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+};
+
+struct mlx5_ifc_destroy_xrc_srq_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x8];
+        u8         xrc_srqn[0x18];
+
+        u8         reserved_3[0x20];
+};
+
+struct mlx5_ifc_destroy_tis_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+};
+
+struct mlx5_ifc_destroy_tis_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x8];
+        u8         tisn[0x18];
+
+        u8         reserved_3[0x20];
+};
+
+struct mlx5_ifc_destroy_tir_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+};
+
+struct mlx5_ifc_destroy_tir_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x8];
+        u8         tirn[0x18];
+
+        u8         reserved_3[0x20];
+};
+
+struct mlx5_ifc_destroy_srq_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+};
+
+struct mlx5_ifc_destroy_srq_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x8];
+        u8         srqn[0x18];
+
+        u8         reserved_3[0x20];
+};
+
+struct mlx5_ifc_destroy_sq_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+};
+
+struct mlx5_ifc_destroy_sq_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x8];
+        u8         sqn[0x18];
+
+        u8         reserved_3[0x20];
+};
+
+struct mlx5_ifc_destroy_rqt_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+};
+
+struct mlx5_ifc_destroy_rqt_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x8];
+        u8         rqtn[0x18];
+
+        u8         reserved_3[0x20];
+};
+
+struct mlx5_ifc_destroy_rq_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+};
+
+struct mlx5_ifc_destroy_rq_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x8];
+        u8         rqn[0x18];
+
+        u8         reserved_3[0x20];
+};
+
+struct mlx5_ifc_destroy_rmp_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+};
+
+struct mlx5_ifc_destroy_rmp_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x8];
+        u8         rmpn[0x18];
+
+        u8         reserved_3[0x20];
+};
+
+struct mlx5_ifc_destroy_qp_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+};
+
+struct mlx5_ifc_destroy_qp_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x8];
+        u8         qpn[0x18];
+
+        u8         reserved_3[0x20];
+};
+
+struct mlx5_ifc_destroy_psv_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+};
+
+struct mlx5_ifc_destroy_psv_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x8];
+        u8         psvn[0x18];
+
+        u8         reserved_3[0x20];
+};
+
+struct mlx5_ifc_destroy_mkey_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+};
+
+struct mlx5_ifc_destroy_mkey_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x8];
+        u8         mkey_index[0x18];
+
+        u8         reserved_3[0x20];
+};
+
+struct mlx5_ifc_destroy_flow_table_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+};
+
+struct mlx5_ifc_destroy_flow_table_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x40];
+
+        u8         table_type[0x8];
+        u8         reserved_3[0x18];
+
+        u8         reserved_4[0x8];
+        u8         table_id[0x18];
+
+        u8         reserved_5[0x140];
+};
+
+struct mlx5_ifc_destroy_flow_group_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+};
+
+struct mlx5_ifc_destroy_flow_group_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x40];
+
+        u8         table_type[0x8];
+        u8         reserved_3[0x18];
+
+        u8         reserved_4[0x8];
+        u8         table_id[0x18];
+
+        u8         group_id[0x20];
+
+        u8         reserved_5[0x120];
+};
+
+struct mlx5_ifc_destroy_eq_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+};
+
+struct mlx5_ifc_destroy_eq_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x18];
+        u8         eq_number[0x8];
+
+        u8         reserved_3[0x20];
+};
+
+struct mlx5_ifc_destroy_dct_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+};
+
+struct mlx5_ifc_destroy_dct_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x8];
+        u8         dctn[0x18];
+
+        u8         reserved_3[0x20];
+};
+
+struct mlx5_ifc_destroy_cq_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+};
+
+struct mlx5_ifc_destroy_cq_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x8];
+        u8         cqn[0x18];
+
+        u8         reserved_3[0x20];
+};
+
+struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+};
+
+struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x20];
+
+        u8         reserved_3[0x10];
+        u8         vxlan_udp_port[0x10];
+};
+
+struct mlx5_ifc_delete_l2_table_entry_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+};
+
+struct mlx5_ifc_delete_l2_table_entry_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x60];
+
+        u8         reserved_3[0x8];
+        u8         table_index[0x18];
+
+        u8         reserved_4[0x140];
+};
+
+struct mlx5_ifc_delete_fte_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+};
+
+struct mlx5_ifc_delete_fte_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x40];
+
+        u8         table_type[0x8];
+        u8         reserved_3[0x18];
+
+        u8         reserved_4[0x8];
+        u8         table_id[0x18];
+
+        u8         reserved_5[0x40];
+
+        u8         flow_index[0x20];
+
+        u8         reserved_6[0xe0];
+};
+
+struct mlx5_ifc_dealloc_xrcd_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+};
+
+struct mlx5_ifc_dealloc_xrcd_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x8];
+        u8         xrcd[0x18];
+
+        u8         reserved_3[0x20];
+};
+
+struct mlx5_ifc_dealloc_uar_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+};
+
+struct mlx5_ifc_dealloc_uar_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x8];
+        u8         uar[0x18];
+
+        u8         reserved_3[0x20];
+};
+
+struct mlx5_ifc_dealloc_transport_domain_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+};
+
+struct mlx5_ifc_dealloc_transport_domain_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x8];
+        u8         transport_domain[0x18];
+
+        u8         reserved_3[0x20];
+};
+
+struct mlx5_ifc_dealloc_q_counter_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+};
+
+struct mlx5_ifc_dealloc_q_counter_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x18];
+        u8         counter_set_id[0x8];
+
+        u8         reserved_3[0x20];
+};
+
+struct mlx5_ifc_dealloc_pd_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+};
+
+struct mlx5_ifc_dealloc_pd_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x8];
+        u8         pd[0x18];
+
+        u8         reserved_3[0x20];
+};
+
+struct mlx5_ifc_create_xrc_srq_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x8];
+        u8         xrc_srqn[0x18];
+
+        u8         reserved_2[0x20];
+};
+
+struct mlx5_ifc_create_xrc_srq_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x40];
+
+        struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
+
+        u8         reserved_3[0x600];
+
+        u8         pas[0][0x40];
+};
+
+struct mlx5_ifc_create_tis_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x8];
+        u8         tisn[0x18];
+
+        u8         reserved_2[0x20];
+};
+
+struct mlx5_ifc_create_tis_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0xc0];
+
+        struct mlx5_ifc_tisc_bits ctx;
+};
+
+struct mlx5_ifc_create_tir_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x8];
+        u8         tirn[0x18];
+
+        u8         reserved_2[0x20];
+};
+
+struct mlx5_ifc_create_tir_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0xc0];
+
+        struct mlx5_ifc_tirc_bits ctx;
+};
+
+struct mlx5_ifc_create_srq_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x8];
+        u8         srqn[0x18];
+
+        u8         reserved_2[0x20];
+};
+
+struct mlx5_ifc_create_srq_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x40];
+
+        struct mlx5_ifc_srqc_bits srq_context_entry;
+
+        u8         reserved_3[0x600];
+
+        u8         pas[0][0x40];
+};
+
+struct mlx5_ifc_create_sq_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x8];
+        u8         sqn[0x18];
+
+        u8         reserved_2[0x20];
+};
+
+struct mlx5_ifc_create_sq_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0xc0];
+
+        struct mlx5_ifc_sqc_bits ctx;
+};
+
+struct mlx5_ifc_create_rqt_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x8];
+        u8         rqtn[0x18];
+
+        u8         reserved_2[0x20];
+};
+
+struct mlx5_ifc_create_rqt_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0xc0];
+
+        struct mlx5_ifc_rqtc_bits rqt_context;
+};
+
+struct mlx5_ifc_create_rq_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x8];
+        u8         rqn[0x18];
+
+        u8         reserved_2[0x20];
+};
+
+struct mlx5_ifc_create_rq_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0xc0];
+
+        struct mlx5_ifc_rqc_bits ctx;
+};
+
+struct mlx5_ifc_create_rmp_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x8];
+        u8         rmpn[0x18];
+
+        u8         reserved_2[0x20];
+};
+
+struct mlx5_ifc_create_rmp_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0xc0];
+
+        struct mlx5_ifc_rmpc_bits ctx;
+};
+
+struct mlx5_ifc_create_qp_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x8];
+        u8         qpn[0x18];
+
+        u8         reserved_2[0x20];
+};
+
+struct mlx5_ifc_create_qp_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x40];
+
+        u8         opt_param_mask[0x20];
+
+        u8         reserved_3[0x20];
+
+        struct mlx5_ifc_qpc_bits qpc;
+
+        u8         reserved_4[0x80];
+
+        u8         pas[0][0x40];
+};
+
+struct mlx5_ifc_create_psv_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+
+        u8         reserved_2[0x8];
+        u8         psv0_index[0x18];
+
+        u8         reserved_3[0x8];
+        u8         psv1_index[0x18];
+
+        u8         reserved_4[0x8];
+        u8         psv2_index[0x18];
+
+        u8         reserved_5[0x8];
+        u8         psv3_index[0x18];
+};
+
+struct mlx5_ifc_create_psv_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         num_psv[0x4];
+        u8         reserved_2[0x4];
+        u8         pd[0x18];
+
+        u8         reserved_3[0x20];
+};
+
+struct mlx5_ifc_create_mkey_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x8];
+        u8         mkey_index[0x18];
+
+        u8         reserved_2[0x20];
+};
+
+struct mlx5_ifc_create_mkey_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x20];
+
+        u8         pg_access[0x1];
+        u8         reserved_3[0x1f];
+
+        struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
+
+        u8         reserved_4[0x80];
+
+        u8         translations_octword_actual_size[0x20];
+
+        u8         reserved_5[0x560];
+
+        u8         klm_pas_mtt[0][0x20];
+};
+
+struct mlx5_ifc_create_flow_table_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x8];
+        u8         table_id[0x18];
+
+        u8         reserved_2[0x20];
+};
+
+struct mlx5_ifc_create_flow_table_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x40];
+
+        u8         table_type[0x8];
+        u8         reserved_3[0x18];
+
+        u8         reserved_4[0x20];
+
+        u8         reserved_5[0x8];
+        u8         level[0x8];
+        u8         reserved_6[0x8];
+        u8         log_size[0x8];
+
+        u8         reserved_7[0x120];
+};
+
+struct mlx5_ifc_create_flow_group_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x8];
+        u8         group_id[0x18];
+
+        u8         reserved_2[0x20];
+};
+
+enum {
+        MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
+        MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
+        MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
+};
+
+struct mlx5_ifc_create_flow_group_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x40];
+
+        u8         table_type[0x8];
+        u8         reserved_3[0x18];
+
+        u8         reserved_4[0x8];
+        u8         table_id[0x18];
+
+        u8         reserved_5[0x20];
+
+        u8         start_flow_index[0x20];
+
+        u8         reserved_6[0x20];
+
+        u8         end_flow_index[0x20];
+
+        u8         reserved_7[0xa0];
+
+        u8         reserved_8[0x18];
+        u8         match_criteria_enable[0x8];
+
+        struct mlx5_ifc_fte_match_param_bits match_criteria;
+
+        u8         reserved_9[0xe00];
+};
+
+struct mlx5_ifc_create_eq_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x18];
+        u8         eq_number[0x8];
+
+        u8         reserved_2[0x20];
+};
+
+struct mlx5_ifc_create_eq_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x40];
+
+        struct mlx5_ifc_eqc_bits eq_context_entry;
+
+        u8         reserved_3[0x40];
+
+        u8         event_bitmask[0x40];
+
+        u8         reserved_4[0x580];
+
+        u8         pas[0][0x40];
+};
+
+struct mlx5_ifc_create_dct_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x8];
+        u8         dctn[0x18];
+
+        u8         reserved_2[0x20];
+};
+
+struct mlx5_ifc_create_dct_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x40];
+
+        struct mlx5_ifc_dctc_bits dct_context_entry;
+
+        u8         reserved_3[0x180];
+};
+
+struct mlx5_ifc_create_cq_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x8];
+        u8         cqn[0x18];
+
+        u8         reserved_2[0x20];
+};
+
+struct mlx5_ifc_create_cq_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x40];
+
+        struct mlx5_ifc_cqc_bits cq_context;
+
+        u8         reserved_3[0x600];
+
+        u8         pas[0][0x40];
+};
+
+struct mlx5_ifc_config_int_moderation_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x4];
+        u8         min_delay[0xc];
+        u8         int_vector[0x10];
+
+        u8         reserved_2[0x20];
+};
+
+enum {
+        MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
+        MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
+};
+
+struct mlx5_ifc_config_int_moderation_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x4];
+        u8         min_delay[0xc];
+        u8         int_vector[0x10];
+
+        u8         reserved_3[0x20];
+};
+
+struct mlx5_ifc_attach_to_mcg_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+};
+
+struct mlx5_ifc_attach_to_mcg_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x8];
+        u8         qpn[0x18];
+
+        u8         reserved_3[0x20];
+
+        u8         multicast_gid[16][0x8];
+};
+
+struct mlx5_ifc_arm_xrc_srq_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+};
+
+enum {
+        MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
+};
+
+struct mlx5_ifc_arm_xrc_srq_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x8];
+        u8         xrc_srqn[0x18];
+
+        u8         reserved_3[0x10];
+        u8         lwm[0x10];
+};
+
+struct mlx5_ifc_arm_rq_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+};
+
+enum {
+        MLX5_ARM_RQ_IN_OP_MOD_SRQ_  = 0x1,
+};
+
+struct mlx5_ifc_arm_rq_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x8];
+        u8         srq_number[0x18];
+
+        u8         reserved_3[0x10];
+        u8         lwm[0x10];
+};
+
+struct mlx5_ifc_arm_dct_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+};
+
+struct mlx5_ifc_arm_dct_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x8];
+        u8         dct_number[0x18];
+
+        u8         reserved_3[0x20];
+};
+
+struct mlx5_ifc_alloc_xrcd_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x8];
+        u8         xrcd[0x18];
+
+        u8         reserved_2[0x20];
+};
+
+struct mlx5_ifc_alloc_xrcd_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x40];
+};
+
+struct mlx5_ifc_alloc_uar_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x8];
+        u8         uar[0x18];
+
+        u8         reserved_2[0x20];
+};
+
+struct mlx5_ifc_alloc_uar_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x40];
+};
+
+struct mlx5_ifc_alloc_transport_domain_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x8];
+        u8         transport_domain[0x18];
+
+        u8         reserved_2[0x20];
+};
+
+struct mlx5_ifc_alloc_transport_domain_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x40];
+};
+
+struct mlx5_ifc_alloc_q_counter_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x18];
+        u8         counter_set_id[0x8];
+
+        u8         reserved_2[0x20];
+};
+
+struct mlx5_ifc_alloc_q_counter_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x40];
+};
+
+struct mlx5_ifc_alloc_pd_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x8];
+        u8         pd[0x18];
+
+        u8         reserved_2[0x20];
+};
+
+struct mlx5_ifc_alloc_pd_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x40];
+};
+
+struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+};
+
+struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x20];
+
+        u8         reserved_3[0x10];
+        u8         vxlan_udp_port[0x10];
+};
+
+struct mlx5_ifc_access_register_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         reserved_1[0x40];
+
+        u8         register_data[0][0x20];
+};
+
+enum {
+        MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
+        MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
+};
+
+struct mlx5_ifc_access_register_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         reserved_2[0x10];
+        u8         register_id[0x10];
+
+        u8         argument[0x20];
+
+        u8         register_data[0][0x20];
+};
+
+struct mlx5_ifc_sltp_reg_bits {
+        u8         status[0x4];
+        u8         version[0x4];
+        u8         local_port[0x8];
+        u8         pnat[0x2];
+        u8         reserved_0[0x2];
+        u8         lane[0x4];
+        u8         reserved_1[0x8];
+
+        u8         reserved_2[0x20];
+
+        u8         reserved_3[0x7];
+        u8         polarity[0x1];
+        u8         ob_tap0[0x8];
+        u8         ob_tap1[0x8];
+        u8         ob_tap2[0x8];
+
+        u8         reserved_4[0xc];
+        u8         ob_preemp_mode[0x4];
+        u8         ob_reg[0x8];
+        u8         ob_bias[0x8];
+
+        u8         reserved_5[0x20];
+};
+
+struct mlx5_ifc_slrg_reg_bits {
+        u8         status[0x4];
+        u8         version[0x4];
+        u8         local_port[0x8];
+        u8         pnat[0x2];
+        u8         reserved_0[0x2];
+        u8         lane[0x4];
+        u8         reserved_1[0x8];
+
+        u8         time_to_link_up[0x10];
+        u8         reserved_2[0xc];
+        u8         grade_lane_speed[0x4];
+
+        u8         grade_version[0x8];
+        u8         grade[0x18];
+
+        u8         reserved_3[0x4];
+        u8         height_grade_type[0x4];
+        u8         height_grade[0x18];
+
+        u8         height_dz[0x10];
+        u8         height_dv[0x10];
+
+        u8         reserved_4[0x10];
+        u8         height_sigma[0x10];
+
+        u8         reserved_5[0x20];
+
+        u8         reserved_6[0x4];
+        u8         phase_grade_type[0x4];
+        u8         phase_grade[0x18];
+
+        u8         reserved_7[0x8];
+        u8         phase_eo_pos[0x8];
+        u8         reserved_8[0x8];
+        u8         phase_eo_neg[0x8];
+
+        u8         ffe_set_tested[0x10];
+        u8         test_errors_per_lane[0x10];
+};
+
+struct mlx5_ifc_pvlc_reg_bits {
+        u8         reserved_0[0x8];
+        u8         local_port[0x8];
+        u8         reserved_1[0x10];
+
+        u8         reserved_2[0x1c];
+        u8         vl_hw_cap[0x4];
+
+        u8         reserved_3[0x1c];
+        u8         vl_admin[0x4];
+
+        u8         reserved_4[0x1c];
+        u8         vl_operational[0x4];
+};
+
+struct mlx5_ifc_pude_reg_bits {
+        u8         swid[0x8];
+        u8         local_port[0x8];
+        u8         reserved_0[0x4];
+        u8         admin_status[0x4];
+        u8         reserved_1[0x4];
+        u8         oper_status[0x4];
+
+        u8         reserved_2[0x60];
+};
+
+struct mlx5_ifc_ptys_reg_bits {
+        u8         reserved_0[0x8];
+        u8         local_port[0x8];
+        u8         reserved_1[0xd];
+        u8         proto_mask[0x3];
+
+        u8         reserved_2[0x40];
+
+        u8         eth_proto_capability[0x20];
+
+        u8         ib_link_width_capability[0x10];
+        u8         ib_proto_capability[0x10];
+
+        u8         reserved_3[0x20];
+
+        u8         eth_proto_admin[0x20];
+
+        u8         ib_link_width_admin[0x10];
+        u8         ib_proto_admin[0x10];
+
+        u8         reserved_4[0x20];
+
+        u8         eth_proto_oper[0x20];
+
+        u8         ib_link_width_oper[0x10];
+        u8         ib_proto_oper[0x10];
+
+        u8         reserved_5[0x20];
+
+        u8         eth_proto_lp_advertise[0x20];
+
+        u8         reserved_6[0x60];
+};
+
+struct mlx5_ifc_ptas_reg_bits {
+        u8         reserved_0[0x20];
+
+        u8         algorithm_options[0x10];
+        u8         reserved_1[0x4];
+        u8         repetitions_mode[0x4];
+        u8         num_of_repetitions[0x8];
+
+        u8         grade_version[0x8];
+        u8         height_grade_type[0x4];
+        u8         phase_grade_type[0x4];
+        u8         height_grade_weight[0x8];
+        u8         phase_grade_weight[0x8];
+
+        u8         gisim_measure_bits[0x10];
+        u8         adaptive_tap_measure_bits[0x10];
+
+        u8         ber_bath_high_error_threshold[0x10];
+        u8         ber_bath_mid_error_threshold[0x10];
+
+        u8         ber_bath_low_error_threshold[0x10];
+        u8         one_ratio_high_threshold[0x10];
+
+        u8         one_ratio_high_mid_threshold[0x10];
+        u8         one_ratio_low_mid_threshold[0x10];
+
+        u8         one_ratio_low_threshold[0x10];
+        u8         ndeo_error_threshold[0x10];
+
+        u8         mixer_offset_step_size[0x10];
+        u8         reserved_2[0x8];
+        u8         mix90_phase_for_voltage_bath[0x8];
+
+        u8         mixer_offset_start[0x10];
+        u8         mixer_offset_end[0x10];
+
+        u8         reserved_3[0x15];
+        u8         ber_test_time[0xb];
+};
+
+struct mlx5_ifc_pspa_reg_bits {
+        u8         swid[0x8];
+        u8         local_port[0x8];
+        u8         sub_port[0x8];
+        u8         reserved_0[0x8];
+
+        u8         reserved_1[0x20];
+};
+
+struct mlx5_ifc_pqdr_reg_bits {
+        u8         reserved_0[0x8];
+        u8         local_port[0x8];
+        u8         reserved_1[0x5];
+        u8         prio[0x3];
+        u8         reserved_2[0x6];
+        u8         mode[0x2];
+
+        u8         reserved_3[0x20];
+
+        u8         reserved_4[0x10];
+        u8         min_threshold[0x10];
+
+        u8         reserved_5[0x10];
+        u8         max_threshold[0x10];
+
+        u8         reserved_6[0x10];
+        u8         mark_probability_denominator[0x10];
+
+        u8         reserved_7[0x60];
+};
+
+struct mlx5_ifc_ppsc_reg_bits {
+        u8         reserved_0[0x8];
+        u8         local_port[0x8];
+        u8         reserved_1[0x10];
+
+        u8         reserved_2[0x60];
+
+        u8         reserved_3[0x1c];
+        u8         wrps_admin[0x4];
+
+        u8         reserved_4[0x1c];
+        u8         wrps_status[0x4];
+
+        u8         reserved_5[0x8];
+        u8         up_threshold[0x8];
+        u8         reserved_6[0x8];
+        u8         down_threshold[0x8];
+
+        u8         reserved_7[0x20];
+
+        u8         reserved_8[0x1c];
+        u8         srps_admin[0x4];
+
+        u8         reserved_9[0x1c];
+        u8         srps_status[0x4];
+
+        u8         reserved_10[0x40];
+};
+
+struct mlx5_ifc_pplr_reg_bits {
+        u8         reserved_0[0x8];
+        u8         local_port[0x8];
+        u8         reserved_1[0x10];
+
+        u8         reserved_2[0x8];
+        u8         lb_cap[0x8];
+        u8         reserved_3[0x8];
+        u8         lb_en[0x8];
+};
+
+struct mlx5_ifc_pplm_reg_bits {
+        u8         reserved_0[0x8];
+        u8         local_port[0x8];
+        u8         reserved_1[0x10];
+
+        u8         reserved_2[0x20];
+
+        u8         port_profile_mode[0x8];
+        u8         static_port_profile[0x8];
+        u8         active_port_profile[0x8];
+        u8         reserved_3[0x8];
+
+        u8         retransmission_active[0x8];
+        u8         fec_mode_active[0x18];
+
+        u8         reserved_4[0x20];
+};
+
+struct mlx5_ifc_ppcnt_reg_bits {
+        u8         swid[0x8];
+        u8         local_port[0x8];
+        u8         pnat[0x2];
+        u8         reserved_0[0x8];
+        u8         grp[0x6];
+
+        u8         clr[0x1];
+        u8         reserved_1[0x1c];
+        u8         prio_tc[0x3];
+
+        union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
+};
+
+struct mlx5_ifc_ppad_reg_bits {
+        u8         reserved_0[0x3];
+        u8         single_mac[0x1];
+        u8         reserved_1[0x4];
+        u8         local_port[0x8];
+        u8         mac_47_32[0x10];
+
+        u8         mac_31_0[0x20];
+
+        u8         reserved_2[0x40];
+};
+
+struct mlx5_ifc_pmtu_reg_bits {
+        u8         reserved_0[0x8];
+        u8         local_port[0x8];
+        u8         reserved_1[0x10];
+
+        u8         max_mtu[0x10];
+        u8         reserved_2[0x10];
+
+        u8         admin_mtu[0x10];
+        u8         reserved_3[0x10];
+
+        u8         oper_mtu[0x10];
+        u8         reserved_4[0x10];
+};
+
+struct mlx5_ifc_pmpr_reg_bits {
+        u8         reserved_0[0x8];
+        u8         module[0x8];
+        u8         reserved_1[0x10];
+
+        u8         reserved_2[0x18];
+        u8         attenuation_5g[0x8];
+
+        u8         reserved_3[0x18];
+        u8         attenuation_7g[0x8];
+
+        u8         reserved_4[0x18];
+        u8         attenuation_12g[0x8];
+};
+
+struct mlx5_ifc_pmpe_reg_bits {
+        u8         reserved_0[0x8];
+        u8         module[0x8];
+        u8         reserved_1[0xc];
+        u8         module_status[0x4];
+
+        u8         reserved_2[0x60];
+};
+
+struct mlx5_ifc_pmpc_reg_bits {
+        u8         module_state_updated[32][0x8];
+};
+
+struct mlx5_ifc_pmlpn_reg_bits {
+        u8         reserved_0[0x4];
+        u8         mlpn_status[0x4];
+        u8         local_port[0x8];
+        u8         reserved_1[0x10];
+
+        u8         e[0x1];
+        u8         reserved_2[0x1f];
+};
+
+struct mlx5_ifc_pmlp_reg_bits {
+        u8         rxtx[0x1];
+        u8         reserved_0[0x7];
+        u8         local_port[0x8];
+        u8         reserved_1[0x8];
+        u8         width[0x8];
+
+        u8         lane0_module_mapping[0x20];
+
+        u8         lane1_module_mapping[0x20];
+
+        u8         lane2_module_mapping[0x20];
+
+        u8         lane3_module_mapping[0x20];
+
+        u8         reserved_2[0x160];
+};
+
+struct mlx5_ifc_pmaos_reg_bits {
+        u8         reserved_0[0x8];
+        u8         module[0x8];
+        u8         reserved_1[0x4];
+        u8         admin_status[0x4];
+        u8         reserved_2[0x4];
+        u8         oper_status[0x4];
+
+        u8         ase[0x1];
+        u8         ee[0x1];
+        u8         reserved_3[0x1c];
+        u8         e[0x2];
+
+        u8         reserved_4[0x40];
+};
+
+struct mlx5_ifc_plpc_reg_bits {
+        u8         reserved_0[0x4];
+        u8         profile_id[0xc];
+        u8         reserved_1[0x4];
+        u8         proto_mask[0x4];
+        u8         reserved_2[0x8];
+
+        u8         reserved_3[0x10];
+        u8         lane_speed[0x10];
+
+        u8         reserved_4[0x17];
+        u8         lpbf[0x1];
+        u8         fec_mode_policy[0x8];
+
+        u8         retransmission_capability[0x8];
+        u8         fec_mode_capability[0x18];
+
+        u8         retransmission_support_admin[0x8];
+        u8         fec_mode_support_admin[0x18];
+
+        u8         retransmission_request_admin[0x8];
+        u8         fec_mode_request_admin[0x18];
+
+        u8         reserved_5[0x80];
+};
+
+struct mlx5_ifc_plib_reg_bits {
+        u8         reserved_0[0x8];
+        u8         local_port[0x8];
+        u8         reserved_1[0x8];
+        u8         ib_port[0x8];
+
+        u8         reserved_2[0x60];
+};
+
+struct mlx5_ifc_plbf_reg_bits {
+        u8         reserved_0[0x8];
+        u8         local_port[0x8];
+        u8         reserved_1[0xd];
+        u8         lbf_mode[0x3];
+
+        u8         reserved_2[0x20];
+};
+
+struct mlx5_ifc_pipg_reg_bits {
+        u8         reserved_0[0x8];
+        u8         local_port[0x8];
+        u8         reserved_1[0x10];
+
+        u8         dic[0x1];
+        u8         reserved_2[0x19];
+        u8         ipg[0x4];
+        u8         reserved_3[0x2];
+};
+
+struct mlx5_ifc_pifr_reg_bits {
+        u8         reserved_0[0x8];
+        u8         local_port[0x8];
+        u8         reserved_1[0x10];
+
+        u8         reserved_2[0xe0];
+
+        u8         port_filter[8][0x20];
+
+        u8         port_filter_update_en[8][0x20];
+};
+
+struct mlx5_ifc_pfcc_reg_bits {
+        u8         reserved_0[0x8];
+        u8         local_port[0x8];
+        u8         reserved_1[0x10];
+
+        u8         ppan[0x4];
+        u8         reserved_2[0x4];
+        u8         prio_mask_tx[0x8];
+        u8         reserved_3[0x8];
+        u8         prio_mask_rx[0x8];
+
+        u8         pptx[0x1];
+        u8         aptx[0x1];
+        u8         reserved_4[0x6];
+        u8         pfctx[0x8];
+        u8         reserved_5[0x10];
+
+        u8         pprx[0x1];
+        u8         aprx[0x1];
+        u8         reserved_6[0x6];
+        u8         pfcrx[0x8];
+        u8         reserved_7[0x10];
+
+        u8         reserved_8[0x80];
+};
+
+struct mlx5_ifc_pelc_reg_bits {
+        u8         op[0x4];
+        u8         reserved_0[0x4];
+        u8         local_port[0x8];
+        u8         reserved_1[0x10];
+
+        u8         op_admin[0x8];
+        u8         op_capability[0x8];
+        u8         op_request[0x8];
+        u8         op_active[0x8];
+
+        u8         admin[0x40];
+
+        u8         capability[0x40];
+
+        u8         request[0x40];
+
+        u8         active[0x40];
+
+        u8         reserved_2[0x80];
+};
+
+struct mlx5_ifc_peir_reg_bits {
+        u8         reserved_0[0x8];
+        u8         local_port[0x8];
+        u8         reserved_1[0x10];
+
+        u8         reserved_2[0xc];
+        u8         error_count[0x4];
+        u8         reserved_3[0x10];
+
+        u8         reserved_4[0xc];
+        u8         lane[0x4];
+        u8         reserved_5[0x8];
+        u8         error_type[0x8];
+};
+
+struct mlx5_ifc_pcap_reg_bits {
+        u8         reserved_0[0x8];
+        u8         local_port[0x8];
+        u8         reserved_1[0x10];
+
+        u8         port_capability_mask[4][0x20];
+};
+
+struct mlx5_ifc_paos_reg_bits {
+        u8         swid[0x8];
+        u8         local_port[0x8];
+        u8         reserved_0[0x4];
+        u8         admin_status[0x4];
+        u8         reserved_1[0x4];
+        u8         oper_status[0x4];
+
+        u8         ase[0x1];
+        u8         ee[0x1];
+        u8         reserved_2[0x1c];
+        u8         e[0x2];
+
+        u8         reserved_3[0x40];
+};
+
+struct mlx5_ifc_pamp_reg_bits {
+        u8         reserved_0[0x8];
+        u8         opamp_group[0x8];
+        u8         reserved_1[0xc];
+        u8         opamp_group_type[0x4];
+
+        u8         start_index[0x10];
+        u8         reserved_2[0x4];
+        u8         num_of_indices[0xc];
+
+        u8         index_data[18][0x10];
+};
+
+struct mlx5_ifc_lane_2_module_mapping_bits {
+        u8         reserved_0[0x6];
+        u8         rx_lane[0x2];
+        u8         reserved_1[0x6];
+        u8         tx_lane[0x2];
+        u8         reserved_2[0x8];
+        u8         module[0x8];
+};
+
+struct mlx5_ifc_bufferx_reg_bits {
+        u8         reserved_0[0x6];
+        u8         lossy[0x1];
+        u8         epsb[0x1];
+        u8         reserved_1[0xc];
+        u8         size[0xc];
+
+        u8         xoff_threshold[0x10];
+        u8         xon_threshold[0x10];
+};
+
+struct mlx5_ifc_set_node_in_bits {
+        u8         node_description[64][0x8];
+};
+
+struct mlx5_ifc_register_power_settings_bits {
+        u8         reserved_0[0x18];
+        u8         power_settings_level[0x8];
+
+        u8         reserved_1[0x60];
+};
+
+struct mlx5_ifc_register_host_endianness_bits {
+        u8         he[0x1];
+        u8         reserved_0[0x1f];
+
+        u8         reserved_1[0x60];
+};
+
+struct mlx5_ifc_umr_pointer_desc_argument_bits {
+        u8         reserved_0[0x20];
+
+        u8         mkey[0x20];
+
+        u8         addressh_63_32[0x20];
+
+        u8         addressl_31_0[0x20];
+};
+
+struct mlx5_ifc_ud_adrs_vector_bits {
+        u8         dc_key[0x40];
+
+        u8         ext[0x1];
+        u8         reserved_0[0x7];
+        u8         destination_qp_dct[0x18];
+
+        u8         static_rate[0x4];
+        u8         sl_eth_prio[0x4];
+        u8         fl[0x1];
+        u8         mlid[0x7];
+        u8         rlid_udp_sport[0x10];
+
+        u8         reserved_1[0x20];
+
+        u8         rmac_47_16[0x20];
+
+        u8         rmac_15_0[0x10];
+        u8         tclass[0x8];
+        u8         hop_limit[0x8];
+
+        u8         reserved_2[0x1];
+        u8         grh[0x1];
+        u8         reserved_3[0x2];
+        u8         src_addr_index[0x8];
+        u8         flow_label[0x14];
+
+        u8         rgid_rip[16][0x8];
+};
+
+struct mlx5_ifc_pages_req_event_bits {
+        u8         reserved_0[0x10];
+        u8         function_id[0x10];
+
+        u8         num_pages[0x20];
+
+        u8         reserved_1[0xa0];
+};
+
+struct mlx5_ifc_eqe_bits {
+        u8         reserved_0[0x8];
+        u8         event_type[0x8];
+        u8         reserved_1[0x8];
+        u8         event_sub_type[0x8];
+
+        u8         reserved_2[0xe0];
+
+        union mlx5_ifc_event_auto_bits event_data;
+
+        u8         reserved_3[0x10];
+        u8         signature[0x8];
+        u8         reserved_4[0x7];
+        u8         owner[0x1];
+};
+
+enum {
+        MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
+};
+
+struct mlx5_ifc_cmd_queue_entry_bits {
+        u8         type[0x8];
+        u8         reserved_0[0x18];
+
+        u8         input_length[0x20];
+
+        u8         input_mailbox_pointer_63_32[0x20];
+
+        u8         input_mailbox_pointer_31_9[0x17];
+        u8         reserved_1[0x9];
+
+        u8         command_input_inline_data[16][0x8];
+
+        u8         command_output_inline_data[16][0x8];
+
+        u8         output_mailbox_pointer_63_32[0x20];
+
+        u8         output_mailbox_pointer_31_9[0x17];
+        u8         reserved_2[0x9];
+
+        u8         output_length[0x20];
+
+        u8         token[0x8];
+        u8         signature[0x8];
+        u8         reserved_3[0x8];
+        u8         status[0x7];
+        u8         ownership[0x1];
+};
+
+struct mlx5_ifc_cmd_out_bits {
+        u8         status[0x8];
+        u8         reserved_0[0x18];
+
+        u8         syndrome[0x20];
+
+        u8         command_output[0x20];
+};
+
+struct mlx5_ifc_cmd_in_bits {
+        u8         opcode[0x10];
+        u8         reserved_0[0x10];
+
+        u8         reserved_1[0x10];
+        u8         op_mod[0x10];
+
+        u8         command[0][0x20];
+};
+
+struct mlx5_ifc_cmd_if_box_bits {
+        u8         mailbox_data[512][0x8];
+
+        u8         reserved_0[0x180];
+
+        u8         next_pointer_63_32[0x20];
+
+        u8         next_pointer_31_10[0x16];
+        u8         reserved_1[0xa];
+
+        u8         block_number[0x20];
+
+        u8         reserved_2[0x8];
+        u8         token[0x8];
+        u8         ctrl_signature[0x8];
+        u8         signature[0x8];
+};
+
+struct mlx5_ifc_mtt_bits {
+        u8         ptag_63_32[0x20];
+
+        u8         ptag_31_8[0x18];
+        u8         reserved_0[0x6];
+        u8         wr_en[0x1];
+        u8         rd_en[0x1];
+};
+
+enum {
+        MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
+        MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
+        MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
+};
+
+enum {
+        MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
+        MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
+        MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
+};
+
+enum {
+        MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
+        MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
+        MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
+        MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
+        MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
+        MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
+        MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
+        MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
+        MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
+        MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
+        MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
+};
+
+struct mlx5_ifc_initial_seg_bits {
+        u8         fw_rev_minor[0x10];
+        u8         fw_rev_major[0x10];
+
+        u8         cmd_interface_rev[0x10];
+        u8         fw_rev_subminor[0x10];
+
+        u8         reserved_0[0x40];
+
+        u8         cmdq_phy_addr_63_32[0x20];
+
+        u8         cmdq_phy_addr_31_12[0x14];
+        u8         reserved_1[0x2];
+        u8         nic_interface[0x2];
+        u8         log_cmdq_size[0x4];
+        u8         log_cmdq_stride[0x4];
+
+        u8         command_doorbell_vector[0x20];
+
+        u8         reserved_2[0xf00];
+
+        u8         initializing[0x1];
+        u8         reserved_3[0x4];
+        u8         nic_interface_supported[0x3];
+        u8         reserved_4[0x18];
+
+        struct mlx5_ifc_health_buffer_bits health_buffer;
+
+        u8         no_dram_nic_offset[0x20];
+
+        u8         reserved_5[0x6e40];
+
+        u8         reserved_6[0x1f];
+        u8         clear_int[0x1];
+
+        u8         health_syndrome[0x8];
+        u8         health_counter[0x18];
+
+        u8         reserved_7[0x17fc0];
+};
+
+union mlx5_ifc_ports_control_registers_document_bits {
+        struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
+        struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
+        struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
+        struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
+        struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
+        struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
+        struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
+        struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
+        struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
+        struct mlx5_ifc_pamp_reg_bits pamp_reg;
+        struct mlx5_ifc_paos_reg_bits paos_reg;
+        struct mlx5_ifc_pcap_reg_bits pcap_reg;
+        struct mlx5_ifc_peir_reg_bits peir_reg;
+        struct mlx5_ifc_pelc_reg_bits pelc_reg;
+        struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
+        struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
+        struct mlx5_ifc_pifr_reg_bits pifr_reg;
+        struct mlx5_ifc_pipg_reg_bits pipg_reg;
+        struct mlx5_ifc_plbf_reg_bits plbf_reg;
+        struct mlx5_ifc_plib_reg_bits plib_reg;
+        struct mlx5_ifc_plpc_reg_bits plpc_reg;
+        struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
+        struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
+        struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
+        struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
+        struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
+        struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
+        struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
+        struct mlx5_ifc_ppad_reg_bits ppad_reg;
+        struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
+        struct mlx5_ifc_pplm_reg_bits pplm_reg;
+        struct mlx5_ifc_pplr_reg_bits pplr_reg;
+        struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
+        struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
+        struct mlx5_ifc_pspa_reg_bits pspa_reg;
+        struct mlx5_ifc_ptas_reg_bits ptas_reg;
+        struct mlx5_ifc_ptys_reg_bits ptys_reg;
+        struct mlx5_ifc_pude_reg_bits pude_reg;
+        struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
+        struct mlx5_ifc_slrg_reg_bits slrg_reg;
+        struct mlx5_ifc_sltp_reg_bits sltp_reg;
+        u8         reserved_0[0x60e0];
+};
+
+union mlx5_ifc_debug_enhancements_document_bits {
+        struct mlx5_ifc_health_buffer_bits health_buffer;
+        u8         reserved_0[0x200];
+};
+
+union mlx5_ifc_uplink_pci_interface_document_bits {
+        struct mlx5_ifc_initial_seg_bits initial_seg;
+        u8         reserved_0[0x20060];
 };
 
 #endif /* MLX5_IFC_H */
diff --git a/include/linux/mlx5/qp.h b/include/linux/mlx5/qp.h
index 310b5f7fd6ae..f079fb1a31f7 100644
--- a/include/linux/mlx5/qp.h
+++ b/include/linux/mlx5/qp.h
@@ -134,13 +134,21 @@ enum {
 
 enum {
         MLX5_WQE_CTRL_CQ_UPDATE         = 2 << 2,
+        MLX5_WQE_CTRL_CQ_UPDATE_AND_EQE = 3 << 2,
         MLX5_WQE_CTRL_SOLICITED         = 1 << 1,
 };
 
 enum {
+        MLX5_SEND_WQE_DS        = 16,
         MLX5_SEND_WQE_BB        = 64,
 };
 
+#define MLX5_SEND_WQEBB_NUM_DS  (MLX5_SEND_WQE_BB / MLX5_SEND_WQE_DS)
+
+enum {
+        MLX5_SEND_WQE_MAX_WQEBBS        = 16,
+};
+
 enum {
         MLX5_WQE_FMR_PERM_LOCAL_READ    = 1 << 27,
         MLX5_WQE_FMR_PERM_LOCAL_WRITE   = 1 << 28,
@@ -200,6 +208,23 @@ struct mlx5_wqe_ctrl_seg {
 #define MLX5_WQE_CTRL_WQE_INDEX_MASK 0x00ffff00
 #define MLX5_WQE_CTRL_WQE_INDEX_SHIFT 8
 
+enum {
+        MLX5_ETH_WQE_L3_INNER_CSUM      = 1 << 4,
+        MLX5_ETH_WQE_L4_INNER_CSUM      = 1 << 5,
+        MLX5_ETH_WQE_L3_CSUM            = 1 << 6,
+        MLX5_ETH_WQE_L4_CSUM            = 1 << 7,
+};
+
+struct mlx5_wqe_eth_seg {
+        u8              rsvd0[4];
+        u8              cs_flags;
+        u8              rsvd1;
+        __be16          mss;
+        __be32          rsvd2;
+        __be16          inline_hdr_sz;
+        u8              inline_hdr_start[2];
+};
+
 struct mlx5_wqe_xrc_seg {
         __be32                  xrc_srqn;
         u8                      rsvd[12];
diff --git a/include/linux/mlx5/vport.h b/include/linux/mlx5/vport.h
new file mode 100644
index 000000000000..967e0fd06e89
--- /dev/null
+++ b/include/linux/mlx5/vport.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the
+ * OpenIB.org BSD license below:
+ *
+ *     Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *      - Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *
+ *      - Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#ifndef __MLX5_VPORT_H__
+#define __MLX5_VPORT_H__
+
+#include <linux/mlx5/driver.h>
+
+u8 mlx5_query_vport_state(struct mlx5_core_dev *mdev, u8 opmod);
+void mlx5_query_nic_vport_mac_address(struct mlx5_core_dev *mdev, u8 *addr);
+int mlx5_query_hca_vport_gid(struct mlx5_core_dev *dev, u8 other_vport,
+                             u8 port_num, u16  vf_num, u16 gid_index,
+                             union ib_gid *gid);
+int mlx5_query_hca_vport_pkey(struct mlx5_core_dev *dev, u8 other_vport,
+                              u8 port_num, u16 vf_num, u16 pkey_index,
+                              u16 *pkey);
+int mlx5_query_hca_vport_context(struct mlx5_core_dev *dev,
+                                 u8 other_vport, u8 port_num,
+                                 u16 vf_num,
+                                 struct mlx5_hca_vport_context *rep);
+int mlx5_query_hca_vport_system_image_guid(struct mlx5_core_dev *dev,
+                                           u64 *sys_image_guid);
+int mlx5_query_hca_vport_node_guid(struct mlx5_core_dev *dev,
+                                   u64 *node_guid);
+
+#endif /* __MLX5_VPORT_H__ */
diff --git a/include/linux/mm_types.h b/include/linux/mm_types.h
index 8d37e26a1007..0038ac7466fd 100644
--- a/include/linux/mm_types.h
+++ b/include/linux/mm_types.h
@@ -226,6 +226,24 @@ struct page_frag {
 #endif
 };
 
+#define PAGE_FRAG_CACHE_MAX_SIZE        __ALIGN_MASK(32768, ~PAGE_MASK)
+#define PAGE_FRAG_CACHE_MAX_ORDER       get_order(PAGE_FRAG_CACHE_MAX_SIZE)
+
+struct page_frag_cache {
+        void * va;
+#if (PAGE_SIZE < PAGE_FRAG_CACHE_MAX_SIZE)
+        __u16 offset;
+        __u16 size;
+#else
+        __u32 offset;
+#endif
+        /* we maintain a pagecount bias, so that we dont dirty cache line
+         * containing page->_count every time we allocate a fragment.
+         */
+        unsigned int            pagecnt_bias;
+        bool pfmemalloc;
+};
+
 typedef unsigned long __nocast vm_flags_t;
 
 /*
diff --git a/include/linux/net.h b/include/linux/net.h
index 738ea48be889..04aa06852771 100644
--- a/include/linux/net.h
+++ b/include/linux/net.h
@@ -38,7 +38,6 @@ struct net;
 #define SOCK_NOSPACE            2
 #define SOCK_PASSCRED           3
 #define SOCK_PASSSEC            4
-#define SOCK_EXTERNALLY_ALLOCATED 5
 
 #ifndef ARCH_HAS_SOCKET_TYPES
 /**
@@ -208,7 +207,7 @@ void sock_unregister(int family);
 int __sock_create(struct net *net, int family, int type, int proto,
                   struct socket **res, int kern);
 int sock_create(int family, int type, int proto, struct socket **res);
-int sock_create_kern(int family, int type, int proto, struct socket **res);
+int sock_create_kern(struct net *net, int family, int type, int proto, struct socket **res);
 int sock_create_lite(int family, int type, int proto, struct socket **res);
 void sock_release(struct socket *sock);
 int sock_sendmsg(struct socket *sock, struct msghdr *msg);
diff --git a/include/linux/netdev_features.h b/include/linux/netdev_features.h
index 7d59dc6ab789..9672781c593d 100644
--- a/include/linux/netdev_features.h
+++ b/include/linux/netdev_features.h
@@ -66,7 +66,6 @@ enum {
         NETIF_F_HW_VLAN_STAG_FILTER_BIT,/* Receive filtering on VLAN STAGs */
         NETIF_F_HW_L2FW_DOFFLOAD_BIT,   /* Allow L2 Forwarding in Hardware */
         NETIF_F_BUSY_POLL_BIT,          /* Busy poll */
-        NETIF_F_HW_SWITCH_OFFLOAD_BIT,  /* HW switch offload */
 
         /*
          * Add your fresh new feature above and remember to update
@@ -125,7 +124,6 @@ enum {
 #define NETIF_F_HW_VLAN_STAG_TX __NETIF_F(HW_VLAN_STAG_TX)
 #define NETIF_F_HW_L2FW_DOFFLOAD        __NETIF_F(HW_L2FW_DOFFLOAD)
 #define NETIF_F_BUSY_POLL       __NETIF_F(BUSY_POLL)
-#define NETIF_F_HW_SWITCH_OFFLOAD       __NETIF_F(HW_SWITCH_OFFLOAD)
 
 /* Features valid for ethtool to change */
 /* = all defined minus driver/device-class-related */
@@ -161,8 +159,7 @@ enum {
  */
 #define NETIF_F_ONE_FOR_ALL     (NETIF_F_GSO_SOFTWARE | NETIF_F_GSO_ROBUST | \
                                  NETIF_F_SG | NETIF_F_HIGHDMA |         \
-                                 NETIF_F_FRAGLIST | NETIF_F_VLAN_CHALLENGED | \
-                                 NETIF_F_HW_SWITCH_OFFLOAD)
+                                 NETIF_F_FRAGLIST | NETIF_F_VLAN_CHALLENGED)
 
 /*
  * If one device doesn't support one of these features, then disable it
diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h
index 05b9a694e213..e20979dfd6a9 100644
--- a/include/linux/netdevice.h
+++ b/include/linux/netdevice.h
@@ -1100,6 +1100,10 @@ struct net_device_ops {
                                                      struct ifla_vf_info *ivf);
         int                     (*ndo_set_vf_link_state)(struct net_device *dev,
                                                          int vf, int link_state);
+        int                     (*ndo_get_vf_stats)(struct net_device *dev,
+                                                    int vf,
+                                                    struct ifla_vf_stats
+                                                    *vf_stats);
         int                     (*ndo_set_vf_port)(struct net_device *dev,
                                                    int vf,
                                                    struct nlattr *port[]);
@@ -1564,7 +1568,7 @@ struct net_device {
         const struct net_device_ops *netdev_ops;
         const struct ethtool_ops *ethtool_ops;
 #ifdef CONFIG_NET_SWITCHDEV
-        const struct swdev_ops *swdev_ops;
+        const struct switchdev_ops *switchdev_ops;
 #endif
 
         const struct header_ops *header_ops;
@@ -1652,7 +1656,14 @@ struct net_device {
         rx_handler_func_t __rcu *rx_handler;
         void __rcu              *rx_handler_data;
 
+#ifdef CONFIG_NET_CLS_ACT
+        struct tcf_proto __rcu  *ingress_cl_list;
+#endif
         struct netdev_queue __rcu *ingress_queue;
+#ifdef CONFIG_NETFILTER_INGRESS
+        struct list_head        nf_hooks_ingress;
+#endif
+
         unsigned char           broadcast[MAX_ADDR_LEN];
 #ifdef CONFIG_RFS_ACCEL
         struct cpu_rmap         *rx_cpu_rmap;
@@ -1990,6 +2001,7 @@ struct offload_callbacks {
 
 struct packet_offload {
         __be16                   type;  /* This is really htons(ether_type). */
+        u16                      priority;
         struct offload_callbacks callbacks;
         struct list_head         list;
 };
@@ -2552,10 +2564,6 @@ static inline void netif_tx_wake_all_queues(struct net_device *dev)
 
 static inline void netif_tx_stop_queue(struct netdev_queue *dev_queue)
 {
-        if (WARN_ON(!dev_queue)) {
-                pr_info("netif_stop_queue() cannot be called before register_netdev()\n");
-                return;
-        }
         set_bit(__QUEUE_STATE_DRV_XOFF, &dev_queue->state);
 }
 
@@ -2571,15 +2579,7 @@ static inline void netif_stop_queue(struct net_device *dev)
         netif_tx_stop_queue(netdev_get_tx_queue(dev, 0));
 }
 
-static inline void netif_tx_stop_all_queues(struct net_device *dev)
-{
-        unsigned int i;
-
-        for (i = 0; i < dev->num_tx_queues; i++) {
-                struct netdev_queue *txq = netdev_get_tx_queue(dev, i);
-                netif_tx_stop_queue(txq);
-        }
-}
+void netif_tx_stop_all_queues(struct net_device *dev);
 
 static inline bool netif_tx_queue_stopped(const struct netdev_queue *dev_queue)
 {
@@ -2840,6 +2840,9 @@ static inline int netif_set_xps_queue(struct net_device *dev,
 }
 #endif
 
+u16 __skb_tx_hash(const struct net_device *dev, struct sk_buff *skb,
+                  unsigned int num_tx_queues);
+
 /*
  * Returns a Tx hash for the given packet when dev->real_num_tx_queues is used
  * as a distribution range limit for the returned value.
diff --git a/include/linux/netfilter.h b/include/linux/netfilter.h
index 63560d0a8dfe..00050dfd9f23 100644
--- a/include/linux/netfilter.h
+++ b/include/linux/netfilter.h
@@ -10,7 +10,8 @@
 #include <linux/wait.h>
 #include <linux/list.h>
 #include <linux/static_key.h>
-#include <uapi/linux/netfilter.h>
+#include <linux/netfilter_defs.h>
+
 #ifdef CONFIG_NETFILTER
 static inline int NF_DROP_GETERR(int verdict)
 {
@@ -38,9 +39,6 @@ static inline void nf_inet_addr_mask(const union nf_inet_addr *a1,
 
 int netfilter_init(void);
 
-/* Largest hook number + 1 */
-#define NF_MAX_HOOKS 8
-
 struct sk_buff;
 
 struct nf_hook_ops;
@@ -54,10 +52,12 @@ struct nf_hook_state {
         struct net_device *in;
         struct net_device *out;
         struct sock *sk;
+        struct list_head *hook_list;
         int (*okfn)(struct sock *, struct sk_buff *);
 };
 
 static inline void nf_hook_state_init(struct nf_hook_state *p,
+                                      struct list_head *hook_list,
                                       unsigned int hook,
                                       int thresh, u_int8_t pf,
                                       struct net_device *indev,
@@ -71,6 +71,7 @@ static inline void nf_hook_state_init(struct nf_hook_state *p,
         p->in = indev;
         p->out = outdev;
         p->sk = sk;
+        p->hook_list = hook_list;
         p->okfn = okfn;
 }
 
@@ -79,16 +80,17 @@ typedef unsigned int nf_hookfn(const struct nf_hook_ops *ops,
                                const struct nf_hook_state *state);
 
 struct nf_hook_ops {
-        struct list_head list;
+        struct list_head        list;
 
         /* User fills in from here down. */
-        nf_hookfn       *hook;
-        struct module   *owner;
-        void            *priv;
-        u_int8_t        pf;
-        unsigned int    hooknum;
+        nf_hookfn               *hook;
+        struct net_device       *dev;
+        struct module           *owner;
+        void                    *priv;
+        u_int8_t                pf;
+        unsigned int            hooknum;
         /* Hooks are ordered in ascending priority. */
-        int             priority;
+        int                     priority;
 };
 
 struct nf_sockopt_ops {
@@ -131,26 +133,33 @@ extern struct list_head nf_hooks[NFPROTO_NUMPROTO][NF_MAX_HOOKS];
 #ifdef HAVE_JUMP_LABEL
 extern struct static_key nf_hooks_needed[NFPROTO_NUMPROTO][NF_MAX_HOOKS];
 
-static inline bool nf_hooks_active(u_int8_t pf, unsigned int hook)
+static inline bool nf_hook_list_active(struct list_head *nf_hook_list,
+                                       u_int8_t pf, unsigned int hook)
 {
         if (__builtin_constant_p(pf) &&
             __builtin_constant_p(hook))
                 return static_key_false(&nf_hooks_needed[pf][hook]);
 
-        return !list_empty(&nf_hooks[pf][hook]);
+        return !list_empty(nf_hook_list);
 }
 #else
-static inline bool nf_hooks_active(u_int8_t pf, unsigned int hook)
+static inline bool nf_hook_list_active(struct list_head *nf_hook_list,
+                                       u_int8_t pf, unsigned int hook)
 {
-        return !list_empty(&nf_hooks[pf][hook]);
+        return !list_empty(nf_hook_list);
 }
 #endif
 
+static inline bool nf_hooks_active(u_int8_t pf, unsigned int hook)
+{
+        return nf_hook_list_active(&nf_hooks[pf][hook], pf, hook);
+}
+
 int nf_hook_slow(struct sk_buff *skb, struct nf_hook_state *state);
 
 /**
  *      nf_hook_thresh - call a netfilter hook
- *      
+ *
  *      Returns 1 if the hook has allowed the packet to pass.  The function
  *      okfn must be invoked by the caller in this case.  Any other return
  *      value indicates the packet has been consumed by the hook.
@@ -166,8 +175,8 @@ static inline int nf_hook_thresh(u_int8_t pf, unsigned int hook,
         if (nf_hooks_active(pf, hook)) {
                 struct nf_hook_state state;
 
-                nf_hook_state_init(&state, hook, thresh, pf,
-                                   indev, outdev, sk, okfn);
+                nf_hook_state_init(&state, &nf_hooks[pf][hook], hook, thresh,
+                                   pf, indev, outdev, sk, okfn);
                 return nf_hook_slow(skb, &state);
         }
         return 1;
diff --git a/include/linux/netfilter/ipset/ip_set.h b/include/linux/netfilter/ipset/ip_set.h
index 34b172301558..48bb01edcf30 100644
--- a/include/linux/netfilter/ipset/ip_set.h
+++ b/include/linux/netfilter/ipset/ip_set.h
@@ -108,8 +108,13 @@ struct ip_set_counter {
         atomic64_t packets;
 };
 
+struct ip_set_comment_rcu {
+        struct rcu_head rcu;
+        char str[0];
+};
+
 struct ip_set_comment {
-        char *str;
+        struct ip_set_comment_rcu __rcu *c;
 };
 
 struct ip_set_skbinfo {
@@ -122,13 +127,13 @@ struct ip_set_skbinfo {
 struct ip_set;
 
 #define ext_timeout(e, s)       \
-(unsigned long *)(((void *)(e)) + (s)->offset[IPSET_EXT_ID_TIMEOUT])
+((unsigned long *)(((void *)(e)) + (s)->offset[IPSET_EXT_ID_TIMEOUT]))
 #define ext_counter(e, s)       \
-(struct ip_set_counter *)(((void *)(e)) + (s)->offset[IPSET_EXT_ID_COUNTER])
+((struct ip_set_counter *)(((void *)(e)) + (s)->offset[IPSET_EXT_ID_COUNTER]))
 #define ext_comment(e, s)       \
-(struct ip_set_comment *)(((void *)(e)) + (s)->offset[IPSET_EXT_ID_COMMENT])
+((struct ip_set_comment *)(((void *)(e)) + (s)->offset[IPSET_EXT_ID_COMMENT]))
 #define ext_skbinfo(e, s)       \
-(struct ip_set_skbinfo *)(((void *)(e)) + (s)->offset[IPSET_EXT_ID_SKBINFO])
+((struct ip_set_skbinfo *)(((void *)(e)) + (s)->offset[IPSET_EXT_ID_SKBINFO]))
 
 typedef int (*ipset_adtfn)(struct ip_set *set, void *value,
                            const struct ip_set_ext *ext,
@@ -176,6 +181,9 @@ struct ip_set_type_variant {
         /* List elements */
         int (*list)(const struct ip_set *set, struct sk_buff *skb,
                     struct netlink_callback *cb);
+        /* Keep listing private when resizing runs parallel */
+        void (*uref)(struct ip_set *set, struct netlink_callback *cb,
+                     bool start);
 
         /* Return true if "b" set is the same as "a"
          * according to the create set parameters */
@@ -223,7 +231,7 @@ struct ip_set {
         /* The name of the set */
         char name[IPSET_MAXNAMELEN];
         /* Lock protecting the set data */
-        rwlock_t lock;
+        spinlock_t lock;
         /* References to the set */
         u32 ref;
         /* The core set type */
@@ -341,12 +349,11 @@ ip_set_put_skbinfo(struct sk_buff *skb, struct ip_set_skbinfo *skbinfo)
                               cpu_to_be64((u64)skbinfo->skbmark << 32 |
                                           skbinfo->skbmarkmask))) ||
                (skbinfo->skbprio &&
-                nla_put_net32(skb, IPSET_ATTR_SKBPRIO,
+                nla_put_net32(skb, IPSET_ATTR_SKBPRIO,
                               cpu_to_be32(skbinfo->skbprio))) ||
                (skbinfo->skbqueue &&
-                nla_put_net16(skb, IPSET_ATTR_SKBQUEUE,
+                nla_put_net16(skb, IPSET_ATTR_SKBQUEUE,
                              cpu_to_be16(skbinfo->skbqueue)));
-
 }
 
 static inline void
@@ -380,12 +387,12 @@ ip_set_init_counter(struct ip_set_counter *counter,
 
 /* Netlink CB args */
 enum {
-        IPSET_CB_NET = 0,
-        IPSET_CB_DUMP,
-        IPSET_CB_INDEX,
-        IPSET_CB_ARG0,
+        IPSET_CB_NET = 0,       /* net namespace */
+        IPSET_CB_DUMP,          /* dump single set/all sets */
+        IPSET_CB_INDEX,         /* set index */
+        IPSET_CB_PRIVATE,       /* set private data */
+        IPSET_CB_ARG0,          /* type specific */
         IPSET_CB_ARG1,
-        IPSET_CB_ARG2,
 };
 
 /* register and unregister set references */
@@ -533,29 +540,9 @@ bitmap_bytes(u32 a, u32 b)
 #include <linux/netfilter/ipset/ip_set_timeout.h>
 #include <linux/netfilter/ipset/ip_set_comment.h>
 
-static inline int
+int
 ip_set_put_extensions(struct sk_buff *skb, const struct ip_set *set,
-                      const void *e, bool active)
-{
-        if (SET_WITH_TIMEOUT(set)) {
-                unsigned long *timeout = ext_timeout(e, set);
-
-                if (nla_put_net32(skb, IPSET_ATTR_TIMEOUT,
-                        htonl(active ? ip_set_timeout_get(timeout)
-                                : *timeout)))
-                        return -EMSGSIZE;
-        }
-        if (SET_WITH_COUNTER(set) &&
-            ip_set_put_counter(skb, ext_counter(e, set)))
-                return -EMSGSIZE;
-        if (SET_WITH_COMMENT(set) &&
-            ip_set_put_comment(skb, ext_comment(e, set)))
-                return -EMSGSIZE;
-        if (SET_WITH_SKBINFO(set) &&
-            ip_set_put_skbinfo(skb, ext_skbinfo(e, set)))
-                return -EMSGSIZE;
-        return 0;
-}
+                      const void *e, bool active);
 
 #define IP_SET_INIT_KEXT(skb, opt, set)                 \
         { .bytes = (skb)->len, .packets = 1,            \
@@ -565,8 +552,6 @@ ip_set_put_extensions(struct sk_buff *skb, const struct ip_set *set,
         { .bytes = ULLONG_MAX, .packets = ULLONG_MAX,   \
           .timeout = (set)->timeout }
 
-#define IP_SET_INIT_CIDR(a, b) ((a) ? (a) : (b))
-
 #define IPSET_CONCAT(a, b)              a##b
 #define IPSET_TOKEN(a, b)               IPSET_CONCAT(a, b)
 
diff --git a/include/linux/netfilter/ipset/ip_set_comment.h b/include/linux/netfilter/ipset/ip_set_comment.h
index 21217ea008d7..8d0248525957 100644
--- a/include/linux/netfilter/ipset/ip_set_comment.h
+++ b/include/linux/netfilter/ipset/ip_set_comment.h
@@ -16,41 +16,57 @@ ip_set_comment_uget(struct nlattr *tb)
         return nla_data(tb);
 }
 
+/* Called from uadd only, protected by the set spinlock.
+ * The kadt functions don't use the comment extensions in any way.
+ */
 static inline void
 ip_set_init_comment(struct ip_set_comment *comment,
                     const struct ip_set_ext *ext)
 {
+        struct ip_set_comment_rcu *c = rcu_dereference_protected(comment->c, 1);
         size_t len = ext->comment ? strlen(ext->comment) : 0;
 
-        if (unlikely(comment->str)) {
-                kfree(comment->str);
-                comment->str = NULL;
+        if (unlikely(c)) {
+                kfree_rcu(c, rcu);
+                rcu_assign_pointer(comment->c, NULL);
         }
         if (!len)
                 return;
         if (unlikely(len > IPSET_MAX_COMMENT_SIZE))
                 len = IPSET_MAX_COMMENT_SIZE;
-        comment->str = kzalloc(len + 1, GFP_ATOMIC);
-        if (unlikely(!comment->str))
+        c = kzalloc(sizeof(*c) + len + 1, GFP_ATOMIC);
+        if (unlikely(!c))
                 return;
-        strlcpy(comment->str, ext->comment, len + 1);
+        strlcpy(c->str, ext->comment, len + 1);
+        rcu_assign_pointer(comment->c, c);
 }
 
+/* Used only when dumping a set, protected by rcu_read_lock_bh() */
 static inline int
 ip_set_put_comment(struct sk_buff *skb, struct ip_set_comment *comment)
 {
-        if (!comment->str)
+        struct ip_set_comment_rcu *c = rcu_dereference_bh(comment->c);
+
+        if (!c)
                 return 0;
-        return nla_put_string(skb, IPSET_ATTR_COMMENT, comment->str);
+        return nla_put_string(skb, IPSET_ATTR_COMMENT, c->str);
 }
 
+/* Called from uadd/udel, flush or the garbage collectors protected
+ * by the set spinlock.
+ * Called when the set is destroyed and when there can't be any user
+ * of the set data anymore.
+ */
 static inline void
 ip_set_comment_free(struct ip_set_comment *comment)
 {
-        if (unlikely(!comment->str))
+        struct ip_set_comment_rcu *c;
+
+        c = rcu_dereference_protected(comment->c, 1);
+        if (unlikely(!c))
                 return;
-        kfree(comment->str);
-        comment->str = NULL;
+        kfree_rcu(c, rcu);
+        rcu_assign_pointer(comment->c, NULL);
 }
 
 #endif
diff --git a/include/linux/netfilter/ipset/ip_set_timeout.h b/include/linux/netfilter/ipset/ip_set_timeout.h
index 83c2f9e0886c..1d6a935c1ac5 100644
--- a/include/linux/netfilter/ipset/ip_set_timeout.h
+++ b/include/linux/netfilter/ipset/ip_set_timeout.h
@@ -40,38 +40,33 @@ ip_set_timeout_uget(struct nlattr *tb)
 }
 
 static inline bool
-ip_set_timeout_test(unsigned long timeout)
+ip_set_timeout_expired(unsigned long *t)
 {
-        return timeout == IPSET_ELEM_PERMANENT ||
-               time_is_after_jiffies(timeout);
-}
-
-static inline bool
-ip_set_timeout_expired(unsigned long *timeout)
-{
-        return *timeout != IPSET_ELEM_PERMANENT &&
-               time_is_before_jiffies(*timeout);
+        return *t != IPSET_ELEM_PERMANENT && time_is_before_jiffies(*t);
 }
 
 static inline void
-ip_set_timeout_set(unsigned long *timeout, u32 t)
+ip_set_timeout_set(unsigned long *timeout, u32 value)
 {
-        if (!t) {
+        unsigned long t;
+
+        if (!value) {
                 *timeout = IPSET_ELEM_PERMANENT;
                 return;
         }
 
-        *timeout = msecs_to_jiffies(t * 1000) + jiffies;
-        if (*timeout == IPSET_ELEM_PERMANENT)
+        t = msecs_to_jiffies(value * MSEC_PER_SEC) + jiffies;
+        if (t == IPSET_ELEM_PERMANENT)
                 /* Bingo! :-) */
-                (*timeout)--;
+                t--;
+        *timeout = t;
 }
 
 static inline u32
 ip_set_timeout_get(unsigned long *timeout)
 {
         return *timeout == IPSET_ELEM_PERMANENT ? 0 :
-                jiffies_to_msecs(*timeout - jiffies)/1000;
+                jiffies_to_msecs(*timeout - jiffies)/MSEC_PER_SEC;
 }
 
 #endif  /* __KERNEL__ */
diff --git a/include/linux/netfilter/x_tables.h b/include/linux/netfilter/x_tables.h
index a3e215bb0241..286098a5667f 100644
--- a/include/linux/netfilter/x_tables.h
+++ b/include/linux/netfilter/x_tables.h
@@ -62,6 +62,7 @@ struct xt_mtchk_param {
         void *matchinfo;
         unsigned int hook_mask;
         u_int8_t family;
+        bool nft_compat;
 };
 
 /**
@@ -92,6 +93,7 @@ struct xt_tgchk_param {
         void *targinfo;
         unsigned int hook_mask;
         u_int8_t family;
+        bool nft_compat;
 };
 
 /* Target destructor parameters */
@@ -222,13 +224,10 @@ struct xt_table_info {
         unsigned int stacksize;
         unsigned int __percpu *stackptr;
         void ***jumpstack;
-        /* ipt_entry tables: one per CPU */
-        /* Note : this field MUST be the last one, see XT_TABLE_INFO_SZ */
-        void *entries[1];
+
+        unsigned char entries[0] __aligned(8);
 };
 
-#define XT_TABLE_INFO_SZ (offsetof(struct xt_table_info, entries) \
-                          + nr_cpu_ids * sizeof(char *))
 int xt_register_target(struct xt_target *target);
 void xt_unregister_target(struct xt_target *target);
 int xt_register_targets(struct xt_target *target, unsigned int n);
@@ -351,6 +350,57 @@ static inline unsigned long ifname_compare_aligned(const char *_a,
         return ret;
 }
 
+
+/* On SMP, ip(6)t_entry->counters.pcnt holds address of the
+ * real (percpu) counter.  On !SMP, its just the packet count,
+ * so nothing needs to be done there.
+ *
+ * xt_percpu_counter_alloc returns the address of the percpu
+ * counter, or 0 on !SMP. We force an alignment of 16 bytes
+ * so that bytes/packets share a common cache line.
+ *
+ * Hence caller must use IS_ERR_VALUE to check for error, this
+ * allows us to return 0 for single core systems without forcing
+ * callers to deal with SMP vs. NONSMP issues.
+ */
+static inline u64 xt_percpu_counter_alloc(void)
+{
+        if (nr_cpu_ids > 1) {
+                void __percpu *res = __alloc_percpu(sizeof(struct xt_counters),
+                                                    sizeof(struct xt_counters));
+
+                if (res == NULL)
+                        return (u64) -ENOMEM;
+
+                return (u64) (__force unsigned long) res;
+        }
+
+        return 0;
+}
+static inline void xt_percpu_counter_free(u64 pcnt)
+{
+        if (nr_cpu_ids > 1)
+                free_percpu((void __percpu *) (unsigned long) pcnt);
+}
+
+static inline struct xt_counters *
+xt_get_this_cpu_counter(struct xt_counters *cnt)
+{
+        if (nr_cpu_ids > 1)
+                return this_cpu_ptr((void __percpu *) (unsigned long) cnt->pcnt);
+
+        return cnt;
+}
+
+static inline struct xt_counters *
+xt_get_per_cpu_counter(struct xt_counters *cnt, unsigned int cpu)
+{
+        if (nr_cpu_ids > 1)
+                return per_cpu_ptr((void __percpu *) (unsigned long) cnt->pcnt, cpu);
+
+        return cnt;
+}
+
 struct nf_hook_ops *xt_hook_link(const struct xt_table *, nf_hookfn *);
 void xt_hook_unlink(const struct xt_table *, struct nf_hook_ops *);
 
diff --git a/include/linux/netfilter_bridge.h b/include/linux/netfilter_bridge.h
index f2fdb5a52070..6d80fc686323 100644
--- a/include/linux/netfilter_bridge.h
+++ b/include/linux/netfilter_bridge.h
@@ -20,13 +20,6 @@ enum nf_br_hook_priorities {
 #define BRNF_BRIDGED_DNAT               0x02
 #define BRNF_NF_BRIDGE_PREROUTING       0x08
 
-static inline unsigned int nf_bridge_mtu_reduction(const struct sk_buff *skb)
-{
-        if (skb->nf_bridge->orig_proto == BRNF_PROTO_PPPOE)
-                return PPPOE_SES_HLEN;
-        return 0;
-}
-
 int br_handle_frame_finish(struct sock *sk, struct sk_buff *skb);
 
 static inline void br_drop_fake_rtable(struct sk_buff *skb)
diff --git a/include/linux/netfilter_defs.h b/include/linux/netfilter_defs.h
new file mode 100644
index 000000000000..d3a7f8597e82
--- /dev/null
+++ b/include/linux/netfilter_defs.h
@@ -0,0 +1,9 @@
+#ifndef __LINUX_NETFILTER_CORE_H_
+#define __LINUX_NETFILTER_CORE_H_
+
+#include <uapi/linux/netfilter.h>
+
+/* Largest hook number + 1, see uapi/linux/netfilter_decnet.h */
+#define NF_MAX_HOOKS 8
+
+#endif
diff --git a/include/linux/netfilter_ingress.h b/include/linux/netfilter_ingress.h
new file mode 100644
index 000000000000..cb0727fe2b3d
--- /dev/null
+++ b/include/linux/netfilter_ingress.h
@@ -0,0 +1,41 @@
+#ifndef _NETFILTER_INGRESS_H_
+#define _NETFILTER_INGRESS_H_
+
+#include <linux/netfilter.h>
+#include <linux/netdevice.h>
+
+#ifdef CONFIG_NETFILTER_INGRESS
+static inline int nf_hook_ingress_active(struct sk_buff *skb)
+{
+        return nf_hook_list_active(&skb->dev->nf_hooks_ingress,
+                                   NFPROTO_NETDEV, NF_NETDEV_INGRESS);
+}
+
+static inline int nf_hook_ingress(struct sk_buff *skb)
+{
+        struct nf_hook_state state;
+
+        nf_hook_state_init(&state, &skb->dev->nf_hooks_ingress,
+                           NF_NETDEV_INGRESS, INT_MIN, NFPROTO_NETDEV, NULL,
+                           skb->dev, NULL, NULL);
+        return nf_hook_slow(skb, &state);
+}
+
+static inline void nf_hook_ingress_init(struct net_device *dev)
+{
+        INIT_LIST_HEAD(&dev->nf_hooks_ingress);
+}
+#else /* CONFIG_NETFILTER_INGRESS */
+static inline int nf_hook_ingress_active(struct sk_buff *skb)
+{
+        return 0;
+}
+
+static inline int nf_hook_ingress(struct sk_buff *skb)
+{
+        return 0;
+}
+
+static inline void nf_hook_ingress_init(struct net_device *dev) {}
+#endif /* CONFIG_NETFILTER_INGRESS */
+#endif /* _NETFILTER_INGRESS_H_ */
diff --git a/include/linux/netfilter_ipv6.h b/include/linux/netfilter_ipv6.h
index 64dad1cc1a4b..8b7d28f3aada 100644
--- a/include/linux/netfilter_ipv6.h
+++ b/include/linux/netfilter_ipv6.h
@@ -25,6 +25,9 @@ void ipv6_netfilter_fini(void);
 struct nf_ipv6_ops {
         int (*chk_addr)(struct net *net, const struct in6_addr *addr,
                         const struct net_device *dev, int strict);
+        void (*route_input)(struct sk_buff *skb);
+        int (*fragment)(struct sock *sk, struct sk_buff *skb,
+                        int (*output)(struct sock *, struct sk_buff *));
 };
 
 extern const struct nf_ipv6_ops __rcu *nf_ipv6_ops;
diff --git a/include/linux/netlink.h b/include/linux/netlink.h
index 6835c1279df7..9120edb650a0 100644
--- a/include/linux/netlink.h
+++ b/include/linux/netlink.h
@@ -28,6 +28,8 @@ struct netlink_skb_parms {
         __u32                   dst_group;
         __u32                   flags;
         struct sock             *sk;
+        bool                    nsid_is_set;
+        int                     nsid;
 };
 
 #define NETLINK_CB(skb)         (*(struct netlink_skb_parms*)&((skb)->cb))
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index cb63a7b522ef..fcff8f865341 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -2330,6 +2330,8 @@
 #define PCI_DEVICE_ID_ALTIMA_AC9100     0x03ea
 #define PCI_DEVICE_ID_ALTIMA_AC1003     0x03eb
 
+#define PCI_VENDOR_ID_CAVIUM            0x177d
+
 #define PCI_VENDOR_ID_BELKIN            0x1799
 #define PCI_DEVICE_ID_BELKIN_F5D7010V7  0x701f
 
diff --git a/include/linux/phy.h b/include/linux/phy.h
index 685809835b5c..a26c3f84b8dd 100644
--- a/include/linux/phy.h
+++ b/include/linux/phy.h
@@ -181,6 +181,9 @@ struct mii_bus {
         /* PHY addresses to be ignored when probing */
         u32 phy_mask;
 
+        /* PHY addresses to ignore the TA/read failure */
+        u32 phy_ignore_ta_mask;
+
         /*
          * Pointer to an array of interrupts, each PHY's
          * interrupt at the index matching its address
@@ -675,6 +678,17 @@ static inline bool phy_is_internal(struct phy_device *phydev)
 }
 
 /**
+ * phy_interface_is_rgmii - Convenience function for testing if a PHY interface
+ * is RGMII (all variants)
+ * @phydev: the phy_device struct
+ */
+static inline bool phy_interface_is_rgmii(struct phy_device *phydev)
+{
+        return phydev->interface >= PHY_INTERFACE_MODE_RGMII &&
+                phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID;
+}
+
+/**
  * phy_write_mmd - Convenience function for writing a register
  * on an MMD on a given PHY.
  * @phydev: The phy_device struct
diff --git a/include/linux/platform_data/nfcmrvl.h b/include/linux/platform_data/nfcmrvl.h
new file mode 100644
index 000000000000..ac91707dabcb
--- /dev/null
+++ b/include/linux/platform_data/nfcmrvl.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2015, Marvell International Ltd.
+ *
+ * This software file (the "File") is distributed by Marvell International
+ * Ltd. under the terms of the GNU General Public License Version 2, June 1991
+ * (the "License").  You may use, redistribute and/or modify this File in
+ * accordance with the terms and conditions of the License, a copy of which
+ * is available on the worldwide web at
+ * http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
+ *
+ * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
+ * ARE EXPRESSLY DISCLAIMED.  The License provides additional details about
+ * this warranty disclaimer.
+ */
+
+#ifndef _NFCMRVL_PTF_H_
+#define _NFCMRVL_PTF_H_
+
+struct nfcmrvl_platform_data {
+        /*
+         * Generic
+         */
+
+        /* GPIO that is wired to RESET_N signal */
+        unsigned int reset_n_io;
+        /* Tell if transport is muxed in HCI one */
+        unsigned int hci_muxed;
+
+        /*
+         * UART specific
+         */
+
+        /* Tell if UART needs flow control at init */
+        unsigned int flow_control;
+        /* Tell if firmware supports break control for power management */
+        unsigned int break_control;
+};
+
+#endif /* _NFCMRVL_PTF_H_ */
diff --git a/include/linux/platform_data/st21nfcb.h b/include/linux/platform_data/st-nci.h
index b023373d9874..d9d400a297bd 100644
--- a/include/linux/platform_data/st21nfcb.h
+++ b/include/linux/platform_data/st-nci.h
@@ -1,7 +1,7 @@
 /*
- * Driver include for the ST21NFCB NFC chip.
+ * Driver include for ST NCI NFC chip family.
  *
- * Copyright (C) 2014  STMicroelectronics SAS. All rights reserved.
+ * Copyright (C) 2014-2015  STMicroelectronics SAS. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -16,14 +16,14 @@
  * along with this program; if not, see <http://www.gnu.org/licenses/>.
  */
 
-#ifndef _ST21NFCB_NCI_H_
-#define _ST21NFCB_NCI_H_
+#ifndef _ST_NCI_H_
+#define _ST_NCI_H_
 
-#define ST21NFCB_NCI_DRIVER_NAME "st21nfcb_nci"
+#define ST_NCI_DRIVER_NAME "st_nci"
 
-struct st21nfcb_nfc_platform_data {
+struct st_nci_nfc_platform_data {
         unsigned int gpio_reset;
         unsigned int irq_polarity;
 };
 
-#endif /* _ST21NFCB_NCI_H_ */
+#endif /* _ST_NCI_H_ */
diff --git a/include/linux/platform_data/st_nci.h b/include/linux/platform_data/st_nci.h
new file mode 100644
index 000000000000..d9d400a297bd
--- /dev/null
+++ b/include/linux/platform_data/st_nci.h
@@ -0,0 +1,29 @@
+/*
+ * Driver include for ST NCI NFC chip family.
+ *
+ * Copyright (C) 2014-2015  STMicroelectronics SAS. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _ST_NCI_H_
+#define _ST_NCI_H_
+
+#define ST_NCI_DRIVER_NAME "st_nci"
+
+struct st_nci_nfc_platform_data {
+        unsigned int gpio_reset;
+        unsigned int irq_polarity;
+};
+
+#endif /* _ST_NCI_H_ */
diff --git a/include/linux/rtnetlink.h b/include/linux/rtnetlink.h
index 7b8e260c4a27..39adaa9529eb 100644
--- a/include/linux/rtnetlink.h
+++ b/include/linux/rtnetlink.h
@@ -79,17 +79,9 @@ static inline struct netdev_queue *dev_ingress_queue(struct net_device *dev)
 
 struct netdev_queue *dev_ingress_queue_create(struct net_device *dev);
 
-#ifdef CONFIG_NET_CLS_ACT
+#ifdef CONFIG_NET_INGRESS
 void net_inc_ingress_queue(void);
 void net_dec_ingress_queue(void);
-#else
-static inline void net_inc_ingress_queue(void)
-{
-}
-
-static inline void net_dec_ingress_queue(void)
-{
-}
 #endif
 
 extern void rtnetlink_init(void);
@@ -122,5 +114,9 @@ extern int ndo_dflt_fdb_del(struct ndmsg *ndm,
 
 extern int ndo_dflt_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
                                    struct net_device *dev, u16 mode,
-                                   u32 flags, u32 mask, int nlflags);
+                                   u32 flags, u32 mask, int nlflags,
+                                   u32 filter_mask,
+                                   int (*vlan_fill)(struct sk_buff *skb,
+                                                    struct net_device *dev,
+                                                    u32 filter_mask));
 #endif  /* __LINUX_RTNETLINK_H */
diff --git a/include/linux/skbuff.h b/include/linux/skbuff.h
index f15154a879c7..d6cdd6e87d53 100644
--- a/include/linux/skbuff.h
+++ b/include/linux/skbuff.h
@@ -34,7 +34,9 @@
 #include <linux/dma-mapping.h>
 #include <linux/netdev_features.h>
 #include <linux/sched.h>
-#include <net/flow_keys.h>
+#include <net/flow_dissector.h>
+#include <linux/splice.h>
+#include <linux/in6.h>
 
 /* A. Checksumming of received packets by device.
  *
@@ -170,13 +172,19 @@ struct nf_bridge_info {
                 BRNF_PROTO_UNCHANGED,
                 BRNF_PROTO_8021Q,
                 BRNF_PROTO_PPPOE
-        } orig_proto;
+        } orig_proto:8;
         bool                    pkt_otherhost;
+        __u16                   frag_max_size;
         unsigned int            mask;
         struct net_device       *physindev;
-        struct net_device       *physoutdev;
-        char                    neigh_header[8];
-        __be32                  ipv4_daddr;
+        union {
+                struct net_device *physoutdev;
+                char neigh_header[8];
+        };
+        union {
+                __be32          ipv4_daddr;
+                struct in6_addr ipv6_daddr;
+        };
 };
 #endif
 
@@ -859,6 +867,9 @@ int skb_append_datato_frags(struct sock *sk, struct sk_buff *skb,
                                         int len, int odd, struct sk_buff *skb),
                             void *from, int length);
 
+int skb_append_pagefrags(struct sk_buff *skb, struct page *page,
+                         int offset, size_t size);
+
 struct skb_seq_state {
         __u32           lower_offset;
         __u32           upper_offset;
@@ -919,7 +930,6 @@ skb_set_hash(struct sk_buff *skb, __u32 hash, enum pkt_hash_types type)
         skb->hash = hash;
 }
 
-void __skb_get_hash(struct sk_buff *skb);
 static inline __u32 skb_get_hash(struct sk_buff *skb)
 {
         if (!skb->l4_hash && !skb->sw_hash)
@@ -928,6 +938,8 @@ static inline __u32 skb_get_hash(struct sk_buff *skb)
         return skb->hash;
 }
 
+__u32 skb_get_hash_perturb(const struct sk_buff *skb, u32 perturb);
+
 static inline __u32 skb_get_hash_raw(const struct sk_buff *skb)
 {
         return skb->hash;
@@ -1935,8 +1947,8 @@ static inline void skb_probe_transport_header(struct sk_buff *skb,
 
         if (skb_transport_header_was_set(skb))
                 return;
-        else if (skb_flow_dissect(skb, &keys))
-                skb_set_transport_header(skb, keys.thoff);
+        else if (skb_flow_dissect_flow_keys(skb, &keys))
+                skb_set_transport_header(skb, keys.control.thoff);
         else
                 skb_set_transport_header(skb, offset_hint);
 }
@@ -2127,10 +2139,6 @@ static inline void __skb_queue_purge(struct sk_buff_head *list)
                 kfree_skb(skb);
 }
 
-#define NETDEV_FRAG_PAGE_MAX_ORDER get_order(32768)
-#define NETDEV_FRAG_PAGE_MAX_SIZE  (PAGE_SIZE << NETDEV_FRAG_PAGE_MAX_ORDER)
-#define NETDEV_PAGECNT_MAX_BIAS    NETDEV_FRAG_PAGE_MAX_SIZE
-
 void *netdev_alloc_frag(unsigned int fragsz);
 
 struct sk_buff *__netdev_alloc_skb(struct net_device *dev, unsigned int length,
@@ -2185,6 +2193,11 @@ static inline struct sk_buff *netdev_alloc_skb_ip_align(struct net_device *dev,
         return __netdev_alloc_skb_ip_align(dev, length, GFP_ATOMIC);
 }
 
+static inline void skb_free_frag(void *addr)
+{
+        __free_page_frag(addr);
+}
+
 void *napi_alloc_frag(unsigned int fragsz);
 struct sk_buff *__napi_alloc_skb(struct napi_struct *napi,
                                  unsigned int length, gfp_t gfp_mask);
@@ -2692,9 +2705,15 @@ int skb_copy_bits(const struct sk_buff *skb, int offset, void *to, int len);
 int skb_store_bits(struct sk_buff *skb, int offset, const void *from, int len);
 __wsum skb_copy_and_csum_bits(const struct sk_buff *skb, int offset, u8 *to,
                               int len, __wsum csum);
-int skb_splice_bits(struct sk_buff *skb, unsigned int offset,
+ssize_t skb_socket_splice(struct sock *sk,
+                          struct pipe_inode_info *pipe,
+                          struct splice_pipe_desc *spd);
+int skb_splice_bits(struct sk_buff *skb, struct sock *sk, unsigned int offset,
                     struct pipe_inode_info *pipe, unsigned int len,
-                    unsigned int flags);
+                    unsigned int flags,
+                    ssize_t (*splice_cb)(struct sock *,
+                                         struct pipe_inode_info *,
+                                         struct splice_pipe_desc *));
 void skb_copy_and_csum_dev(const struct sk_buff *skb, u8 *to);
 unsigned int skb_zerocopy_headlen(const struct sk_buff *from);
 int skb_zerocopy(struct sk_buff *to, struct sk_buff *from,
@@ -2729,8 +2748,9 @@ __wsum __skb_checksum(const struct sk_buff *skb, int offset, int len,
 __wsum skb_checksum(const struct sk_buff *skb, int offset, int len,
                     __wsum csum);
 
-static inline void *__skb_header_pointer(const struct sk_buff *skb, int offset,
-                                         int len, void *data, int hlen, void *buffer)
+static inline void * __must_check
+__skb_header_pointer(const struct sk_buff *skb, int offset,
+                     int len, void *data, int hlen, void *buffer)
 {
         if (hlen - offset >= len)
                 return data + offset;
@@ -2742,8 +2762,8 @@ static inline void *__skb_header_pointer(const struct sk_buff *skb, int offset,
         return buffer;
 }
 
-static inline void *skb_header_pointer(const struct sk_buff *skb, int offset,
-                                       int len, void *buffer)
+static inline void * __must_check
+skb_header_pointer(const struct sk_buff *skb, int offset, int len, void *buffer)
 {
         return __skb_header_pointer(skb, offset, len, skb->data,
                                     skb_headlen(skb), buffer);
@@ -3050,7 +3070,7 @@ static inline __sum16 __skb_checksum_validate_complete(struct sk_buff *skb,
                 }
         } else if (skb->csum_bad) {
                 /* ip_summed == CHECKSUM_NONE in this case */
-                return 1;
+                return (__force __sum16)1;
         }
 
         skb->csum = psum;
@@ -3298,9 +3318,6 @@ static inline bool skb_rx_queue_recorded(const struct sk_buff *skb)
         return skb->queue_mapping != 0;
 }
 
-u16 __skb_tx_hash(const struct net_device *dev, struct sk_buff *skb,
-                  unsigned int num_tx_queues);
-
 static inline struct sec_path *skb_sec_path(struct sk_buff *skb)
 {
 #ifdef CONFIG_XFRM
@@ -3355,15 +3372,14 @@ static inline int gso_pskb_expand_head(struct sk_buff *skb, int extra)
 static inline __sum16 gso_make_checksum(struct sk_buff *skb, __wsum res)
 {
         int plen = SKB_GSO_CB(skb)->csum_start - skb_headroom(skb) -
-            skb_transport_offset(skb);
-        __u16 csum;
+                   skb_transport_offset(skb);
+        __wsum partial;
 
-        csum = csum_fold(csum_partial(skb_transport_header(skb),
-                                      plen, skb->csum));
+        partial = csum_partial(skb_transport_header(skb), plen, skb->csum);
         skb->csum = res;
         SKB_GSO_CB(skb)->csum_start -= plen;
 
-        return csum;
+        return csum_fold(partial);
 }
 
 static inline bool skb_is_gso(const struct sk_buff *skb)
@@ -3418,10 +3434,9 @@ static inline void skb_checksum_none_assert(const struct sk_buff *skb)
 bool skb_partial_csum_set(struct sk_buff *skb, u16 start, u16 off);
 
 int skb_checksum_setup(struct sk_buff *skb, bool recalculate);
-
-u32 skb_get_poff(const struct sk_buff *skb);
-u32 __skb_get_poff(const struct sk_buff *skb, void *data,
-                   const struct flow_keys *keys, int hlen);
+struct sk_buff *skb_checksum_trimmed(struct sk_buff *skb,
+                                     unsigned int transport_len,
+                                     __sum16(*skb_chkf)(struct sk_buff *skb));
 
 /**
  * skb_head_is_locked - Determine if the skb->head is locked down
diff --git a/include/linux/sock_diag.h b/include/linux/sock_diag.h
index 083ac388098e..fddebc617469 100644
--- a/include/linux/sock_diag.h
+++ b/include/linux/sock_diag.h
@@ -1,7 +1,10 @@
 #ifndef __SOCK_DIAG_H__
 #define __SOCK_DIAG_H__
 
+#include <linux/netlink.h>
 #include <linux/user_namespace.h>
+#include <net/net_namespace.h>
+#include <net/sock.h>
 #include <uapi/linux/sock_diag.h>
 
 struct sk_buff;
@@ -11,6 +14,7 @@ struct sock;
 struct sock_diag_handler {
         __u8 family;
         int (*dump)(struct sk_buff *skb, struct nlmsghdr *nlh);
+        int (*get_info)(struct sk_buff *skb, struct sock *sk);
 };
 
 int sock_diag_register(const struct sock_diag_handler *h);
@@ -26,4 +30,42 @@ int sock_diag_put_meminfo(struct sock *sk, struct sk_buff *skb, int attr);
 int sock_diag_put_filterinfo(bool may_report_filterinfo, struct sock *sk,
                              struct sk_buff *skb, int attrtype);
 
+static inline
+enum sknetlink_groups sock_diag_destroy_group(const struct sock *sk)
+{
+        switch (sk->sk_family) {
+        case AF_INET:
+                switch (sk->sk_protocol) {
+                case IPPROTO_TCP:
+                        return SKNLGRP_INET_TCP_DESTROY;
+                case IPPROTO_UDP:
+                        return SKNLGRP_INET_UDP_DESTROY;
+                default:
+                        return SKNLGRP_NONE;
+                }
+        case AF_INET6:
+                switch (sk->sk_protocol) {
+                case IPPROTO_TCP:
+                        return SKNLGRP_INET6_TCP_DESTROY;
+                case IPPROTO_UDP:
+                        return SKNLGRP_INET6_UDP_DESTROY;
+                default:
+                        return SKNLGRP_NONE;
+                }
+        default:
+                return SKNLGRP_NONE;
+        }
+}
+
+static inline
+bool sock_diag_has_destroy_listeners(const struct sock *sk)
+{
+        const struct net *n = sock_net(sk);
+        const enum sknetlink_groups group = sock_diag_destroy_group(sk);
+
+        return group != SKNLGRP_NONE && n->diag_nlsk &&
+                netlink_has_listeners(n->diag_nlsk, group);
+}
+void sock_diag_broadcast_destroy(struct sock *sk);
+
 #endif
diff --git a/include/linux/spi/cc2520.h b/include/linux/spi/cc2520.h
index e741e8baad92..85b8ee67e937 100644
--- a/include/linux/spi/cc2520.h
+++ b/include/linux/spi/cc2520.h
@@ -21,7 +21,6 @@ struct cc2520_platform_data {
         int sfd;
         int reset;
         int vreg;
-        bool amplified;
 };
 
 #endif
diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h
index 7f484a239f53..c735f5c91eea 100644
--- a/include/linux/stmmac.h
+++ b/include/linux/stmmac.h
@@ -99,6 +99,7 @@ struct plat_stmmacenet_data {
         int phy_addr;
         int interface;
         struct stmmac_mdio_bus_data *mdio_bus_data;
+        struct device_node *phy_node;
         struct stmmac_dma_cfg *dma_cfg;
         int clk_csr;
         int has_gmac;
diff --git a/include/linux/tcp.h b/include/linux/tcp.h
index e8bbf403618f..48c3696e8645 100644
--- a/include/linux/tcp.h
+++ b/include/linux/tcp.h
@@ -149,11 +149,16 @@ struct tcp_sock {
                                  * sum(delta(rcv_nxt)), or how many bytes
                                  * were acked.
                                  */
+        u32     segs_in;        /* RFC4898 tcpEStatsPerfSegsIn
+                                 * total number of segments in.
+                                 */
         u32     rcv_nxt;        /* What we want to receive next         */
         u32     copied_seq;     /* Head of yet unread data              */
         u32     rcv_wup;        /* rcv_nxt on last window update sent   */
         u32     snd_nxt;        /* Next sequence we send                */
-
+        u32     segs_out;       /* RFC4898 tcpEStatsPerfSegsOut
+                                 * The total number of segments sent.
+                                 */
         u64     bytes_acked;    /* RFC4898 tcpEStatsAppHCThruOctetsAcked
                                  * sum(delta(snd_una)), or how many bytes
                                  * were acked.
@@ -201,6 +206,7 @@ struct tcp_sock {
                 syn_fastopen:1, /* SYN includes Fast Open option */
                 syn_fastopen_exp:1,/* SYN includes Fast Open exp. option */
                 syn_data_acked:1,/* data in SYN is acked by SYN-ACK */
+                save_syn:1,     /* Save headers of SYN packet */
                 is_cwnd_limited:1;/* forward progress limited by snd_cwnd? */
         u32     tlp_high_seq;   /* snd_nxt at the time of TLP retransmit. */
 
@@ -328,6 +334,7 @@ struct tcp_sock {
          * socket. Used to retransmit SYNACKs etc.
          */
         struct request_sock *fastopen_rsk;
+        u32     *saved_syn;
 };
 
 enum tsq_flags {
@@ -395,4 +402,10 @@ static inline int fastopen_init_queue(struct sock *sk, int backlog)
         return 0;
 }
 
+static inline void tcp_saved_syn_free(struct tcp_sock *tp)
+{
+        kfree(tp->saved_syn);
+        tp->saved_syn = NULL;
+}
+
 #endif  /* _LINUX_TCP_H */
diff --git a/include/linux/u64_stats_sync.h b/include/linux/u64_stats_sync.h
index 4b4439e75f45..df89c9bcba7d 100644
--- a/include/linux/u64_stats_sync.h
+++ b/include/linux/u64_stats_sync.h
@@ -68,11 +68,12 @@ struct u64_stats_sync {
 };
 
 
+static inline void u64_stats_init(struct u64_stats_sync *syncp)
+{
 #if BITS_PER_LONG == 32 && defined(CONFIG_SMP)
-# define u64_stats_init(syncp)  seqcount_init(syncp.seq)
-#else
-# define u64_stats_init(syncp)  do { } while (0)
+        seqcount_init(&syncp->seq);
 #endif
+}
 
 static inline void u64_stats_update_begin(struct u64_stats_sync *syncp)
 {