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authorNicolas Ferre <nicolas.ferre@atmel.com>2015-06-17 08:40:38 -0400
committerStephen Boyd <sboyd@codeaurora.org>2015-10-01 15:39:41 -0400
commit96ef36e9c424b7a66413bb9229ef5afcddf4fef4 (patch)
tree636ed3e2dafa26a9b51de5ef0cea33cdf5252204 /include/linux
parenta3ff23375aa4dac7ceee2087f02b4141c78c762e (diff)
clk: at91: cleanup PMC header file for PCR register fields
Add _MASK and _OFFSET values and cleanup register fields layout. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'include/linux')
-rw-r--r--include/linux/clk/at91_pmc.h14
1 files changed, 6 insertions, 8 deletions
diff --git a/include/linux/clk/at91_pmc.h b/include/linux/clk/at91_pmc.h
index 7669f7618f39..dfc59e2b64fb 100644
--- a/include/linux/clk/at91_pmc.h
+++ b/include/linux/clk/at91_pmc.h
@@ -182,13 +182,11 @@ extern void __iomem *at91_pmc_base;
182#define AT91_PMC_PCSR1 0x108 /* Peripheral Clock Enable Register 1 */ 182#define AT91_PMC_PCSR1 0x108 /* Peripheral Clock Enable Register 1 */
183 183
184#define AT91_PMC_PCR 0x10c /* Peripheral Control Register [some SAM9 and SAMA5] */ 184#define AT91_PMC_PCR 0x10c /* Peripheral Control Register [some SAM9 and SAMA5] */
185#define AT91_PMC_PCR_PID (0x3f << 0) /* Peripheral ID */ 185#define AT91_PMC_PCR_PID_MASK 0x3f
186#define AT91_PMC_PCR_CMD (0x1 << 12) /* Command (read=0, write=1) */ 186#define AT91_PMC_PCR_CMD (0x1 << 12) /* Command (read=0, write=1) */
187#define AT91_PMC_PCR_DIV(n) ((n) << 16) /* Divisor Value */ 187#define AT91_PMC_PCR_DIV_OFFSET 16
188#define AT91_PMC_PCR_DIV0 0x0 /* Peripheral clock is MCK */ 188#define AT91_PMC_PCR_DIV_MASK (0x3 << AT91_PMC_PCR_DIV_OFFSET)
189#define AT91_PMC_PCR_DIV2 0x1 /* Peripheral clock is MCK/2 */ 189#define AT91_PMC_PCR_DIV(n) ((n) << AT91_PMC_PCR_DIV_OFFSET) /* Divisor Value */
190#define AT91_PMC_PCR_DIV4 0x2 /* Peripheral clock is MCK/4 */ 190#define AT91_PMC_PCR_EN (0x1 << 28) /* Enable */
191#define AT91_PMC_PCR_DIV8 0x3 /* Peripheral clock is MCK/8 */
192#define AT91_PMC_PCR_EN (0x1 << 28) /* Enable */
193 191
194#endif 192#endif