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authorHadar Hen Zion <hadarh@mellanox.com>2016-08-03 08:08:33 -0400
committerLeon Romanovsky <leon@kernel.org>2016-08-17 10:46:00 -0400
commit7adbde2035c2e5baf2f6a90eba11813db4813a67 (patch)
treee3b0d33703146e2a8da4577c961d30363a9b9665 /include/linux
parent9def7121bed3be8a9d126c900ca7067647bc4789 (diff)
net/mlx5: Update mlx5_ifc.h for vxlan encap/decap
Add the required definitions related to vxlan encap/decap. Signed-off-by: Hadar Hen Zion <hadarh@mellanox.com> Signed-off-by: Ilya Lesokhin <ilyal@mellanox.com> Signed-off-by: Saeed Mahameed <saeedm@mellanox.com> Signed-off-by: Leon Romanovsky <leon@kernel.org>
Diffstat (limited to 'include/linux')
-rw-r--r--include/linux/mlx5/mlx5_ifc.h105
1 files changed, 101 insertions, 4 deletions
diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h
index 7a8ef0af94e7..3766110e13ea 100644
--- a/include/linux/mlx5/mlx5_ifc.h
+++ b/include/linux/mlx5/mlx5_ifc.h
@@ -212,6 +212,8 @@ enum {
212 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 212 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
213 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 213 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
214 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 214 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
215 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d,
216 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e,
215 MLX5_CMD_OP_MAX 217 MLX5_CMD_OP_MAX
216}; 218};
217 219
@@ -281,7 +283,9 @@ struct mlx5_ifc_flow_table_prop_layout_bits {
281 u8 modify_root[0x1]; 283 u8 modify_root[0x1];
282 u8 identified_miss_table_mode[0x1]; 284 u8 identified_miss_table_mode[0x1];
283 u8 flow_table_modify[0x1]; 285 u8 flow_table_modify[0x1];
284 u8 reserved_at_7[0x19]; 286 u8 encap[0x1];
287 u8 decap[0x1];
288 u8 reserved_at_9[0x17];
285 289
286 u8 reserved_at_20[0x2]; 290 u8 reserved_at_20[0x2];
287 u8 log_max_ft_size[0x6]; 291 u8 log_max_ft_size[0x6];
@@ -512,7 +516,15 @@ struct mlx5_ifc_e_switch_cap_bits {
512 u8 nic_vport_node_guid_modify[0x1]; 516 u8 nic_vport_node_guid_modify[0x1];
513 u8 nic_vport_port_guid_modify[0x1]; 517 u8 nic_vport_port_guid_modify[0x1];
514 518
515 u8 reserved_at_20[0x7e0]; 519 u8 vxlan_encap_decap[0x1];
520 u8 nvgre_encap_decap[0x1];
521 u8 reserved_at_22[0x9];
522 u8 log_max_encap_headers[0x5];
523 u8 reserved_2b[0x6];
524 u8 max_encap_header_size[0xa];
525
526 u8 reserved_40[0x7c0];
527
516}; 528};
517 529
518struct mlx5_ifc_qos_cap_bits { 530struct mlx5_ifc_qos_cap_bits {
@@ -2067,6 +2079,8 @@ enum {
2067 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 2079 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
2068 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 2080 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
2069 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 2081 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
2082 MLX5_FLOW_CONTEXT_ACTION_ENCAP = 0x10,
2083 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
2070}; 2084};
2071 2085
2072struct mlx5_ifc_flow_context_bits { 2086struct mlx5_ifc_flow_context_bits {
@@ -2086,7 +2100,9 @@ struct mlx5_ifc_flow_context_bits {
2086 u8 reserved_at_a0[0x8]; 2100 u8 reserved_at_a0[0x8];
2087 u8 flow_counter_list_size[0x18]; 2101 u8 flow_counter_list_size[0x18];
2088 2102
2089 u8 reserved_at_c0[0x140]; 2103 u8 encap_id[0x20];
2104
2105 u8 reserved_at_e0[0x120];
2090 2106
2091 struct mlx5_ifc_fte_match_param_bits match_value; 2107 struct mlx5_ifc_fte_match_param_bits match_value;
2092 2108
@@ -4216,6 +4232,85 @@ struct mlx5_ifc_query_eq_in_bits {
4216 u8 reserved_at_60[0x20]; 4232 u8 reserved_at_60[0x20];
4217}; 4233};
4218 4234
4235struct mlx5_ifc_encap_header_in_bits {
4236 u8 reserved_at_0[0x5];
4237 u8 header_type[0x3];
4238 u8 reserved_at_8[0xe];
4239 u8 encap_header_size[0xa];
4240
4241 u8 reserved_at_20[0x10];
4242 u8 encap_header[2][0x8];
4243
4244 u8 more_encap_header[0][0x8];
4245};
4246
4247struct mlx5_ifc_query_encap_header_out_bits {
4248 u8 status[0x8];
4249 u8 reserved_at_8[0x18];
4250
4251 u8 syndrome[0x20];
4252
4253 u8 reserved_at_40[0xa0];
4254
4255 struct mlx5_ifc_encap_header_in_bits encap_header[0];
4256};
4257
4258struct mlx5_ifc_query_encap_header_in_bits {
4259 u8 opcode[0x10];
4260 u8 reserved_at_10[0x10];
4261
4262 u8 reserved_at_20[0x10];
4263 u8 op_mod[0x10];
4264
4265 u8 encap_id[0x20];
4266
4267 u8 reserved_at_60[0xa0];
4268};
4269
4270struct mlx5_ifc_alloc_encap_header_out_bits {
4271 u8 status[0x8];
4272 u8 reserved_at_8[0x18];
4273
4274 u8 syndrome[0x20];
4275
4276 u8 encap_id[0x20];
4277
4278 u8 reserved_at_60[0x20];
4279};
4280
4281struct mlx5_ifc_alloc_encap_header_in_bits {
4282 u8 opcode[0x10];
4283 u8 reserved_at_10[0x10];
4284
4285 u8 reserved_at_20[0x10];
4286 u8 op_mod[0x10];
4287
4288 u8 reserved_at_40[0xa0];
4289
4290 struct mlx5_ifc_encap_header_in_bits encap_header;
4291};
4292
4293struct mlx5_ifc_dealloc_encap_header_out_bits {
4294 u8 status[0x8];
4295 u8 reserved_at_8[0x18];
4296
4297 u8 syndrome[0x20];
4298
4299 u8 reserved_at_40[0x40];
4300};
4301
4302struct mlx5_ifc_dealloc_encap_header_in_bits {
4303 u8 opcode[0x10];
4304 u8 reserved_at_10[0x10];
4305
4306 u8 reserved_20[0x10];
4307 u8 op_mod[0x10];
4308
4309 u8 encap_id[0x20];
4310
4311 u8 reserved_60[0x20];
4312};
4313
4219struct mlx5_ifc_query_dct_out_bits { 4314struct mlx5_ifc_query_dct_out_bits {
4220 u8 status[0x8]; 4315 u8 status[0x8];
4221 u8 reserved_at_8[0x18]; 4316 u8 reserved_at_8[0x18];
@@ -6102,7 +6197,9 @@ struct mlx5_ifc_create_flow_table_in_bits {
6102 6197
6103 u8 reserved_at_a0[0x20]; 6198 u8 reserved_at_a0[0x20];
6104 6199
6105 u8 reserved_at_c0[0x4]; 6200 u8 encap_en[0x1];
6201 u8 decap_en[0x1];
6202 u8 reserved_at_c2[0x2];
6106 u8 table_miss_mode[0x4]; 6203 u8 table_miss_mode[0x4];
6107 u8 level[0x8]; 6204 u8 level[0x8];
6108 u8 reserved_at_d0[0x8]; 6205 u8 reserved_at_d0[0x8];