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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2016-05-19 14:47:18 -0400 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2016-05-19 14:47:18 -0400 |
| commit | a0d3c7c5c07cfbe00ab89438ddf82482f5a99422 (patch) | |
| tree | 560def78af776bef5d0d0202580c4be0fc6219c6 /include/linux/platform_data | |
| parent | ec67b14c1be4ebe4cf08f06746a8d0313ab85432 (diff) | |
| parent | f9114a54c1d828abbe87ac446a2da49d9720203f (diff) | |
Merge tag 'dmaengine-4.7-rc1' of git://git.infradead.org/users/vkoul/slave-dma
Pull dmaengine updates from Vinod Koul:
"This time round the update brings in following changes:
- new tegra driver for ADMA device
- support for Xilinx AXI Direct Memory Access Engine and Xilinx AXI
Central Direct Memory Access Engine and few updates to this driver
- new cyclic capability to sun6i and few updates
- slave-sg support in bcm2835
- updates to many drivers like designware, hsu, mv_xor, pxa, edma,
qcom_hidma & bam"
* tag 'dmaengine-4.7-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (84 commits)
dmaengine: ioatdma: disable relaxed ordering for ioatdma
dmaengine: of_dma: approximate an average distribution
dmaengine: core: Use IS_ENABLED() instead of checking for built-in or module
dmaengine: edma: Re-evaluate errors when ccerr is triggered w/o error event
dmaengine: qcom_hidma: add support for object hierarchy
dmaengine: qcom_hidma: add debugfs hooks
dmaengine: qcom_hidma: implement lower level hardware interface
dmaengine: vdma: Add clock support
Documentation: DT: vdma: Add clock support for dmas
dmaengine: vdma: Add config structure to differentiate dmas
MAINTAINERS: Update Tegra DMA maintainers
dmaengine: tegra-adma: Add support for Tegra210 ADMA
Documentation: DT: Add binding documentation for NVIDIA ADMA
dmaengine: vdma: Add Support for Xilinx AXI Central Direct Memory Access Engine
Documentation: DT: vdma: update binding doc for AXI CDMA
dmaengine: vdma: Add Support for Xilinx AXI Direct Memory Access Engine
Documentation: DT: vdma: update binding doc for AXI DMA
dmaengine: vdma: Rename xilinx_vdma_ prefix to xilinx_dma
dmaengine: slave means at least one of DMA_SLAVE, DMA_CYCLIC
dmaengine: mv_xor: Allow selecting mv_xor for mvebu only compatible SoC
...
Diffstat (limited to 'include/linux/platform_data')
| -rw-r--r-- | include/linux/platform_data/dma-dw.h | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/include/linux/platform_data/dma-dw.h b/include/linux/platform_data/dma-dw.h index 03b6095d3b18..d15d8ba8cc24 100644 --- a/include/linux/platform_data/dma-dw.h +++ b/include/linux/platform_data/dma-dw.h | |||
| @@ -21,15 +21,15 @@ | |||
| 21 | * @dma_dev: required DMA master device | 21 | * @dma_dev: required DMA master device |
| 22 | * @src_id: src request line | 22 | * @src_id: src request line |
| 23 | * @dst_id: dst request line | 23 | * @dst_id: dst request line |
| 24 | * @src_master: src master for transfers on allocated channel. | 24 | * @m_master: memory master for transfers on allocated channel |
| 25 | * @dst_master: dest master for transfers on allocated channel. | 25 | * @p_master: peripheral master for transfers on allocated channel |
| 26 | */ | 26 | */ |
| 27 | struct dw_dma_slave { | 27 | struct dw_dma_slave { |
| 28 | struct device *dma_dev; | 28 | struct device *dma_dev; |
| 29 | u8 src_id; | 29 | u8 src_id; |
| 30 | u8 dst_id; | 30 | u8 dst_id; |
| 31 | u8 src_master; | 31 | u8 m_master; |
| 32 | u8 dst_master; | 32 | u8 p_master; |
| 33 | }; | 33 | }; |
| 34 | 34 | ||
| 35 | /** | 35 | /** |
| @@ -43,7 +43,7 @@ struct dw_dma_slave { | |||
| 43 | * @block_size: Maximum block size supported by the controller | 43 | * @block_size: Maximum block size supported by the controller |
| 44 | * @nr_masters: Number of AHB masters supported by the controller | 44 | * @nr_masters: Number of AHB masters supported by the controller |
| 45 | * @data_width: Maximum data width supported by hardware per AHB master | 45 | * @data_width: Maximum data width supported by hardware per AHB master |
| 46 | * (0 - 8bits, 1 - 16bits, ..., 5 - 256bits) | 46 | * (in bytes, power of 2) |
| 47 | */ | 47 | */ |
| 48 | struct dw_dma_platform_data { | 48 | struct dw_dma_platform_data { |
| 49 | unsigned int nr_channels; | 49 | unsigned int nr_channels; |
| @@ -55,7 +55,7 @@ struct dw_dma_platform_data { | |||
| 55 | #define CHAN_PRIORITY_ASCENDING 0 /* chan0 highest */ | 55 | #define CHAN_PRIORITY_ASCENDING 0 /* chan0 highest */ |
| 56 | #define CHAN_PRIORITY_DESCENDING 1 /* chan7 highest */ | 56 | #define CHAN_PRIORITY_DESCENDING 1 /* chan7 highest */ |
| 57 | unsigned char chan_priority; | 57 | unsigned char chan_priority; |
| 58 | unsigned short block_size; | 58 | unsigned int block_size; |
| 59 | unsigned char nr_masters; | 59 | unsigned char nr_masters; |
| 60 | unsigned char data_width[DW_DMA_MAX_NR_MASTERS]; | 60 | unsigned char data_width[DW_DMA_MAX_NR_MASTERS]; |
| 61 | }; | 61 | }; |
