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authorSaeed Mahameed <saeedm@mellanox.com>2015-05-28 15:28:40 -0400
committerDavid S. Miller <davem@davemloft.net>2015-05-30 21:23:11 -0400
commite281682bf29438848daac11627216bceb1507b71 (patch)
tree98ed232873b05ca20f6d251514d5254c0e04a231 /include/linux/mlx5
parentdb058a186f98b057c19c42f7b10d9a96fd3b5d59 (diff)
net/mlx5_core: HW data structs/types definitions cleanup
mlx5_ifc.h was heavily modified here since it is now generated by a script from the device specification (PRM rev 0.25). This specification is backward compatible to existing hardware. Some structures/fields were added here in order to enable the Ethernet functionality of the driver. Signed-off-by: Saeed Mahameed <saeedm@mellanox.com> Signed-off-by: Amir Vadai <amirv@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'include/linux/mlx5')
-rw-r--r--include/linux/mlx5/device.h113
-rw-r--r--include/linux/mlx5/driver.h4
-rw-r--r--include/linux/mlx5/mlx5_ifc.h6570
-rw-r--r--include/linux/mlx5/qp.h25
4 files changed, 6631 insertions, 81 deletions
diff --git a/include/linux/mlx5/device.h b/include/linux/mlx5/device.h
index abf65c790421..feebed7b392b 100644
--- a/include/linux/mlx5/device.h
+++ b/include/linux/mlx5/device.h
@@ -35,6 +35,7 @@
35 35
36#include <linux/types.h> 36#include <linux/types.h>
37#include <rdma/ib_verbs.h> 37#include <rdma/ib_verbs.h>
38#include <linux/mlx5/mlx5_ifc.h>
38 39
39#if defined(__LITTLE_ENDIAN) 40#if defined(__LITTLE_ENDIAN)
40#define MLX5_SET_HOST_ENDIANNESS 0 41#define MLX5_SET_HOST_ENDIANNESS 0
@@ -70,6 +71,14 @@
70 << __mlx5_dw_bit_off(typ, fld))); \ 71 << __mlx5_dw_bit_off(typ, fld))); \
71} while (0) 72} while (0)
72 73
74#define MLX5_SET_TO_ONES(typ, p, fld) do { \
75 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
76 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
77 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
78 (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \
79 << __mlx5_dw_bit_off(typ, fld))); \
80} while (0)
81
73#define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\ 82#define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\
74__mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \ 83__mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
75__mlx5_mask(typ, fld)) 84__mlx5_mask(typ, fld))
@@ -264,6 +273,7 @@ enum {
264 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09, 273 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09,
265 MLX5_OPCODE_SEND = 0x0a, 274 MLX5_OPCODE_SEND = 0x0a,
266 MLX5_OPCODE_SEND_IMM = 0x0b, 275 MLX5_OPCODE_SEND_IMM = 0x0b,
276 MLX5_OPCODE_LSO = 0x0e,
267 MLX5_OPCODE_RDMA_READ = 0x10, 277 MLX5_OPCODE_RDMA_READ = 0x10,
268 MLX5_OPCODE_ATOMIC_CS = 0x11, 278 MLX5_OPCODE_ATOMIC_CS = 0x11,
269 MLX5_OPCODE_ATOMIC_FA = 0x12, 279 MLX5_OPCODE_ATOMIC_FA = 0x12,
@@ -541,6 +551,10 @@ struct mlx5_cmd_prot_block {
541 u8 sig; 551 u8 sig;
542}; 552};
543 553
554enum {
555 MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5,
556};
557
544struct mlx5_err_cqe { 558struct mlx5_err_cqe {
545 u8 rsvd0[32]; 559 u8 rsvd0[32];
546 __be32 srqn; 560 __be32 srqn;
@@ -554,13 +568,22 @@ struct mlx5_err_cqe {
554}; 568};
555 569
556struct mlx5_cqe64 { 570struct mlx5_cqe64 {
557 u8 rsvd0[17]; 571 u8 rsvd0[4];
572 u8 lro_tcppsh_abort_dupack;
573 u8 lro_min_ttl;
574 __be16 lro_tcp_win;
575 __be32 lro_ack_seq_num;
576 __be32 rss_hash_result;
577 u8 rss_hash_type;
558 u8 ml_path; 578 u8 ml_path;
559 u8 rsvd20[4]; 579 u8 rsvd20[2];
580 __be16 check_sum;
560 __be16 slid; 581 __be16 slid;
561 __be32 flags_rqpn; 582 __be32 flags_rqpn;
562 u8 rsvd28[4]; 583 u8 hds_ip_ext;
563 __be32 srqn; 584 u8 l4_hdr_type_etc;
585 __be16 vlan_info;
586 __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */
564 __be32 imm_inval_pkey; 587 __be32 imm_inval_pkey;
565 u8 rsvd40[4]; 588 u8 rsvd40[4];
566 __be32 byte_cnt; 589 __be32 byte_cnt;
@@ -571,6 +594,40 @@ struct mlx5_cqe64 {
571 u8 op_own; 594 u8 op_own;
572}; 595};
573 596
597static inline int get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe)
598{
599 return (cqe->lro_tcppsh_abort_dupack >> 6) & 1;
600}
601
602static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe)
603{
604 return (cqe->l4_hdr_type_etc >> 4) & 0x7;
605}
606
607static inline int cqe_has_vlan(struct mlx5_cqe64 *cqe)
608{
609 return !!(cqe->l4_hdr_type_etc & 0x1);
610}
611
612enum {
613 CQE_L4_HDR_TYPE_NONE = 0x0,
614 CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1,
615 CQE_L4_HDR_TYPE_UDP = 0x2,
616 CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3,
617 CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4,
618};
619
620enum {
621 CQE_RSS_HTYPE_IP = 0x3 << 6,
622 CQE_RSS_HTYPE_L4 = 0x3 << 2,
623};
624
625enum {
626 CQE_L2_OK = 1 << 0,
627 CQE_L3_OK = 1 << 1,
628 CQE_L4_OK = 1 << 2,
629};
630
574struct mlx5_sig_err_cqe { 631struct mlx5_sig_err_cqe {
575 u8 rsvd0[16]; 632 u8 rsvd0[16];
576 __be32 expected_trans_sig; 633 __be32 expected_trans_sig;
@@ -996,4 +1053,52 @@ struct mlx5_destroy_psv_out {
996 u8 rsvd[8]; 1053 u8 rsvd[8];
997}; 1054};
998 1055
1056#define MLX5_CMD_OP_MAX 0x920
1057
1058enum {
1059 VPORT_STATE_DOWN = 0x0,
1060 VPORT_STATE_UP = 0x1,
1061};
1062
1063enum {
1064 MLX5_L3_PROT_TYPE_IPV4 = 0,
1065 MLX5_L3_PROT_TYPE_IPV6 = 1,
1066};
1067
1068enum {
1069 MLX5_L4_PROT_TYPE_TCP = 0,
1070 MLX5_L4_PROT_TYPE_UDP = 1,
1071};
1072
1073enum {
1074 MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0,
1075 MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1,
1076 MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2,
1077 MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3,
1078 MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4,
1079};
1080
1081enum {
1082 MLX5_MATCH_OUTER_HEADERS = 1 << 0,
1083 MLX5_MATCH_MISC_PARAMETERS = 1 << 1,
1084 MLX5_MATCH_INNER_HEADERS = 1 << 2,
1085
1086};
1087
1088enum {
1089 MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0,
1090 MLX5_FLOW_TABLE_TYPE_ESWITCH = 4,
1091};
1092
1093enum {
1094 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0,
1095 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 1,
1096 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 2,
1097};
1098
1099enum {
1100 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
1101 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM = 0x1,
1102};
1103
999#endif /* MLX5_DEVICE_H */ 1104#endif /* MLX5_DEVICE_H */
diff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h
index 9e8979502826..3fd4fdc1ba16 100644
--- a/include/linux/mlx5/driver.h
+++ b/include/linux/mlx5/driver.h
@@ -44,7 +44,6 @@
44 44
45#include <linux/mlx5/device.h> 45#include <linux/mlx5/device.h>
46#include <linux/mlx5/doorbell.h> 46#include <linux/mlx5/doorbell.h>
47#include <linux/mlx5/mlx5_ifc.h>
48 47
49enum { 48enum {
50 MLX5_BOARD_ID_LEN = 64, 49 MLX5_BOARD_ID_LEN = 64,
@@ -278,7 +277,6 @@ struct mlx5_general_caps {
278 u8 log_max_mkey; 277 u8 log_max_mkey;
279 u8 log_max_pd; 278 u8 log_max_pd;
280 u8 log_max_srq; 279 u8 log_max_srq;
281 u8 log_max_strq;
282 u8 log_max_mrw_sz; 280 u8 log_max_mrw_sz;
283 u8 log_max_bsf_list_size; 281 u8 log_max_bsf_list_size;
284 u8 log_max_klm_list_size; 282 u8 log_max_klm_list_size;
@@ -664,6 +662,8 @@ int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
664int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn); 662int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
665int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari); 663int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
666int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari); 664int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
665int mlx5_alloc_map_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar);
666void mlx5_unmap_free_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar);
667void mlx5_health_cleanup(void); 667void mlx5_health_cleanup(void);
668void __init mlx5_health_init(void); 668void __init mlx5_health_init(void);
669void mlx5_start_health_poll(struct mlx5_core_dev *dev); 669void mlx5_start_health_poll(struct mlx5_core_dev *dev);
diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h
index cb3ad17edd1f..b27e9f6e090a 100644
--- a/include/linux/mlx5/mlx5_ifc.h
+++ b/include/linux/mlx5/mlx5_ifc.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
3 * 3 *
4 * This software is available to you under a choice of one of two 4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU 5 * licenses. You may choose to be licensed under the terms of the GNU
@@ -28,12 +28,45 @@
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE. 30 * SOFTWARE.
31 */ 31*/
32
33#ifndef MLX5_IFC_H 32#ifndef MLX5_IFC_H
34#define MLX5_IFC_H 33#define MLX5_IFC_H
35 34
36enum { 35enum {
36 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
37 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
38 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
39 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
40 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
41 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
42 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
43 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
44 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
45 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
46 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
47 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
48 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
49 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
50 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
51 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
52 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
53 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
54 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
55 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
56 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
57 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
58 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
59 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb
60};
61
62enum {
63 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
64 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
65 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
66 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
67};
68
69enum {
37 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 70 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
38 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 71 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
39 MLX5_CMD_OP_INIT_HCA = 0x102, 72 MLX5_CMD_OP_INIT_HCA = 0x102,
@@ -43,6 +76,8 @@ enum {
43 MLX5_CMD_OP_QUERY_PAGES = 0x107, 76 MLX5_CMD_OP_QUERY_PAGES = 0x107,
44 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 77 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
45 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 78 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
79 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
80 MLX5_CMD_OP_SET_ISSI = 0x10b,
46 MLX5_CMD_OP_CREATE_MKEY = 0x200, 81 MLX5_CMD_OP_CREATE_MKEY = 0x200,
47 MLX5_CMD_OP_QUERY_MKEY = 0x201, 82 MLX5_CMD_OP_QUERY_MKEY = 0x201,
48 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 83 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
@@ -66,6 +101,7 @@ enum {
66 MLX5_CMD_OP_2ERR_QP = 0x507, 101 MLX5_CMD_OP_2ERR_QP = 0x507,
67 MLX5_CMD_OP_2RST_QP = 0x50a, 102 MLX5_CMD_OP_2RST_QP = 0x50a,
68 MLX5_CMD_OP_QUERY_QP = 0x50b, 103 MLX5_CMD_OP_QUERY_QP = 0x50b,
104 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
69 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 105 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
70 MLX5_CMD_OP_CREATE_PSV = 0x600, 106 MLX5_CMD_OP_CREATE_PSV = 0x600,
71 MLX5_CMD_OP_DESTROY_PSV = 0x601, 107 MLX5_CMD_OP_DESTROY_PSV = 0x601,
@@ -73,7 +109,10 @@ enum {
73 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 109 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
74 MLX5_CMD_OP_QUERY_SRQ = 0x702, 110 MLX5_CMD_OP_QUERY_SRQ = 0x702,
75 MLX5_CMD_OP_ARM_RQ = 0x703, 111 MLX5_CMD_OP_ARM_RQ = 0x703,
76 MLX5_CMD_OP_RESIZE_SRQ = 0x704, 112 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
113 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
114 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
115 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
77 MLX5_CMD_OP_CREATE_DCT = 0x710, 116 MLX5_CMD_OP_CREATE_DCT = 0x710,
78 MLX5_CMD_OP_DESTROY_DCT = 0x711, 117 MLX5_CMD_OP_DESTROY_DCT = 0x711,
79 MLX5_CMD_OP_DRAIN_DCT = 0x712, 118 MLX5_CMD_OP_DRAIN_DCT = 0x712,
@@ -85,8 +124,12 @@ enum {
85 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 124 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
86 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 125 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
87 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 126 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
88 MLX5_CMD_OP_QUERY_RCOE_ADDRESS = 0x760, 127 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
89 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 128 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
129 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
130 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
131 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
132 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
90 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 133 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
91 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 134 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
92 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 135 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
@@ -98,7 +141,7 @@ enum {
98 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 141 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
99 MLX5_CMD_OP_ACCESS_REG = 0x805, 142 MLX5_CMD_OP_ACCESS_REG = 0x805,
100 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 143 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
101 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 144 MLX5_CMD_OP_DETTACH_FROM_MCG = 0x807,
102 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 145 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
103 MLX5_CMD_OP_MAD_IFC = 0x50d, 146 MLX5_CMD_OP_MAD_IFC = 0x50d,
104 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 147 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
@@ -106,23 +149,22 @@ enum {
106 MLX5_CMD_OP_NOP = 0x80d, 149 MLX5_CMD_OP_NOP = 0x80d,
107 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 150 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
108 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 151 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
109 MLX5_CMD_OP_SET_BURST_SIZE = 0x812, 152 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
110 MLX5_CMD_OP_QUERY_BURST_SZIE = 0x813, 153 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
111 MLX5_CMD_OP_ACTIVATE_TRACER = 0x814, 154 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
112 MLX5_CMD_OP_DEACTIVATE_TRACER = 0x815, 155 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
113 MLX5_CMD_OP_CREATE_SNIFFER_RULE = 0x820, 156 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
114 MLX5_CMD_OP_DESTROY_SNIFFER_RULE = 0x821, 157 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
115 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x822, 158 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
116 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x823, 159 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
117 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x824, 160 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
161 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
162 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
163 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
118 MLX5_CMD_OP_CREATE_TIR = 0x900, 164 MLX5_CMD_OP_CREATE_TIR = 0x900,
119 MLX5_CMD_OP_MODIFY_TIR = 0x901, 165 MLX5_CMD_OP_MODIFY_TIR = 0x901,
120 MLX5_CMD_OP_DESTROY_TIR = 0x902, 166 MLX5_CMD_OP_DESTROY_TIR = 0x902,
121 MLX5_CMD_OP_QUERY_TIR = 0x903, 167 MLX5_CMD_OP_QUERY_TIR = 0x903,
122 MLX5_CMD_OP_CREATE_TIS = 0x912,
123 MLX5_CMD_OP_MODIFY_TIS = 0x913,
124 MLX5_CMD_OP_DESTROY_TIS = 0x914,
125 MLX5_CMD_OP_QUERY_TIS = 0x915,
126 MLX5_CMD_OP_CREATE_SQ = 0x904, 168 MLX5_CMD_OP_CREATE_SQ = 0x904,
127 MLX5_CMD_OP_MODIFY_SQ = 0x905, 169 MLX5_CMD_OP_MODIFY_SQ = 0x905,
128 MLX5_CMD_OP_DESTROY_SQ = 0x906, 170 MLX5_CMD_OP_DESTROY_SQ = 0x906,
@@ -135,9 +177,430 @@ enum {
135 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 177 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
136 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 178 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
137 MLX5_CMD_OP_QUERY_RMP = 0x90f, 179 MLX5_CMD_OP_QUERY_RMP = 0x90f,
138 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x910, 180 MLX5_CMD_OP_CREATE_TIS = 0x912,
139 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x911, 181 MLX5_CMD_OP_MODIFY_TIS = 0x913,
140 MLX5_CMD_OP_MAX = 0x911 182 MLX5_CMD_OP_DESTROY_TIS = 0x914,
183 MLX5_CMD_OP_QUERY_TIS = 0x915,
184 MLX5_CMD_OP_CREATE_RQT = 0x916,
185 MLX5_CMD_OP_MODIFY_RQT = 0x917,
186 MLX5_CMD_OP_DESTROY_RQT = 0x918,
187 MLX5_CMD_OP_QUERY_RQT = 0x919,
188 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
189 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
190 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
191 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
192 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
193 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
194 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
195 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
196 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938
197};
198
199struct mlx5_ifc_flow_table_fields_supported_bits {
200 u8 outer_dmac[0x1];
201 u8 outer_smac[0x1];
202 u8 outer_ether_type[0x1];
203 u8 reserved_0[0x1];
204 u8 outer_first_prio[0x1];
205 u8 outer_first_cfi[0x1];
206 u8 outer_first_vid[0x1];
207 u8 reserved_1[0x1];
208 u8 outer_second_prio[0x1];
209 u8 outer_second_cfi[0x1];
210 u8 outer_second_vid[0x1];
211 u8 reserved_2[0x1];
212 u8 outer_sip[0x1];
213 u8 outer_dip[0x1];
214 u8 outer_frag[0x1];
215 u8 outer_ip_protocol[0x1];
216 u8 outer_ip_ecn[0x1];
217 u8 outer_ip_dscp[0x1];
218 u8 outer_udp_sport[0x1];
219 u8 outer_udp_dport[0x1];
220 u8 outer_tcp_sport[0x1];
221 u8 outer_tcp_dport[0x1];
222 u8 outer_tcp_flags[0x1];
223 u8 outer_gre_protocol[0x1];
224 u8 outer_gre_key[0x1];
225 u8 outer_vxlan_vni[0x1];
226 u8 reserved_3[0x5];
227 u8 source_eswitch_port[0x1];
228
229 u8 inner_dmac[0x1];
230 u8 inner_smac[0x1];
231 u8 inner_ether_type[0x1];
232 u8 reserved_4[0x1];
233 u8 inner_first_prio[0x1];
234 u8 inner_first_cfi[0x1];
235 u8 inner_first_vid[0x1];
236 u8 reserved_5[0x1];
237 u8 inner_second_prio[0x1];
238 u8 inner_second_cfi[0x1];
239 u8 inner_second_vid[0x1];
240 u8 reserved_6[0x1];
241 u8 inner_sip[0x1];
242 u8 inner_dip[0x1];
243 u8 inner_frag[0x1];
244 u8 inner_ip_protocol[0x1];
245 u8 inner_ip_ecn[0x1];
246 u8 inner_ip_dscp[0x1];
247 u8 inner_udp_sport[0x1];
248 u8 inner_udp_dport[0x1];
249 u8 inner_tcp_sport[0x1];
250 u8 inner_tcp_dport[0x1];
251 u8 inner_tcp_flags[0x1];
252 u8 reserved_7[0x9];
253
254 u8 reserved_8[0x40];
255};
256
257struct mlx5_ifc_flow_table_prop_layout_bits {
258 u8 ft_support[0x1];
259 u8 reserved_0[0x1f];
260
261 u8 reserved_1[0x2];
262 u8 log_max_ft_size[0x6];
263 u8 reserved_2[0x10];
264 u8 max_ft_level[0x8];
265
266 u8 reserved_3[0x20];
267
268 u8 reserved_4[0x18];
269 u8 log_max_ft_num[0x8];
270
271 u8 reserved_5[0x18];
272 u8 log_max_destination[0x8];
273
274 u8 reserved_6[0x18];
275 u8 log_max_flow[0x8];
276
277 u8 reserved_7[0x40];
278
279 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
280
281 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
282};
283
284struct mlx5_ifc_odp_per_transport_service_cap_bits {
285 u8 send[0x1];
286 u8 receive[0x1];
287 u8 write[0x1];
288 u8 read[0x1];
289 u8 reserved_0[0x1];
290 u8 srq_receive[0x1];
291 u8 reserved_1[0x1a];
292};
293
294struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
295 u8 smac_47_16[0x20];
296
297 u8 smac_15_0[0x10];
298 u8 ethertype[0x10];
299
300 u8 dmac_47_16[0x20];
301
302 u8 dmac_15_0[0x10];
303 u8 first_prio[0x3];
304 u8 first_cfi[0x1];
305 u8 first_vid[0xc];
306
307 u8 ip_protocol[0x8];
308 u8 ip_dscp[0x6];
309 u8 ip_ecn[0x2];
310 u8 vlan_tag[0x1];
311 u8 reserved_0[0x1];
312 u8 frag[0x1];
313 u8 reserved_1[0x4];
314 u8 tcp_flags[0x9];
315
316 u8 tcp_sport[0x10];
317 u8 tcp_dport[0x10];
318
319 u8 reserved_2[0x20];
320
321 u8 udp_sport[0x10];
322 u8 udp_dport[0x10];
323
324 u8 src_ip[4][0x20];
325
326 u8 dst_ip[4][0x20];
327};
328
329struct mlx5_ifc_fte_match_set_misc_bits {
330 u8 reserved_0[0x20];
331
332 u8 reserved_1[0x10];
333 u8 source_port[0x10];
334
335 u8 outer_second_prio[0x3];
336 u8 outer_second_cfi[0x1];
337 u8 outer_second_vid[0xc];
338 u8 inner_second_prio[0x3];
339 u8 inner_second_cfi[0x1];
340 u8 inner_second_vid[0xc];
341
342 u8 outer_second_vlan_tag[0x1];
343 u8 inner_second_vlan_tag[0x1];
344 u8 reserved_2[0xe];
345 u8 gre_protocol[0x10];
346
347 u8 gre_key_h[0x18];
348 u8 gre_key_l[0x8];
349
350 u8 vxlan_vni[0x18];
351 u8 reserved_3[0x8];
352
353 u8 reserved_4[0x20];
354
355 u8 reserved_5[0xc];
356 u8 outer_ipv6_flow_label[0x14];
357
358 u8 reserved_6[0xc];
359 u8 inner_ipv6_flow_label[0x14];
360
361 u8 reserved_7[0xe0];
362};
363
364struct mlx5_ifc_cmd_pas_bits {
365 u8 pa_h[0x20];
366
367 u8 pa_l[0x14];
368 u8 reserved_0[0xc];
369};
370
371struct mlx5_ifc_uint64_bits {
372 u8 hi[0x20];
373
374 u8 lo[0x20];
375};
376
377enum {
378 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
379 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
380 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
381 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
382 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
383 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
384 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
385 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
386 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
387 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
388};
389
390struct mlx5_ifc_ads_bits {
391 u8 fl[0x1];
392 u8 free_ar[0x1];
393 u8 reserved_0[0xe];
394 u8 pkey_index[0x10];
395
396 u8 reserved_1[0x8];
397 u8 grh[0x1];
398 u8 mlid[0x7];
399 u8 rlid[0x10];
400
401 u8 ack_timeout[0x5];
402 u8 reserved_2[0x3];
403 u8 src_addr_index[0x8];
404 u8 reserved_3[0x4];
405 u8 stat_rate[0x4];
406 u8 hop_limit[0x8];
407
408 u8 reserved_4[0x4];
409 u8 tclass[0x8];
410 u8 flow_label[0x14];
411
412 u8 rgid_rip[16][0x8];
413
414 u8 reserved_5[0x4];
415 u8 f_dscp[0x1];
416 u8 f_ecn[0x1];
417 u8 reserved_6[0x1];
418 u8 f_eth_prio[0x1];
419 u8 ecn[0x2];
420 u8 dscp[0x6];
421 u8 udp_sport[0x10];
422
423 u8 dei_cfi[0x1];
424 u8 eth_prio[0x3];
425 u8 sl[0x4];
426 u8 port[0x8];
427 u8 rmac_47_32[0x10];
428
429 u8 rmac_31_0[0x20];
430};
431
432struct mlx5_ifc_flow_table_nic_cap_bits {
433 u8 reserved_0[0x200];
434
435 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
436
437 u8 reserved_1[0x200];
438
439 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
440
441 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
442
443 u8 reserved_2[0x200];
444
445 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
446
447 u8 reserved_3[0x7200];
448};
449
450struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
451 u8 csum_cap[0x1];
452 u8 vlan_cap[0x1];
453 u8 lro_cap[0x1];
454 u8 lro_psh_flag[0x1];
455 u8 lro_time_stamp[0x1];
456 u8 reserved_0[0x6];
457 u8 max_lso_cap[0x5];
458 u8 reserved_1[0x4];
459 u8 rss_ind_tbl_cap[0x4];
460 u8 reserved_2[0x3];
461 u8 tunnel_lso_const_out_ip_id[0x1];
462 u8 reserved_3[0x2];
463 u8 tunnel_statless_gre[0x1];
464 u8 tunnel_stateless_vxlan[0x1];
465
466 u8 reserved_4[0x20];
467
468 u8 reserved_5[0x10];
469 u8 lro_min_mss_size[0x10];
470
471 u8 reserved_6[0x120];
472
473 u8 lro_timer_supported_periods[4][0x20];
474
475 u8 reserved_7[0x600];
476};
477
478struct mlx5_ifc_roce_cap_bits {
479 u8 roce_apm[0x1];
480 u8 reserved_0[0x1f];
481
482 u8 reserved_1[0x60];
483
484 u8 reserved_2[0xc];
485 u8 l3_type[0x4];
486 u8 reserved_3[0x8];
487 u8 roce_version[0x8];
488
489 u8 reserved_4[0x10];
490 u8 r_roce_dest_udp_port[0x10];
491
492 u8 r_roce_max_src_udp_port[0x10];
493 u8 r_roce_min_src_udp_port[0x10];
494
495 u8 reserved_5[0x10];
496 u8 roce_address_table_size[0x10];
497
498 u8 reserved_6[0x700];
499};
500
501enum {
502 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
503 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
504 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
505 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
506 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
507 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
508 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
509 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
510 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
511};
512
513enum {
514 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
515 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
516 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
517 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
518 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
519 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
520 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
521 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
522 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
523};
524
525struct mlx5_ifc_atomic_caps_bits {
526 u8 reserved_0[0x40];
527
528 u8 atomic_req_endianness[0x1];
529 u8 reserved_1[0x1f];
530
531 u8 reserved_2[0x20];
532
533 u8 reserved_3[0x10];
534 u8 atomic_operations[0x10];
535
536 u8 reserved_4[0x10];
537 u8 atomic_size_qp[0x10];
538
539 u8 reserved_5[0x10];
540 u8 atomic_size_dc[0x10];
541
542 u8 reserved_6[0x720];
543};
544
545struct mlx5_ifc_odp_cap_bits {
546 u8 reserved_0[0x40];
547
548 u8 sig[0x1];
549 u8 reserved_1[0x1f];
550
551 u8 reserved_2[0x20];
552
553 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
554
555 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
556
557 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
558
559 u8 reserved_3[0x720];
560};
561
562enum {
563 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
564 MLX5_WQ_TYPE_CYCLIC = 0x1,
565 MLX5_WQ_TYPE_STRQ = 0x2,
566};
567
568enum {
569 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
570 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
571};
572
573enum {
574 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
575 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
576 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
577 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
578 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
579};
580
581enum {
582 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
583 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
584 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
585 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
586 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
587 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
588};
589
590enum {
591 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
592 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
593};
594
595enum {
596 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
597 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
598 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
599};
600
601enum {
602 MLX5_CAP_PORT_TYPE_IB = 0x0,
603 MLX5_CAP_PORT_TYPE_ETH = 0x1,
141}; 604};
142 605
143struct mlx5_ifc_cmd_hca_cap_bits { 606struct mlx5_ifc_cmd_hca_cap_bits {
@@ -148,9 +611,8 @@ struct mlx5_ifc_cmd_hca_cap_bits {
148 u8 reserved_1[0xb]; 611 u8 reserved_1[0xb];
149 u8 log_max_qp[0x5]; 612 u8 log_max_qp[0x5];
150 613
151 u8 log_max_strq_sz[0x8]; 614 u8 reserved_2[0xb];
152 u8 reserved_2[0x3]; 615 u8 log_max_srq[0x5];
153 u8 log_max_srqs[0x5];
154 u8 reserved_3[0x10]; 616 u8 reserved_3[0x10];
155 617
156 u8 reserved_4[0x8]; 618 u8 reserved_4[0x8];
@@ -185,123 +647,2109 @@ struct mlx5_ifc_cmd_hca_cap_bits {
185 u8 pad_cap[0x1]; 647 u8 pad_cap[0x1];
186 u8 cc_query_allowed[0x1]; 648 u8 cc_query_allowed[0x1];
187 u8 cc_modify_allowed[0x1]; 649 u8 cc_modify_allowed[0x1];
188 u8 reserved_15[0x1d]; 650 u8 reserved_15[0xd];
651 u8 gid_table_size[0x10];
189 652
190 u8 reserved_16[0x6]; 653 u8 out_of_seq_cnt[0x1];
654 u8 vport_counters[0x1];
655 u8 reserved_16[0x4];
191 u8 max_qp_cnt[0xa]; 656 u8 max_qp_cnt[0xa];
192 u8 pkey_table_size[0x10]; 657 u8 pkey_table_size[0x10];
193 658
194 u8 eswitch_owner[0x1]; 659 u8 vport_group_manager[0x1];
195 u8 reserved_17[0xa]; 660 u8 vhca_group_manager[0x1];
661 u8 ib_virt[0x1];
662 u8 eth_virt[0x1];
663 u8 reserved_17[0x1];
664 u8 ets[0x1];
665 u8 nic_flow_table[0x1];
666 u8 reserved_18[0x4];
196 u8 local_ca_ack_delay[0x5]; 667 u8 local_ca_ack_delay[0x5];
197 u8 reserved_18[0x8]; 668 u8 reserved_19[0x6];
669 u8 port_type[0x2];
198 u8 num_ports[0x8]; 670 u8 num_ports[0x8];
199 671
200 u8 reserved_19[0x3]; 672 u8 reserved_20[0x3];
201 u8 log_max_msg[0x5]; 673 u8 log_max_msg[0x5];
202 u8 reserved_20[0x18]; 674 u8 reserved_21[0x18];
203 675
204 u8 stat_rate_support[0x10]; 676 u8 stat_rate_support[0x10];
205 u8 reserved_21[0x10]; 677 u8 reserved_22[0xc];
678 u8 cqe_version[0x4];
206 679
207 u8 reserved_22[0x10]; 680 u8 compact_address_vector[0x1];
681 u8 reserved_23[0xe];
682 u8 drain_sigerr[0x1];
208 u8 cmdif_checksum[0x2]; 683 u8 cmdif_checksum[0x2];
209 u8 sigerr_cqe[0x1]; 684 u8 sigerr_cqe[0x1];
210 u8 reserved_23[0x1]; 685 u8 reserved_24[0x1];
211 u8 wq_signature[0x1]; 686 u8 wq_signature[0x1];
212 u8 sctr_data_cqe[0x1]; 687 u8 sctr_data_cqe[0x1];
213 u8 reserved_24[0x1]; 688 u8 reserved_25[0x1];
214 u8 sho[0x1]; 689 u8 sho[0x1];
215 u8 tph[0x1]; 690 u8 tph[0x1];
216 u8 rf[0x1]; 691 u8 rf[0x1];
217 u8 dc[0x1]; 692 u8 dct[0x1];
218 u8 reserved_25[0x2]; 693 u8 reserved_26[0x1];
694 u8 eth_net_offloads[0x1];
219 u8 roce[0x1]; 695 u8 roce[0x1];
220 u8 atomic[0x1]; 696 u8 atomic[0x1];
221 u8 rsz_srq[0x1]; 697 u8 reserved_27[0x1];
222 698
223 u8 cq_oi[0x1]; 699 u8 cq_oi[0x1];
224 u8 cq_resize[0x1]; 700 u8 cq_resize[0x1];
225 u8 cq_moderation[0x1]; 701 u8 cq_moderation[0x1];
226 u8 sniffer_rule_flow[0x1]; 702 u8 reserved_28[0x3];
227 u8 sniffer_rule_vport[0x1]; 703 u8 cq_eq_remap[0x1];
228 u8 sniffer_rule_phy[0x1];
229 u8 reserved_26[0x1];
230 u8 pg[0x1]; 704 u8 pg[0x1];
231 u8 block_lb_mc[0x1]; 705 u8 block_lb_mc[0x1];
232 u8 reserved_27[0x3]; 706 u8 reserved_29[0x1];
707 u8 scqe_break_moderation[0x1];
708 u8 reserved_30[0x1];
233 u8 cd[0x1]; 709 u8 cd[0x1];
234 u8 reserved_28[0x1]; 710 u8 reserved_31[0x1];
235 u8 apm[0x1]; 711 u8 apm[0x1];
236 u8 reserved_29[0x7]; 712 u8 reserved_32[0x7];
237 u8 qkv[0x1]; 713 u8 qkv[0x1];
238 u8 pkv[0x1]; 714 u8 pkv[0x1];
239 u8 reserved_30[0x4]; 715 u8 reserved_33[0x4];
240 u8 xrc[0x1]; 716 u8 xrc[0x1];
241 u8 ud[0x1]; 717 u8 ud[0x1];
242 u8 uc[0x1]; 718 u8 uc[0x1];
243 u8 rc[0x1]; 719 u8 rc[0x1];
244 720
245 u8 reserved_31[0xa]; 721 u8 reserved_34[0xa];
246 u8 uar_sz[0x6]; 722 u8 uar_sz[0x6];
247 u8 reserved_32[0x8]; 723 u8 reserved_35[0x8];
248 u8 log_pg_sz[0x8]; 724 u8 log_pg_sz[0x8];
249 725
250 u8 bf[0x1]; 726 u8 bf[0x1];
251 u8 reserved_33[0xa]; 727 u8 reserved_36[0x1];
728 u8 pad_tx_eth_packet[0x1];
729 u8 reserved_37[0x8];
252 u8 log_bf_reg_size[0x5]; 730 u8 log_bf_reg_size[0x5];
253 u8 reserved_34[0x10]; 731 u8 reserved_38[0x10];
254 732
255 u8 reserved_35[0x10]; 733 u8 reserved_39[0x10];
256 u8 max_wqe_sz_sq[0x10]; 734 u8 max_wqe_sz_sq[0x10];
257 735
258 u8 reserved_36[0x10]; 736 u8 reserved_40[0x10];
259 u8 max_wqe_sz_rq[0x10]; 737 u8 max_wqe_sz_rq[0x10];
260 738
261 u8 reserved_37[0x10]; 739 u8 reserved_41[0x10];
262 u8 max_wqe_sz_sq_dc[0x10]; 740 u8 max_wqe_sz_sq_dc[0x10];
263 741
264 u8 reserved_38[0x7]; 742 u8 reserved_42[0x7];
265 u8 max_qp_mcg[0x19]; 743 u8 max_qp_mcg[0x19];
266 744
267 u8 reserved_39[0x18]; 745 u8 reserved_43[0x18];
268 u8 log_max_mcg[0x8]; 746 u8 log_max_mcg[0x8];
269 747
270 u8 reserved_40[0xb]; 748 u8 reserved_44[0x3];
749 u8 log_max_transport_domain[0x5];
750 u8 reserved_45[0x3];
271 u8 log_max_pd[0x5]; 751 u8 log_max_pd[0x5];
272 u8 reserved_41[0xb]; 752 u8 reserved_46[0xb];
273 u8 log_max_xrcd[0x5]; 753 u8 log_max_xrcd[0x5];
274 754
275 u8 reserved_42[0x20]; 755 u8 reserved_47[0x20];
276 756
277 u8 reserved_43[0x3]; 757 u8 reserved_48[0x3];
278 u8 log_max_rq[0x5]; 758 u8 log_max_rq[0x5];
279 u8 reserved_44[0x3]; 759 u8 reserved_49[0x3];
280 u8 log_max_sq[0x5]; 760 u8 log_max_sq[0x5];
281 u8 reserved_45[0x3]; 761 u8 reserved_50[0x3];
282 u8 log_max_tir[0x5]; 762 u8 log_max_tir[0x5];
283 u8 reserved_46[0x3]; 763 u8 reserved_51[0x3];
284 u8 log_max_tis[0x5]; 764 u8 log_max_tis[0x5];
285 765
286 u8 reserved_47[0x13]; 766 u8 basic_cyclic_rcv_wqe[0x1];
287 u8 log_max_rq_per_tir[0x5]; 767 u8 reserved_52[0x2];
288 u8 reserved_48[0x3]; 768 u8 log_max_rmp[0x5];
769 u8 reserved_53[0x3];
770 u8 log_max_rqt[0x5];
771 u8 reserved_54[0x3];
772 u8 log_max_rqt_size[0x5];
773 u8 reserved_55[0x3];
289 u8 log_max_tis_per_sq[0x5]; 774 u8 log_max_tis_per_sq[0x5];
290 775
291 u8 reserved_49[0xe0]; 776 u8 reserved_56[0x3];
777 u8 log_max_stride_sz_rq[0x5];
778 u8 reserved_57[0x3];
779 u8 log_min_stride_sz_rq[0x5];
780 u8 reserved_58[0x3];
781 u8 log_max_stride_sz_sq[0x5];
782 u8 reserved_59[0x3];
783 u8 log_min_stride_sz_sq[0x5];
292 784
293 u8 reserved_50[0x10]; 785 u8 reserved_60[0x1b];
786 u8 log_max_wq_sz[0x5];
787
788 u8 reserved_61[0xa0];
789
790 u8 reserved_62[0x3];
791 u8 log_max_l2_table[0x5];
792 u8 reserved_63[0x8];
294 u8 log_uar_page_sz[0x10]; 793 u8 log_uar_page_sz[0x10];
295 794
296 u8 reserved_51[0x100]; 795 u8 reserved_64[0x100];
297 796
298 u8 reserved_52[0x1f]; 797 u8 reserved_65[0x1f];
299 u8 cqe_zip[0x1]; 798 u8 cqe_zip[0x1];
300 799
301 u8 cqe_zip_timeout[0x10]; 800 u8 cqe_zip_timeout[0x10];
302 u8 cqe_zip_max_num[0x10]; 801 u8 cqe_zip_max_num[0x10];
303 802
304 u8 reserved_53[0x220]; 803 u8 reserved_66[0x220];
804};
805
806enum {
807 MLX5_DEST_FORMAT_STRUCT_DESTINATION_TYPE_FLOW_TABLE_ = 0x1,
808 MLX5_DEST_FORMAT_STRUCT_DESTINATION_TYPE_TIR = 0x2,
809};
810
811struct mlx5_ifc_dest_format_struct_bits {
812 u8 destination_type[0x8];
813 u8 destination_id[0x18];
814
815 u8 reserved_0[0x20];
816};
817
818struct mlx5_ifc_fte_match_param_bits {
819 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
820
821 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
822
823 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
824
825 u8 reserved_0[0xa00];
826};
827
828enum {
829 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
830 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
831 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
832 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
833 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
834};
835
836struct mlx5_ifc_rx_hash_field_select_bits {
837 u8 l3_prot_type[0x1];
838 u8 l4_prot_type[0x1];
839 u8 selected_fields[0x1e];
840};
841
842enum {
843 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
844 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
845};
846
847enum {
848 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
849 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
850};
851
852struct mlx5_ifc_wq_bits {
853 u8 wq_type[0x4];
854 u8 wq_signature[0x1];
855 u8 end_padding_mode[0x2];
856 u8 cd_slave[0x1];
857 u8 reserved_0[0x18];
858
859 u8 hds_skip_first_sge[0x1];
860 u8 log2_hds_buf_size[0x3];
861 u8 reserved_1[0x7];
862 u8 page_offset[0x5];
863 u8 lwm[0x10];
864
865 u8 reserved_2[0x8];
866 u8 pd[0x18];
867
868 u8 reserved_3[0x8];
869 u8 uar_page[0x18];
870
871 u8 dbr_addr[0x40];
872
873 u8 hw_counter[0x20];
874
875 u8 sw_counter[0x20];
876
877 u8 reserved_4[0xc];
878 u8 log_wq_stride[0x4];
879 u8 reserved_5[0x3];
880 u8 log_wq_pg_sz[0x5];
881 u8 reserved_6[0x3];
882 u8 log_wq_sz[0x5];
883
884 u8 reserved_7[0x4e0];
885
886 struct mlx5_ifc_cmd_pas_bits pas[0];
887};
888
889struct mlx5_ifc_rq_num_bits {
890 u8 reserved_0[0x8];
891 u8 rq_num[0x18];
892};
893
894struct mlx5_ifc_mac_address_layout_bits {
895 u8 reserved_0[0x10];
896 u8 mac_addr_47_32[0x10];
897
898 u8 mac_addr_31_0[0x20];
899};
900
901struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
902 u8 reserved_0[0xa0];
903
904 u8 min_time_between_cnps[0x20];
905
906 u8 reserved_1[0x12];
907 u8 cnp_dscp[0x6];
908 u8 reserved_2[0x5];
909 u8 cnp_802p_prio[0x3];
910
911 u8 reserved_3[0x720];
912};
913
914struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
915 u8 reserved_0[0x60];
916
917 u8 reserved_1[0x4];
918 u8 clamp_tgt_rate[0x1];
919 u8 reserved_2[0x3];
920 u8 clamp_tgt_rate_after_time_inc[0x1];
921 u8 reserved_3[0x17];
922
923 u8 reserved_4[0x20];
924
925 u8 rpg_time_reset[0x20];
926
927 u8 rpg_byte_reset[0x20];
928
929 u8 rpg_threshold[0x20];
930
931 u8 rpg_max_rate[0x20];
932
933 u8 rpg_ai_rate[0x20];
934
935 u8 rpg_hai_rate[0x20];
936
937 u8 rpg_gd[0x20];
938
939 u8 rpg_min_dec_fac[0x20];
940
941 u8 rpg_min_rate[0x20];
942
943 u8 reserved_5[0xe0];
944
945 u8 rate_to_set_on_first_cnp[0x20];
946
947 u8 dce_tcp_g[0x20];
948
949 u8 dce_tcp_rtt[0x20];
950
951 u8 rate_reduce_monitor_period[0x20];
952
953 u8 reserved_6[0x20];
954
955 u8 initial_alpha_value[0x20];
956
957 u8 reserved_7[0x4a0];
958};
959
960struct mlx5_ifc_cong_control_802_1qau_rp_bits {
961 u8 reserved_0[0x80];
962
963 u8 rppp_max_rps[0x20];
964
965 u8 rpg_time_reset[0x20];
966
967 u8 rpg_byte_reset[0x20];
968
969 u8 rpg_threshold[0x20];
970
971 u8 rpg_max_rate[0x20];
972
973 u8 rpg_ai_rate[0x20];
974
975 u8 rpg_hai_rate[0x20];
976
977 u8 rpg_gd[0x20];
978
979 u8 rpg_min_dec_fac[0x20];
980
981 u8 rpg_min_rate[0x20];
982
983 u8 reserved_1[0x640];
984};
985
986enum {
987 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
988 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
989 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
990};
991
992struct mlx5_ifc_resize_field_select_bits {
993 u8 resize_field_select[0x20];
994};
995
996enum {
997 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
998 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
999 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1000 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1001};
1002
1003struct mlx5_ifc_modify_field_select_bits {
1004 u8 modify_field_select[0x20];
1005};
1006
1007struct mlx5_ifc_field_select_r_roce_np_bits {
1008 u8 field_select_r_roce_np[0x20];
1009};
1010
1011struct mlx5_ifc_field_select_r_roce_rp_bits {
1012 u8 field_select_r_roce_rp[0x20];
1013};
1014
1015enum {
1016 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1017 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1018 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1019 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1020 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1021 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1022 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1023 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1024 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1025 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1026};
1027
1028struct mlx5_ifc_field_select_802_1qau_rp_bits {
1029 u8 field_select_8021qaurp[0x20];
1030};
1031
1032struct mlx5_ifc_phys_layer_cntrs_bits {
1033 u8 time_since_last_clear_high[0x20];
1034
1035 u8 time_since_last_clear_low[0x20];
1036
1037 u8 symbol_errors_high[0x20];
1038
1039 u8 symbol_errors_low[0x20];
1040
1041 u8 sync_headers_errors_high[0x20];
1042
1043 u8 sync_headers_errors_low[0x20];
1044
1045 u8 edpl_bip_errors_lane0_high[0x20];
1046
1047 u8 edpl_bip_errors_lane0_low[0x20];
1048
1049 u8 edpl_bip_errors_lane1_high[0x20];
1050
1051 u8 edpl_bip_errors_lane1_low[0x20];
1052
1053 u8 edpl_bip_errors_lane2_high[0x20];
1054
1055 u8 edpl_bip_errors_lane2_low[0x20];
1056
1057 u8 edpl_bip_errors_lane3_high[0x20];
1058
1059 u8 edpl_bip_errors_lane3_low[0x20];
1060
1061 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1062
1063 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1064
1065 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1066
1067 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1068
1069 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1070
1071 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1072
1073 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1074
1075 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1076
1077 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1078
1079 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1080
1081 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1082
1083 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1084
1085 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1086
1087 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1088
1089 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1090
1091 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1092
1093 u8 rs_fec_corrected_blocks_high[0x20];
1094
1095 u8 rs_fec_corrected_blocks_low[0x20];
1096
1097 u8 rs_fec_uncorrectable_blocks_high[0x20];
1098
1099 u8 rs_fec_uncorrectable_blocks_low[0x20];
1100
1101 u8 rs_fec_no_errors_blocks_high[0x20];
1102
1103 u8 rs_fec_no_errors_blocks_low[0x20];
1104
1105 u8 rs_fec_single_error_blocks_high[0x20];
1106
1107 u8 rs_fec_single_error_blocks_low[0x20];
1108
1109 u8 rs_fec_corrected_symbols_total_high[0x20];
1110
1111 u8 rs_fec_corrected_symbols_total_low[0x20];
1112
1113 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1114
1115 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1116
1117 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1118
1119 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1120
1121 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1122
1123 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1124
1125 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1126
1127 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1128
1129 u8 link_down_events[0x20];
1130
1131 u8 successful_recovery_events[0x20];
1132
1133 u8 reserved_0[0x180];
1134};
1135
1136struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1137 u8 transmit_queue_high[0x20];
1138
1139 u8 transmit_queue_low[0x20];
1140
1141 u8 reserved_0[0x780];
1142};
1143
1144struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1145 u8 rx_octets_high[0x20];
1146
1147 u8 rx_octets_low[0x20];
1148
1149 u8 reserved_0[0xc0];
1150
1151 u8 rx_frames_high[0x20];
1152
1153 u8 rx_frames_low[0x20];
1154
1155 u8 tx_octets_high[0x20];
1156
1157 u8 tx_octets_low[0x20];
1158
1159 u8 reserved_1[0xc0];
1160
1161 u8 tx_frames_high[0x20];
1162
1163 u8 tx_frames_low[0x20];
1164
1165 u8 rx_pause_high[0x20];
1166
1167 u8 rx_pause_low[0x20];
1168
1169 u8 rx_pause_duration_high[0x20];
1170
1171 u8 rx_pause_duration_low[0x20];
1172
1173 u8 tx_pause_high[0x20];
1174
1175 u8 tx_pause_low[0x20];
1176
1177 u8 tx_pause_duration_high[0x20];
1178
1179 u8 tx_pause_duration_low[0x20];
1180
1181 u8 rx_pause_transition_high[0x20];
1182
1183 u8 rx_pause_transition_low[0x20];
1184
1185 u8 reserved_2[0x400];
1186};
1187
1188struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1189 u8 port_transmit_wait_high[0x20];
1190
1191 u8 port_transmit_wait_low[0x20];
1192
1193 u8 reserved_0[0x780];
1194};
1195
1196struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1197 u8 dot3stats_alignment_errors_high[0x20];
1198
1199 u8 dot3stats_alignment_errors_low[0x20];
1200
1201 u8 dot3stats_fcs_errors_high[0x20];
1202
1203 u8 dot3stats_fcs_errors_low[0x20];
1204
1205 u8 dot3stats_single_collision_frames_high[0x20];
1206
1207 u8 dot3stats_single_collision_frames_low[0x20];
1208
1209 u8 dot3stats_multiple_collision_frames_high[0x20];
1210
1211 u8 dot3stats_multiple_collision_frames_low[0x20];
1212
1213 u8 dot3stats_sqe_test_errors_high[0x20];
1214
1215 u8 dot3stats_sqe_test_errors_low[0x20];
1216
1217 u8 dot3stats_deferred_transmissions_high[0x20];
1218
1219 u8 dot3stats_deferred_transmissions_low[0x20];
1220
1221 u8 dot3stats_late_collisions_high[0x20];
1222
1223 u8 dot3stats_late_collisions_low[0x20];
1224
1225 u8 dot3stats_excessive_collisions_high[0x20];
1226
1227 u8 dot3stats_excessive_collisions_low[0x20];
1228
1229 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
1230
1231 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
1232
1233 u8 dot3stats_carrier_sense_errors_high[0x20];
1234
1235 u8 dot3stats_carrier_sense_errors_low[0x20];
1236
1237 u8 dot3stats_frame_too_longs_high[0x20];
1238
1239 u8 dot3stats_frame_too_longs_low[0x20];
1240
1241 u8 dot3stats_internal_mac_receive_errors_high[0x20];
1242
1243 u8 dot3stats_internal_mac_receive_errors_low[0x20];
1244
1245 u8 dot3stats_symbol_errors_high[0x20];
1246
1247 u8 dot3stats_symbol_errors_low[0x20];
1248
1249 u8 dot3control_in_unknown_opcodes_high[0x20];
1250
1251 u8 dot3control_in_unknown_opcodes_low[0x20];
1252
1253 u8 dot3in_pause_frames_high[0x20];
1254
1255 u8 dot3in_pause_frames_low[0x20];
1256
1257 u8 dot3out_pause_frames_high[0x20];
1258
1259 u8 dot3out_pause_frames_low[0x20];
1260
1261 u8 reserved_0[0x3c0];
1262};
1263
1264struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1265 u8 ether_stats_drop_events_high[0x20];
1266
1267 u8 ether_stats_drop_events_low[0x20];
1268
1269 u8 ether_stats_octets_high[0x20];
1270
1271 u8 ether_stats_octets_low[0x20];
1272
1273 u8 ether_stats_pkts_high[0x20];
1274
1275 u8 ether_stats_pkts_low[0x20];
1276
1277 u8 ether_stats_broadcast_pkts_high[0x20];
1278
1279 u8 ether_stats_broadcast_pkts_low[0x20];
1280
1281 u8 ether_stats_multicast_pkts_high[0x20];
1282
1283 u8 ether_stats_multicast_pkts_low[0x20];
1284
1285 u8 ether_stats_crc_align_errors_high[0x20];
1286
1287 u8 ether_stats_crc_align_errors_low[0x20];
1288
1289 u8 ether_stats_undersize_pkts_high[0x20];
1290
1291 u8 ether_stats_undersize_pkts_low[0x20];
1292
1293 u8 ether_stats_oversize_pkts_high[0x20];
1294
1295 u8 ether_stats_oversize_pkts_low[0x20];
1296
1297 u8 ether_stats_fragments_high[0x20];
1298
1299 u8 ether_stats_fragments_low[0x20];
1300
1301 u8 ether_stats_jabbers_high[0x20];
1302
1303 u8 ether_stats_jabbers_low[0x20];
1304
1305 u8 ether_stats_collisions_high[0x20];
1306
1307 u8 ether_stats_collisions_low[0x20];
1308
1309 u8 ether_stats_pkts64octets_high[0x20];
1310
1311 u8 ether_stats_pkts64octets_low[0x20];
1312
1313 u8 ether_stats_pkts65to127octets_high[0x20];
1314
1315 u8 ether_stats_pkts65to127octets_low[0x20];
1316
1317 u8 ether_stats_pkts128to255octets_high[0x20];
1318
1319 u8 ether_stats_pkts128to255octets_low[0x20];
1320
1321 u8 ether_stats_pkts256to511octets_high[0x20];
1322
1323 u8 ether_stats_pkts256to511octets_low[0x20];
1324
1325 u8 ether_stats_pkts512to1023octets_high[0x20];
1326
1327 u8 ether_stats_pkts512to1023octets_low[0x20];
1328
1329 u8 ether_stats_pkts1024to1518octets_high[0x20];
1330
1331 u8 ether_stats_pkts1024to1518octets_low[0x20];
1332
1333 u8 ether_stats_pkts1519to2047octets_high[0x20];
1334
1335 u8 ether_stats_pkts1519to2047octets_low[0x20];
1336
1337 u8 ether_stats_pkts2048to4095octets_high[0x20];
1338
1339 u8 ether_stats_pkts2048to4095octets_low[0x20];
1340
1341 u8 ether_stats_pkts4096to8191octets_high[0x20];
1342
1343 u8 ether_stats_pkts4096to8191octets_low[0x20];
1344
1345 u8 ether_stats_pkts8192to10239octets_high[0x20];
1346
1347 u8 ether_stats_pkts8192to10239octets_low[0x20];
1348
1349 u8 reserved_0[0x280];
1350};
1351
1352struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1353 u8 if_in_octets_high[0x20];
1354
1355 u8 if_in_octets_low[0x20];
1356
1357 u8 if_in_ucast_pkts_high[0x20];
1358
1359 u8 if_in_ucast_pkts_low[0x20];
1360
1361 u8 if_in_discards_high[0x20];
1362
1363 u8 if_in_discards_low[0x20];
1364
1365 u8 if_in_errors_high[0x20];
1366
1367 u8 if_in_errors_low[0x20];
1368
1369 u8 if_in_unknown_protos_high[0x20];
1370
1371 u8 if_in_unknown_protos_low[0x20];
1372
1373 u8 if_out_octets_high[0x20];
1374
1375 u8 if_out_octets_low[0x20];
1376
1377 u8 if_out_ucast_pkts_high[0x20];
1378
1379 u8 if_out_ucast_pkts_low[0x20];
1380
1381 u8 if_out_discards_high[0x20];
1382
1383 u8 if_out_discards_low[0x20];
1384
1385 u8 if_out_errors_high[0x20];
1386
1387 u8 if_out_errors_low[0x20];
1388
1389 u8 if_in_multicast_pkts_high[0x20];
1390
1391 u8 if_in_multicast_pkts_low[0x20];
1392
1393 u8 if_in_broadcast_pkts_high[0x20];
1394
1395 u8 if_in_broadcast_pkts_low[0x20];
1396
1397 u8 if_out_multicast_pkts_high[0x20];
1398
1399 u8 if_out_multicast_pkts_low[0x20];
1400
1401 u8 if_out_broadcast_pkts_high[0x20];
1402
1403 u8 if_out_broadcast_pkts_low[0x20];
1404
1405 u8 reserved_0[0x480];
1406};
1407
1408struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1409 u8 a_frames_transmitted_ok_high[0x20];
1410
1411 u8 a_frames_transmitted_ok_low[0x20];
1412
1413 u8 a_frames_received_ok_high[0x20];
1414
1415 u8 a_frames_received_ok_low[0x20];
1416
1417 u8 a_frame_check_sequence_errors_high[0x20];
1418
1419 u8 a_frame_check_sequence_errors_low[0x20];
1420
1421 u8 a_alignment_errors_high[0x20];
1422
1423 u8 a_alignment_errors_low[0x20];
1424
1425 u8 a_octets_transmitted_ok_high[0x20];
1426
1427 u8 a_octets_transmitted_ok_low[0x20];
1428
1429 u8 a_octets_received_ok_high[0x20];
1430
1431 u8 a_octets_received_ok_low[0x20];
1432
1433 u8 a_multicast_frames_xmitted_ok_high[0x20];
1434
1435 u8 a_multicast_frames_xmitted_ok_low[0x20];
1436
1437 u8 a_broadcast_frames_xmitted_ok_high[0x20];
1438
1439 u8 a_broadcast_frames_xmitted_ok_low[0x20];
1440
1441 u8 a_multicast_frames_received_ok_high[0x20];
1442
1443 u8 a_multicast_frames_received_ok_low[0x20];
1444
1445 u8 a_broadcast_frames_received_ok_high[0x20];
1446
1447 u8 a_broadcast_frames_received_ok_low[0x20];
1448
1449 u8 a_in_range_length_errors_high[0x20];
1450
1451 u8 a_in_range_length_errors_low[0x20];
1452
1453 u8 a_out_of_range_length_field_high[0x20];
1454
1455 u8 a_out_of_range_length_field_low[0x20];
1456
1457 u8 a_frame_too_long_errors_high[0x20];
1458
1459 u8 a_frame_too_long_errors_low[0x20];
1460
1461 u8 a_symbol_error_during_carrier_high[0x20];
1462
1463 u8 a_symbol_error_during_carrier_low[0x20];
1464
1465 u8 a_mac_control_frames_transmitted_high[0x20];
1466
1467 u8 a_mac_control_frames_transmitted_low[0x20];
1468
1469 u8 a_mac_control_frames_received_high[0x20];
1470
1471 u8 a_mac_control_frames_received_low[0x20];
1472
1473 u8 a_unsupported_opcodes_received_high[0x20];
1474
1475 u8 a_unsupported_opcodes_received_low[0x20];
1476
1477 u8 a_pause_mac_ctrl_frames_received_high[0x20];
1478
1479 u8 a_pause_mac_ctrl_frames_received_low[0x20];
1480
1481 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
1482
1483 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
1484
1485 u8 reserved_0[0x300];
1486};
1487
1488struct mlx5_ifc_cmd_inter_comp_event_bits {
1489 u8 command_completion_vector[0x20];
1490
1491 u8 reserved_0[0xc0];
1492};
1493
1494struct mlx5_ifc_stall_vl_event_bits {
1495 u8 reserved_0[0x18];
1496 u8 port_num[0x1];
1497 u8 reserved_1[0x3];
1498 u8 vl[0x4];
1499
1500 u8 reserved_2[0xa0];
1501};
1502
1503struct mlx5_ifc_db_bf_congestion_event_bits {
1504 u8 event_subtype[0x8];
1505 u8 reserved_0[0x8];
1506 u8 congestion_level[0x8];
1507 u8 reserved_1[0x8];
1508
1509 u8 reserved_2[0xa0];
1510};
1511
1512struct mlx5_ifc_gpio_event_bits {
1513 u8 reserved_0[0x60];
1514
1515 u8 gpio_event_hi[0x20];
1516
1517 u8 gpio_event_lo[0x20];
1518
1519 u8 reserved_1[0x40];
1520};
1521
1522struct mlx5_ifc_port_state_change_event_bits {
1523 u8 reserved_0[0x40];
1524
1525 u8 port_num[0x4];
1526 u8 reserved_1[0x1c];
1527
1528 u8 reserved_2[0x80];
1529};
1530
1531struct mlx5_ifc_dropped_packet_logged_bits {
1532 u8 reserved_0[0xe0];
1533};
1534
1535enum {
1536 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
1537 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
1538};
1539
1540struct mlx5_ifc_cq_error_bits {
1541 u8 reserved_0[0x8];
1542 u8 cqn[0x18];
1543
1544 u8 reserved_1[0x20];
1545
1546 u8 reserved_2[0x18];
1547 u8 syndrome[0x8];
1548
1549 u8 reserved_3[0x80];
1550};
1551
1552struct mlx5_ifc_rdma_page_fault_event_bits {
1553 u8 bytes_committed[0x20];
1554
1555 u8 r_key[0x20];
1556
1557 u8 reserved_0[0x10];
1558 u8 packet_len[0x10];
1559
1560 u8 rdma_op_len[0x20];
1561
1562 u8 rdma_va[0x40];
1563
1564 u8 reserved_1[0x5];
1565 u8 rdma[0x1];
1566 u8 write[0x1];
1567 u8 requestor[0x1];
1568 u8 qp_number[0x18];
1569};
1570
1571struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1572 u8 bytes_committed[0x20];
1573
1574 u8 reserved_0[0x10];
1575 u8 wqe_index[0x10];
1576
1577 u8 reserved_1[0x10];
1578 u8 len[0x10];
1579
1580 u8 reserved_2[0x60];
1581
1582 u8 reserved_3[0x5];
1583 u8 rdma[0x1];
1584 u8 write_read[0x1];
1585 u8 requestor[0x1];
1586 u8 qpn[0x18];
1587};
1588
1589struct mlx5_ifc_qp_events_bits {
1590 u8 reserved_0[0xa0];
1591
1592 u8 type[0x8];
1593 u8 reserved_1[0x18];
1594
1595 u8 reserved_2[0x8];
1596 u8 qpn_rqn_sqn[0x18];
1597};
1598
1599struct mlx5_ifc_dct_events_bits {
1600 u8 reserved_0[0xc0];
1601
1602 u8 reserved_1[0x8];
1603 u8 dct_number[0x18];
1604};
1605
1606struct mlx5_ifc_comp_event_bits {
1607 u8 reserved_0[0xc0];
1608
1609 u8 reserved_1[0x8];
1610 u8 cq_number[0x18];
1611};
1612
1613enum {
1614 MLX5_QPC_STATE_RST = 0x0,
1615 MLX5_QPC_STATE_INIT = 0x1,
1616 MLX5_QPC_STATE_RTR = 0x2,
1617 MLX5_QPC_STATE_RTS = 0x3,
1618 MLX5_QPC_STATE_SQER = 0x4,
1619 MLX5_QPC_STATE_ERR = 0x6,
1620 MLX5_QPC_STATE_SQD = 0x7,
1621 MLX5_QPC_STATE_SUSPENDED = 0x9,
1622};
1623
1624enum {
1625 MLX5_QPC_ST_RC = 0x0,
1626 MLX5_QPC_ST_UC = 0x1,
1627 MLX5_QPC_ST_UD = 0x2,
1628 MLX5_QPC_ST_XRC = 0x3,
1629 MLX5_QPC_ST_DCI = 0x5,
1630 MLX5_QPC_ST_QP0 = 0x7,
1631 MLX5_QPC_ST_QP1 = 0x8,
1632 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
1633 MLX5_QPC_ST_REG_UMR = 0xc,
1634};
1635
1636enum {
1637 MLX5_QPC_PM_STATE_ARMED = 0x0,
1638 MLX5_QPC_PM_STATE_REARM = 0x1,
1639 MLX5_QPC_PM_STATE_RESERVED = 0x2,
1640 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
1641};
1642
1643enum {
1644 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
1645 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
1646};
1647
1648enum {
1649 MLX5_QPC_MTU_256_BYTES = 0x1,
1650 MLX5_QPC_MTU_512_BYTES = 0x2,
1651 MLX5_QPC_MTU_1K_BYTES = 0x3,
1652 MLX5_QPC_MTU_2K_BYTES = 0x4,
1653 MLX5_QPC_MTU_4K_BYTES = 0x5,
1654 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
1655};
1656
1657enum {
1658 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
1659 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
1660 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
1661 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
1662 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
1663 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
1664 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
1665 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
1666};
1667
1668enum {
1669 MLX5_QPC_CS_REQ_DISABLE = 0x0,
1670 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
1671 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
1672};
1673
1674enum {
1675 MLX5_QPC_CS_RES_DISABLE = 0x0,
1676 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
1677 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
1678};
1679
1680struct mlx5_ifc_qpc_bits {
1681 u8 state[0x4];
1682 u8 reserved_0[0x4];
1683 u8 st[0x8];
1684 u8 reserved_1[0x3];
1685 u8 pm_state[0x2];
1686 u8 reserved_2[0x7];
1687 u8 end_padding_mode[0x2];
1688 u8 reserved_3[0x2];
1689
1690 u8 wq_signature[0x1];
1691 u8 block_lb_mc[0x1];
1692 u8 atomic_like_write_en[0x1];
1693 u8 latency_sensitive[0x1];
1694 u8 reserved_4[0x1];
1695 u8 drain_sigerr[0x1];
1696 u8 reserved_5[0x2];
1697 u8 pd[0x18];
1698
1699 u8 mtu[0x3];
1700 u8 log_msg_max[0x5];
1701 u8 reserved_6[0x1];
1702 u8 log_rq_size[0x4];
1703 u8 log_rq_stride[0x3];
1704 u8 no_sq[0x1];
1705 u8 log_sq_size[0x4];
1706 u8 reserved_7[0x6];
1707 u8 rlky[0x1];
1708 u8 reserved_8[0x4];
1709
1710 u8 counter_set_id[0x8];
1711 u8 uar_page[0x18];
1712
1713 u8 reserved_9[0x8];
1714 u8 user_index[0x18];
1715
1716 u8 reserved_10[0x3];
1717 u8 log_page_size[0x5];
1718 u8 remote_qpn[0x18];
1719
1720 struct mlx5_ifc_ads_bits primary_address_path;
1721
1722 struct mlx5_ifc_ads_bits secondary_address_path;
1723
1724 u8 log_ack_req_freq[0x4];
1725 u8 reserved_11[0x4];
1726 u8 log_sra_max[0x3];
1727 u8 reserved_12[0x2];
1728 u8 retry_count[0x3];
1729 u8 rnr_retry[0x3];
1730 u8 reserved_13[0x1];
1731 u8 fre[0x1];
1732 u8 cur_rnr_retry[0x3];
1733 u8 cur_retry_count[0x3];
1734 u8 reserved_14[0x5];
1735
1736 u8 reserved_15[0x20];
1737
1738 u8 reserved_16[0x8];
1739 u8 next_send_psn[0x18];
1740
1741 u8 reserved_17[0x8];
1742 u8 cqn_snd[0x18];
1743
1744 u8 reserved_18[0x40];
1745
1746 u8 reserved_19[0x8];
1747 u8 last_acked_psn[0x18];
1748
1749 u8 reserved_20[0x8];
1750 u8 ssn[0x18];
1751
1752 u8 reserved_21[0x8];
1753 u8 log_rra_max[0x3];
1754 u8 reserved_22[0x1];
1755 u8 atomic_mode[0x4];
1756 u8 rre[0x1];
1757 u8 rwe[0x1];
1758 u8 rae[0x1];
1759 u8 reserved_23[0x1];
1760 u8 page_offset[0x6];
1761 u8 reserved_24[0x3];
1762 u8 cd_slave_receive[0x1];
1763 u8 cd_slave_send[0x1];
1764 u8 cd_master[0x1];
1765
1766 u8 reserved_25[0x3];
1767 u8 min_rnr_nak[0x5];
1768 u8 next_rcv_psn[0x18];
1769
1770 u8 reserved_26[0x8];
1771 u8 xrcd[0x18];
1772
1773 u8 reserved_27[0x8];
1774 u8 cqn_rcv[0x18];
1775
1776 u8 dbr_addr[0x40];
1777
1778 u8 q_key[0x20];
1779
1780 u8 reserved_28[0x5];
1781 u8 rq_type[0x3];
1782 u8 srqn_rmpn[0x18];
1783
1784 u8 reserved_29[0x8];
1785 u8 rmsn[0x18];
1786
1787 u8 hw_sq_wqebb_counter[0x10];
1788 u8 sw_sq_wqebb_counter[0x10];
1789
1790 u8 hw_rq_counter[0x20];
1791
1792 u8 sw_rq_counter[0x20];
1793
1794 u8 reserved_30[0x20];
1795
1796 u8 reserved_31[0xf];
1797 u8 cgs[0x1];
1798 u8 cs_req[0x8];
1799 u8 cs_res[0x8];
1800
1801 u8 dc_access_key[0x40];
1802
1803 u8 reserved_32[0xc0];
1804};
1805
1806struct mlx5_ifc_roce_addr_layout_bits {
1807 u8 source_l3_address[16][0x8];
1808
1809 u8 reserved_0[0x3];
1810 u8 vlan_valid[0x1];
1811 u8 vlan_id[0xc];
1812 u8 source_mac_47_32[0x10];
1813
1814 u8 source_mac_31_0[0x20];
1815
1816 u8 reserved_1[0x14];
1817 u8 roce_l3_type[0x4];
1818 u8 roce_version[0x8];
1819
1820 u8 reserved_2[0x20];
1821};
1822
1823union mlx5_ifc_hca_cap_union_bits {
1824 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
1825 struct mlx5_ifc_odp_cap_bits odp_cap;
1826 struct mlx5_ifc_atomic_caps_bits atomic_caps;
1827 struct mlx5_ifc_roce_cap_bits roce_cap;
1828 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
1829 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
1830 u8 reserved_0[0x8000];
1831};
1832
1833enum {
1834 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
1835 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
1836 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
1837};
1838
1839struct mlx5_ifc_flow_context_bits {
1840 u8 reserved_0[0x20];
1841
1842 u8 group_id[0x20];
1843
1844 u8 reserved_1[0x8];
1845 u8 flow_tag[0x18];
1846
1847 u8 reserved_2[0x10];
1848 u8 action[0x10];
1849
1850 u8 reserved_3[0x8];
1851 u8 destination_list_size[0x18];
1852
1853 u8 reserved_4[0x160];
1854
1855 struct mlx5_ifc_fte_match_param_bits match_value;
1856
1857 u8 reserved_5[0x600];
1858
1859 struct mlx5_ifc_dest_format_struct_bits destination[0];
1860};
1861
1862enum {
1863 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
1864 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
1865};
1866
1867struct mlx5_ifc_xrc_srqc_bits {
1868 u8 state[0x4];
1869 u8 log_xrc_srq_size[0x4];
1870 u8 reserved_0[0x18];
1871
1872 u8 wq_signature[0x1];
1873 u8 cont_srq[0x1];
1874 u8 reserved_1[0x1];
1875 u8 rlky[0x1];
1876 u8 basic_cyclic_rcv_wqe[0x1];
1877 u8 log_rq_stride[0x3];
1878 u8 xrcd[0x18];
1879
1880 u8 page_offset[0x6];
1881 u8 reserved_2[0x2];
1882 u8 cqn[0x18];
1883
1884 u8 reserved_3[0x20];
1885
1886 u8 user_index_equal_xrc_srqn[0x1];
1887 u8 reserved_4[0x1];
1888 u8 log_page_size[0x6];
1889 u8 user_index[0x18];
1890
1891 u8 reserved_5[0x20];
1892
1893 u8 reserved_6[0x8];
1894 u8 pd[0x18];
1895
1896 u8 lwm[0x10];
1897 u8 wqe_cnt[0x10];
1898
1899 u8 reserved_7[0x40];
1900
1901 u8 db_record_addr_h[0x20];
1902
1903 u8 db_record_addr_l[0x1e];
1904 u8 reserved_8[0x2];
1905
1906 u8 reserved_9[0x80];
1907};
1908
1909struct mlx5_ifc_traffic_counter_bits {
1910 u8 packets[0x40];
1911
1912 u8 octets[0x40];
1913};
1914
1915struct mlx5_ifc_tisc_bits {
1916 u8 reserved_0[0xc];
1917 u8 prio[0x4];
1918 u8 reserved_1[0x10];
1919
1920 u8 reserved_2[0x100];
1921
1922 u8 reserved_3[0x8];
1923 u8 transport_domain[0x18];
1924
1925 u8 reserved_4[0x3c0];
1926};
1927
1928enum {
1929 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
1930 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
1931};
1932
1933enum {
1934 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
1935 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
1936};
1937
1938enum {
1939 MLX5_TIRC_RX_HASH_FN_HASH_NONE = 0x0,
1940 MLX5_TIRC_RX_HASH_FN_HASH_INVERTED_XOR8 = 0x1,
1941 MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ = 0x2,
1942};
1943
1944enum {
1945 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1,
1946 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2,
1947};
1948
1949struct mlx5_ifc_tirc_bits {
1950 u8 reserved_0[0x20];
1951
1952 u8 disp_type[0x4];
1953 u8 reserved_1[0x1c];
1954
1955 u8 reserved_2[0x40];
1956
1957 u8 reserved_3[0x4];
1958 u8 lro_timeout_period_usecs[0x10];
1959 u8 lro_enable_mask[0x4];
1960 u8 lro_max_ip_payload_size[0x8];
1961
1962 u8 reserved_4[0x40];
1963
1964 u8 reserved_5[0x8];
1965 u8 inline_rqn[0x18];
1966
1967 u8 rx_hash_symmetric[0x1];
1968 u8 reserved_6[0x1];
1969 u8 tunneled_offload_en[0x1];
1970 u8 reserved_7[0x5];
1971 u8 indirect_table[0x18];
1972
1973 u8 rx_hash_fn[0x4];
1974 u8 reserved_8[0x2];
1975 u8 self_lb_block[0x2];
1976 u8 transport_domain[0x18];
1977
1978 u8 rx_hash_toeplitz_key[10][0x20];
1979
1980 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
1981
1982 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
1983
1984 u8 reserved_9[0x4c0];
1985};
1986
1987enum {
1988 MLX5_SRQC_STATE_GOOD = 0x0,
1989 MLX5_SRQC_STATE_ERROR = 0x1,
1990};
1991
1992struct mlx5_ifc_srqc_bits {
1993 u8 state[0x4];
1994 u8 log_srq_size[0x4];
1995 u8 reserved_0[0x18];
1996
1997 u8 wq_signature[0x1];
1998 u8 cont_srq[0x1];
1999 u8 reserved_1[0x1];
2000 u8 rlky[0x1];
2001 u8 reserved_2[0x1];
2002 u8 log_rq_stride[0x3];
2003 u8 xrcd[0x18];
2004
2005 u8 page_offset[0x6];
2006 u8 reserved_3[0x2];
2007 u8 cqn[0x18];
2008
2009 u8 reserved_4[0x20];
2010
2011 u8 reserved_5[0x2];
2012 u8 log_page_size[0x6];
2013 u8 reserved_6[0x18];
2014
2015 u8 reserved_7[0x20];
2016
2017 u8 reserved_8[0x8];
2018 u8 pd[0x18];
2019
2020 u8 lwm[0x10];
2021 u8 wqe_cnt[0x10];
2022
2023 u8 reserved_9[0x40];
2024
2025 u8 db_record_addr_h[0x20];
2026
2027 u8 db_record_addr_l[0x1e];
2028 u8 reserved_10[0x2];
2029
2030 u8 reserved_11[0x80];
2031};
2032
2033enum {
2034 MLX5_SQC_STATE_RST = 0x0,
2035 MLX5_SQC_STATE_RDY = 0x1,
2036 MLX5_SQC_STATE_ERR = 0x3,
2037};
2038
2039struct mlx5_ifc_sqc_bits {
2040 u8 rlky[0x1];
2041 u8 cd_master[0x1];
2042 u8 fre[0x1];
2043 u8 flush_in_error_en[0x1];
2044 u8 reserved_0[0x4];
2045 u8 state[0x4];
2046 u8 reserved_1[0x14];
2047
2048 u8 reserved_2[0x8];
2049 u8 user_index[0x18];
2050
2051 u8 reserved_3[0x8];
2052 u8 cqn[0x18];
2053
2054 u8 reserved_4[0xa0];
2055
2056 u8 tis_lst_sz[0x10];
2057 u8 reserved_5[0x10];
2058
2059 u8 reserved_6[0x40];
2060
2061 u8 reserved_7[0x8];
2062 u8 tis_num_0[0x18];
2063
2064 struct mlx5_ifc_wq_bits wq;
2065};
2066
2067struct mlx5_ifc_rqtc_bits {
2068 u8 reserved_0[0xa0];
2069
2070 u8 reserved_1[0x10];
2071 u8 rqt_max_size[0x10];
2072
2073 u8 reserved_2[0x10];
2074 u8 rqt_actual_size[0x10];
2075
2076 u8 reserved_3[0x6a0];
2077
2078 struct mlx5_ifc_rq_num_bits rq_num[0];
2079};
2080
2081enum {
2082 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2083 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2084};
2085
2086enum {
2087 MLX5_RQC_STATE_RST = 0x0,
2088 MLX5_RQC_STATE_RDY = 0x1,
2089 MLX5_RQC_STATE_ERR = 0x3,
2090};
2091
2092struct mlx5_ifc_rqc_bits {
2093 u8 rlky[0x1];
2094 u8 reserved_0[0x2];
2095 u8 vsd[0x1];
2096 u8 mem_rq_type[0x4];
2097 u8 state[0x4];
2098 u8 reserved_1[0x1];
2099 u8 flush_in_error_en[0x1];
2100 u8 reserved_2[0x12];
2101
2102 u8 reserved_3[0x8];
2103 u8 user_index[0x18];
2104
2105 u8 reserved_4[0x8];
2106 u8 cqn[0x18];
2107
2108 u8 counter_set_id[0x8];
2109 u8 reserved_5[0x18];
2110
2111 u8 reserved_6[0x8];
2112 u8 rmpn[0x18];
2113
2114 u8 reserved_7[0xe0];
2115
2116 struct mlx5_ifc_wq_bits wq;
2117};
2118
2119enum {
2120 MLX5_RMPC_STATE_RDY = 0x1,
2121 MLX5_RMPC_STATE_ERR = 0x3,
2122};
2123
2124struct mlx5_ifc_rmpc_bits {
2125 u8 reserved_0[0x8];
2126 u8 state[0x4];
2127 u8 reserved_1[0x14];
2128
2129 u8 basic_cyclic_rcv_wqe[0x1];
2130 u8 reserved_2[0x1f];
2131
2132 u8 reserved_3[0x140];
2133
2134 struct mlx5_ifc_wq_bits wq;
2135};
2136
2137enum {
2138 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_UC_MAC_ADDRESS = 0x0,
2139};
2140
2141struct mlx5_ifc_nic_vport_context_bits {
2142 u8 reserved_0[0x1f];
2143 u8 roce_en[0x1];
2144
2145 u8 reserved_1[0x760];
2146
2147 u8 reserved_2[0x5];
2148 u8 allowed_list_type[0x3];
2149 u8 reserved_3[0xc];
2150 u8 allowed_list_size[0xc];
2151
2152 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2153
2154 u8 reserved_4[0x20];
2155
2156 u8 current_uc_mac_address[0][0x40];
2157};
2158
2159enum {
2160 MLX5_MKC_ACCESS_MODE_PA = 0x0,
2161 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
2162 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
2163};
2164
2165struct mlx5_ifc_mkc_bits {
2166 u8 reserved_0[0x1];
2167 u8 free[0x1];
2168 u8 reserved_1[0xd];
2169 u8 small_fence_on_rdma_read_response[0x1];
2170 u8 umr_en[0x1];
2171 u8 a[0x1];
2172 u8 rw[0x1];
2173 u8 rr[0x1];
2174 u8 lw[0x1];
2175 u8 lr[0x1];
2176 u8 access_mode[0x2];
2177 u8 reserved_2[0x8];
2178
2179 u8 qpn[0x18];
2180 u8 mkey_7_0[0x8];
2181
2182 u8 reserved_3[0x20];
2183
2184 u8 length64[0x1];
2185 u8 bsf_en[0x1];
2186 u8 sync_umr[0x1];
2187 u8 reserved_4[0x2];
2188 u8 expected_sigerr_count[0x1];
2189 u8 reserved_5[0x1];
2190 u8 en_rinval[0x1];
2191 u8 pd[0x18];
2192
2193 u8 start_addr[0x40];
2194
2195 u8 len[0x40];
2196
2197 u8 bsf_octword_size[0x20];
2198
2199 u8 reserved_6[0x80];
2200
2201 u8 translations_octword_size[0x20];
2202
2203 u8 reserved_7[0x1b];
2204 u8 log_page_size[0x5];
2205
2206 u8 reserved_8[0x20];
2207};
2208
2209struct mlx5_ifc_pkey_bits {
2210 u8 reserved_0[0x10];
2211 u8 pkey[0x10];
2212};
2213
2214struct mlx5_ifc_array128_auto_bits {
2215 u8 array128_auto[16][0x8];
2216};
2217
2218struct mlx5_ifc_hca_vport_context_bits {
2219 u8 field_select[0x20];
2220
2221 u8 reserved_0[0xe0];
2222
2223 u8 sm_virt_aware[0x1];
2224 u8 has_smi[0x1];
2225 u8 has_raw[0x1];
2226 u8 grh_required[0x1];
2227 u8 reserved_1[0x10];
2228 u8 port_state_policy[0x4];
2229 u8 phy_port_state[0x4];
2230 u8 vport_state[0x4];
2231
2232 u8 reserved_2[0x60];
2233
2234 u8 port_guid[0x40];
2235
2236 u8 node_guid[0x40];
2237
2238 u8 cap_mask1[0x20];
2239
2240 u8 cap_mask1_field_select[0x20];
2241
2242 u8 cap_mask2[0x20];
2243
2244 u8 cap_mask2_field_select[0x20];
2245
2246 u8 reserved_3[0x80];
2247
2248 u8 lid[0x10];
2249 u8 reserved_4[0x4];
2250 u8 init_type_reply[0x4];
2251 u8 lmc[0x3];
2252 u8 subnet_timeout[0x5];
2253
2254 u8 sm_lid[0x10];
2255 u8 sm_sl[0x4];
2256 u8 reserved_5[0xc];
2257
2258 u8 qkey_violation_counter[0x10];
2259 u8 pkey_violation_counter[0x10];
2260
2261 u8 reserved_6[0xca0];
2262};
2263
2264enum {
2265 MLX5_EQC_STATUS_OK = 0x0,
2266 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
2267};
2268
2269enum {
2270 MLX5_EQC_ST_ARMED = 0x9,
2271 MLX5_EQC_ST_FIRED = 0xa,
2272};
2273
2274struct mlx5_ifc_eqc_bits {
2275 u8 status[0x4];
2276 u8 reserved_0[0x9];
2277 u8 ec[0x1];
2278 u8 oi[0x1];
2279 u8 reserved_1[0x5];
2280 u8 st[0x4];
2281 u8 reserved_2[0x8];
2282
2283 u8 reserved_3[0x20];
2284
2285 u8 reserved_4[0x14];
2286 u8 page_offset[0x6];
2287 u8 reserved_5[0x6];
2288
2289 u8 reserved_6[0x3];
2290 u8 log_eq_size[0x5];
2291 u8 uar_page[0x18];
2292
2293 u8 reserved_7[0x20];
2294
2295 u8 reserved_8[0x18];
2296 u8 intr[0x8];
2297
2298 u8 reserved_9[0x3];
2299 u8 log_page_size[0x5];
2300 u8 reserved_10[0x18];
2301
2302 u8 reserved_11[0x60];
2303
2304 u8 reserved_12[0x8];
2305 u8 consumer_counter[0x18];
2306
2307 u8 reserved_13[0x8];
2308 u8 producer_counter[0x18];
2309
2310 u8 reserved_14[0x80];
2311};
2312
2313enum {
2314 MLX5_DCTC_STATE_ACTIVE = 0x0,
2315 MLX5_DCTC_STATE_DRAINING = 0x1,
2316 MLX5_DCTC_STATE_DRAINED = 0x2,
2317};
2318
2319enum {
2320 MLX5_DCTC_CS_RES_DISABLE = 0x0,
2321 MLX5_DCTC_CS_RES_NA = 0x1,
2322 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
2323};
2324
2325enum {
2326 MLX5_DCTC_MTU_256_BYTES = 0x1,
2327 MLX5_DCTC_MTU_512_BYTES = 0x2,
2328 MLX5_DCTC_MTU_1K_BYTES = 0x3,
2329 MLX5_DCTC_MTU_2K_BYTES = 0x4,
2330 MLX5_DCTC_MTU_4K_BYTES = 0x5,
2331};
2332
2333struct mlx5_ifc_dctc_bits {
2334 u8 reserved_0[0x4];
2335 u8 state[0x4];
2336 u8 reserved_1[0x18];
2337
2338 u8 reserved_2[0x8];
2339 u8 user_index[0x18];
2340
2341 u8 reserved_3[0x8];
2342 u8 cqn[0x18];
2343
2344 u8 counter_set_id[0x8];
2345 u8 atomic_mode[0x4];
2346 u8 rre[0x1];
2347 u8 rwe[0x1];
2348 u8 rae[0x1];
2349 u8 atomic_like_write_en[0x1];
2350 u8 latency_sensitive[0x1];
2351 u8 rlky[0x1];
2352 u8 free_ar[0x1];
2353 u8 reserved_4[0xd];
2354
2355 u8 reserved_5[0x8];
2356 u8 cs_res[0x8];
2357 u8 reserved_6[0x3];
2358 u8 min_rnr_nak[0x5];
2359 u8 reserved_7[0x8];
2360
2361 u8 reserved_8[0x8];
2362 u8 srqn[0x18];
2363
2364 u8 reserved_9[0x8];
2365 u8 pd[0x18];
2366
2367 u8 tclass[0x8];
2368 u8 reserved_10[0x4];
2369 u8 flow_label[0x14];
2370
2371 u8 dc_access_key[0x40];
2372
2373 u8 reserved_11[0x5];
2374 u8 mtu[0x3];
2375 u8 port[0x8];
2376 u8 pkey_index[0x10];
2377
2378 u8 reserved_12[0x8];
2379 u8 my_addr_index[0x8];
2380 u8 reserved_13[0x8];
2381 u8 hop_limit[0x8];
2382
2383 u8 dc_access_key_violation_count[0x20];
2384
2385 u8 reserved_14[0x14];
2386 u8 dei_cfi[0x1];
2387 u8 eth_prio[0x3];
2388 u8 ecn[0x2];
2389 u8 dscp[0x6];
2390
2391 u8 reserved_15[0x40];
2392};
2393
2394enum {
2395 MLX5_CQC_STATUS_OK = 0x0,
2396 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
2397 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
2398};
2399
2400enum {
2401 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
2402 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
2403};
2404
2405enum {
2406 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
2407 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
2408 MLX5_CQC_ST_FIRED = 0xa,
2409};
2410
2411struct mlx5_ifc_cqc_bits {
2412 u8 status[0x4];
2413 u8 reserved_0[0x4];
2414 u8 cqe_sz[0x3];
2415 u8 cc[0x1];
2416 u8 reserved_1[0x1];
2417 u8 scqe_break_moderation_en[0x1];
2418 u8 oi[0x1];
2419 u8 reserved_2[0x2];
2420 u8 cqe_zip_en[0x1];
2421 u8 mini_cqe_res_format[0x2];
2422 u8 st[0x4];
2423 u8 reserved_3[0x8];
2424
2425 u8 reserved_4[0x20];
2426
2427 u8 reserved_5[0x14];
2428 u8 page_offset[0x6];
2429 u8 reserved_6[0x6];
2430
2431 u8 reserved_7[0x3];
2432 u8 log_cq_size[0x5];
2433 u8 uar_page[0x18];
2434
2435 u8 reserved_8[0x4];
2436 u8 cq_period[0xc];
2437 u8 cq_max_count[0x10];
2438
2439 u8 reserved_9[0x18];
2440 u8 c_eqn[0x8];
2441
2442 u8 reserved_10[0x3];
2443 u8 log_page_size[0x5];
2444 u8 reserved_11[0x18];
2445
2446 u8 reserved_12[0x20];
2447
2448 u8 reserved_13[0x8];
2449 u8 last_notified_index[0x18];
2450
2451 u8 reserved_14[0x8];
2452 u8 last_solicit_index[0x18];
2453
2454 u8 reserved_15[0x8];
2455 u8 consumer_counter[0x18];
2456
2457 u8 reserved_16[0x8];
2458 u8 producer_counter[0x18];
2459
2460 u8 reserved_17[0x40];
2461
2462 u8 dbr_addr[0x40];
2463};
2464
2465union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2466 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2467 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2468 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2469 u8 reserved_0[0x800];
2470};
2471
2472struct mlx5_ifc_query_adapter_param_block_bits {
2473 u8 reserved_0[0xe0];
2474
2475 u8 reserved_1[0x10];
2476 u8 vsd_vendor_id[0x10];
2477
2478 u8 vsd[208][0x8];
2479
2480 u8 vsd_contd_psid[16][0x8];
2481};
2482
2483union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2484 struct mlx5_ifc_modify_field_select_bits modify_field_select;
2485 struct mlx5_ifc_resize_field_select_bits resize_field_select;
2486 u8 reserved_0[0x20];
2487};
2488
2489union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2490 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2491 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2492 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
2493 u8 reserved_0[0x20];
2494};
2495
2496union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
2497 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
2498 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
2499 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
2500 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
2501 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
2502 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
2503 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
2504 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
2505 u8 reserved_0[0x7c0];
2506};
2507
2508union mlx5_ifc_event_auto_bits {
2509 struct mlx5_ifc_comp_event_bits comp_event;
2510 struct mlx5_ifc_dct_events_bits dct_events;
2511 struct mlx5_ifc_qp_events_bits qp_events;
2512 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
2513 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
2514 struct mlx5_ifc_cq_error_bits cq_error;
2515 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
2516 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
2517 struct mlx5_ifc_gpio_event_bits gpio_event;
2518 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
2519 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
2520 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
2521 u8 reserved_0[0xe0];
2522};
2523
2524struct mlx5_ifc_health_buffer_bits {
2525 u8 reserved_0[0x100];
2526
2527 u8 assert_existptr[0x20];
2528
2529 u8 assert_callra[0x20];
2530
2531 u8 reserved_1[0x40];
2532
2533 u8 fw_version[0x20];
2534
2535 u8 hw_id[0x20];
2536
2537 u8 reserved_2[0x20];
2538
2539 u8 irisc_index[0x8];
2540 u8 synd[0x8];
2541 u8 ext_synd[0x10];
2542};
2543
2544struct mlx5_ifc_register_loopback_control_bits {
2545 u8 no_lb[0x1];
2546 u8 reserved_0[0x7];
2547 u8 port[0x8];
2548 u8 reserved_1[0x10];
2549
2550 u8 reserved_2[0x60];
2551};
2552
2553struct mlx5_ifc_teardown_hca_out_bits {
2554 u8 status[0x8];
2555 u8 reserved_0[0x18];
2556
2557 u8 syndrome[0x20];
2558
2559 u8 reserved_1[0x40];
2560};
2561
2562enum {
2563 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
2564 MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE = 0x1,
2565};
2566
2567struct mlx5_ifc_teardown_hca_in_bits {
2568 u8 opcode[0x10];
2569 u8 reserved_0[0x10];
2570
2571 u8 reserved_1[0x10];
2572 u8 op_mod[0x10];
2573
2574 u8 reserved_2[0x10];
2575 u8 profile[0x10];
2576
2577 u8 reserved_3[0x20];
2578};
2579
2580struct mlx5_ifc_sqerr2rts_qp_out_bits {
2581 u8 status[0x8];
2582 u8 reserved_0[0x18];
2583
2584 u8 syndrome[0x20];
2585
2586 u8 reserved_1[0x40];
2587};
2588
2589struct mlx5_ifc_sqerr2rts_qp_in_bits {
2590 u8 opcode[0x10];
2591 u8 reserved_0[0x10];
2592
2593 u8 reserved_1[0x10];
2594 u8 op_mod[0x10];
2595
2596 u8 reserved_2[0x8];
2597 u8 qpn[0x18];
2598
2599 u8 reserved_3[0x20];
2600
2601 u8 opt_param_mask[0x20];
2602
2603 u8 reserved_4[0x20];
2604
2605 struct mlx5_ifc_qpc_bits qpc;
2606
2607 u8 reserved_5[0x80];
2608};
2609
2610struct mlx5_ifc_sqd2rts_qp_out_bits {
2611 u8 status[0x8];
2612 u8 reserved_0[0x18];
2613
2614 u8 syndrome[0x20];
2615
2616 u8 reserved_1[0x40];
2617};
2618
2619struct mlx5_ifc_sqd2rts_qp_in_bits {
2620 u8 opcode[0x10];
2621 u8 reserved_0[0x10];
2622
2623 u8 reserved_1[0x10];
2624 u8 op_mod[0x10];
2625
2626 u8 reserved_2[0x8];
2627 u8 qpn[0x18];
2628
2629 u8 reserved_3[0x20];
2630
2631 u8 opt_param_mask[0x20];
2632
2633 u8 reserved_4[0x20];
2634
2635 struct mlx5_ifc_qpc_bits qpc;
2636
2637 u8 reserved_5[0x80];
2638};
2639
2640struct mlx5_ifc_set_roce_address_out_bits {
2641 u8 status[0x8];
2642 u8 reserved_0[0x18];
2643
2644 u8 syndrome[0x20];
2645
2646 u8 reserved_1[0x40];
2647};
2648
2649struct mlx5_ifc_set_roce_address_in_bits {
2650 u8 opcode[0x10];
2651 u8 reserved_0[0x10];
2652
2653 u8 reserved_1[0x10];
2654 u8 op_mod[0x10];
2655
2656 u8 roce_address_index[0x10];
2657 u8 reserved_2[0x10];
2658
2659 u8 reserved_3[0x20];
2660
2661 struct mlx5_ifc_roce_addr_layout_bits roce_address;
2662};
2663
2664struct mlx5_ifc_set_mad_demux_out_bits {
2665 u8 status[0x8];
2666 u8 reserved_0[0x18];
2667
2668 u8 syndrome[0x20];
2669
2670 u8 reserved_1[0x40];
2671};
2672
2673enum {
2674 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
2675 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
2676};
2677
2678struct mlx5_ifc_set_mad_demux_in_bits {
2679 u8 opcode[0x10];
2680 u8 reserved_0[0x10];
2681
2682 u8 reserved_1[0x10];
2683 u8 op_mod[0x10];
2684
2685 u8 reserved_2[0x20];
2686
2687 u8 reserved_3[0x6];
2688 u8 demux_mode[0x2];
2689 u8 reserved_4[0x18];
2690};
2691
2692struct mlx5_ifc_set_l2_table_entry_out_bits {
2693 u8 status[0x8];
2694 u8 reserved_0[0x18];
2695
2696 u8 syndrome[0x20];
2697
2698 u8 reserved_1[0x40];
2699};
2700
2701struct mlx5_ifc_set_l2_table_entry_in_bits {
2702 u8 opcode[0x10];
2703 u8 reserved_0[0x10];
2704
2705 u8 reserved_1[0x10];
2706 u8 op_mod[0x10];
2707
2708 u8 reserved_2[0x60];
2709
2710 u8 reserved_3[0x8];
2711 u8 table_index[0x18];
2712
2713 u8 reserved_4[0x20];
2714
2715 u8 reserved_5[0x13];
2716 u8 vlan_valid[0x1];
2717 u8 vlan[0xc];
2718
2719 struct mlx5_ifc_mac_address_layout_bits mac_address;
2720
2721 u8 reserved_6[0xc0];
2722};
2723
2724struct mlx5_ifc_set_issi_out_bits {
2725 u8 status[0x8];
2726 u8 reserved_0[0x18];
2727
2728 u8 syndrome[0x20];
2729
2730 u8 reserved_1[0x40];
2731};
2732
2733struct mlx5_ifc_set_issi_in_bits {
2734 u8 opcode[0x10];
2735 u8 reserved_0[0x10];
2736
2737 u8 reserved_1[0x10];
2738 u8 op_mod[0x10];
2739
2740 u8 reserved_2[0x10];
2741 u8 current_issi[0x10];
2742
2743 u8 reserved_3[0x20];
2744};
2745
2746struct mlx5_ifc_set_hca_cap_out_bits {
2747 u8 status[0x8];
2748 u8 reserved_0[0x18];
2749
2750 u8 syndrome[0x20];
2751
2752 u8 reserved_1[0x40];
305}; 2753};
306 2754
307struct mlx5_ifc_set_hca_cap_in_bits { 2755struct mlx5_ifc_set_hca_cap_in_bits {
@@ -313,10 +2761,653 @@ struct mlx5_ifc_set_hca_cap_in_bits {
313 2761
314 u8 reserved_2[0x40]; 2762 u8 reserved_2[0x40];
315 2763
316 struct mlx5_ifc_cmd_hca_cap_bits hca_capability_struct; 2764 union mlx5_ifc_hca_cap_union_bits capability;
317}; 2765};
318 2766
319struct mlx5_ifc_query_hca_cap_in_bits { 2767struct mlx5_ifc_set_fte_out_bits {
2768 u8 status[0x8];
2769 u8 reserved_0[0x18];
2770
2771 u8 syndrome[0x20];
2772
2773 u8 reserved_1[0x40];
2774};
2775
2776struct mlx5_ifc_set_fte_in_bits {
2777 u8 opcode[0x10];
2778 u8 reserved_0[0x10];
2779
2780 u8 reserved_1[0x10];
2781 u8 op_mod[0x10];
2782
2783 u8 reserved_2[0x40];
2784
2785 u8 table_type[0x8];
2786 u8 reserved_3[0x18];
2787
2788 u8 reserved_4[0x8];
2789 u8 table_id[0x18];
2790
2791 u8 reserved_5[0x40];
2792
2793 u8 flow_index[0x20];
2794
2795 u8 reserved_6[0xe0];
2796
2797 struct mlx5_ifc_flow_context_bits flow_context;
2798};
2799
2800struct mlx5_ifc_rts2rts_qp_out_bits {
2801 u8 status[0x8];
2802 u8 reserved_0[0x18];
2803
2804 u8 syndrome[0x20];
2805
2806 u8 reserved_1[0x40];
2807};
2808
2809struct mlx5_ifc_rts2rts_qp_in_bits {
2810 u8 opcode[0x10];
2811 u8 reserved_0[0x10];
2812
2813 u8 reserved_1[0x10];
2814 u8 op_mod[0x10];
2815
2816 u8 reserved_2[0x8];
2817 u8 qpn[0x18];
2818
2819 u8 reserved_3[0x20];
2820
2821 u8 opt_param_mask[0x20];
2822
2823 u8 reserved_4[0x20];
2824
2825 struct mlx5_ifc_qpc_bits qpc;
2826
2827 u8 reserved_5[0x80];
2828};
2829
2830struct mlx5_ifc_rtr2rts_qp_out_bits {
2831 u8 status[0x8];
2832 u8 reserved_0[0x18];
2833
2834 u8 syndrome[0x20];
2835
2836 u8 reserved_1[0x40];
2837};
2838
2839struct mlx5_ifc_rtr2rts_qp_in_bits {
2840 u8 opcode[0x10];
2841 u8 reserved_0[0x10];
2842
2843 u8 reserved_1[0x10];
2844 u8 op_mod[0x10];
2845
2846 u8 reserved_2[0x8];
2847 u8 qpn[0x18];
2848
2849 u8 reserved_3[0x20];
2850
2851 u8 opt_param_mask[0x20];
2852
2853 u8 reserved_4[0x20];
2854
2855 struct mlx5_ifc_qpc_bits qpc;
2856
2857 u8 reserved_5[0x80];
2858};
2859
2860struct mlx5_ifc_rst2init_qp_out_bits {
2861 u8 status[0x8];
2862 u8 reserved_0[0x18];
2863
2864 u8 syndrome[0x20];
2865
2866 u8 reserved_1[0x40];
2867};
2868
2869struct mlx5_ifc_rst2init_qp_in_bits {
2870 u8 opcode[0x10];
2871 u8 reserved_0[0x10];
2872
2873 u8 reserved_1[0x10];
2874 u8 op_mod[0x10];
2875
2876 u8 reserved_2[0x8];
2877 u8 qpn[0x18];
2878
2879 u8 reserved_3[0x20];
2880
2881 u8 opt_param_mask[0x20];
2882
2883 u8 reserved_4[0x20];
2884
2885 struct mlx5_ifc_qpc_bits qpc;
2886
2887 u8 reserved_5[0x80];
2888};
2889
2890struct mlx5_ifc_query_xrc_srq_out_bits {
2891 u8 status[0x8];
2892 u8 reserved_0[0x18];
2893
2894 u8 syndrome[0x20];
2895
2896 u8 reserved_1[0x40];
2897
2898 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
2899
2900 u8 reserved_2[0x600];
2901
2902 u8 pas[0][0x40];
2903};
2904
2905struct mlx5_ifc_query_xrc_srq_in_bits {
2906 u8 opcode[0x10];
2907 u8 reserved_0[0x10];
2908
2909 u8 reserved_1[0x10];
2910 u8 op_mod[0x10];
2911
2912 u8 reserved_2[0x8];
2913 u8 xrc_srqn[0x18];
2914
2915 u8 reserved_3[0x20];
2916};
2917
2918enum {
2919 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
2920 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
2921};
2922
2923struct mlx5_ifc_query_vport_state_out_bits {
2924 u8 status[0x8];
2925 u8 reserved_0[0x18];
2926
2927 u8 syndrome[0x20];
2928
2929 u8 reserved_1[0x20];
2930
2931 u8 reserved_2[0x18];
2932 u8 admin_state[0x4];
2933 u8 state[0x4];
2934};
2935
2936enum {
2937 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0,
2938};
2939
2940struct mlx5_ifc_query_vport_state_in_bits {
2941 u8 opcode[0x10];
2942 u8 reserved_0[0x10];
2943
2944 u8 reserved_1[0x10];
2945 u8 op_mod[0x10];
2946
2947 u8 other_vport[0x1];
2948 u8 reserved_2[0xf];
2949 u8 vport_number[0x10];
2950
2951 u8 reserved_3[0x20];
2952};
2953
2954struct mlx5_ifc_query_vport_counter_out_bits {
2955 u8 status[0x8];
2956 u8 reserved_0[0x18];
2957
2958 u8 syndrome[0x20];
2959
2960 u8 reserved_1[0x40];
2961
2962 struct mlx5_ifc_traffic_counter_bits received_errors;
2963
2964 struct mlx5_ifc_traffic_counter_bits transmit_errors;
2965
2966 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
2967
2968 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
2969
2970 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
2971
2972 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
2973
2974 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
2975
2976 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
2977
2978 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
2979
2980 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
2981
2982 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
2983
2984 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
2985
2986 u8 reserved_2[0xa00];
2987};
2988
2989enum {
2990 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
2991};
2992
2993struct mlx5_ifc_query_vport_counter_in_bits {
2994 u8 opcode[0x10];
2995 u8 reserved_0[0x10];
2996
2997 u8 reserved_1[0x10];
2998 u8 op_mod[0x10];
2999
3000 u8 other_vport[0x1];
3001 u8 reserved_2[0xf];
3002 u8 vport_number[0x10];
3003
3004 u8 reserved_3[0x60];
3005
3006 u8 clear[0x1];
3007 u8 reserved_4[0x1f];
3008
3009 u8 reserved_5[0x20];
3010};
3011
3012struct mlx5_ifc_query_tis_out_bits {
3013 u8 status[0x8];
3014 u8 reserved_0[0x18];
3015
3016 u8 syndrome[0x20];
3017
3018 u8 reserved_1[0x40];
3019
3020 struct mlx5_ifc_tisc_bits tis_context;
3021};
3022
3023struct mlx5_ifc_query_tis_in_bits {
3024 u8 opcode[0x10];
3025 u8 reserved_0[0x10];
3026
3027 u8 reserved_1[0x10];
3028 u8 op_mod[0x10];
3029
3030 u8 reserved_2[0x8];
3031 u8 tisn[0x18];
3032
3033 u8 reserved_3[0x20];
3034};
3035
3036struct mlx5_ifc_query_tir_out_bits {
3037 u8 status[0x8];
3038 u8 reserved_0[0x18];
3039
3040 u8 syndrome[0x20];
3041
3042 u8 reserved_1[0xc0];
3043
3044 struct mlx5_ifc_tirc_bits tir_context;
3045};
3046
3047struct mlx5_ifc_query_tir_in_bits {
3048 u8 opcode[0x10];
3049 u8 reserved_0[0x10];
3050
3051 u8 reserved_1[0x10];
3052 u8 op_mod[0x10];
3053
3054 u8 reserved_2[0x8];
3055 u8 tirn[0x18];
3056
3057 u8 reserved_3[0x20];
3058};
3059
3060struct mlx5_ifc_query_srq_out_bits {
3061 u8 status[0x8];
3062 u8 reserved_0[0x18];
3063
3064 u8 syndrome[0x20];
3065
3066 u8 reserved_1[0x40];
3067
3068 struct mlx5_ifc_srqc_bits srq_context_entry;
3069
3070 u8 reserved_2[0x600];
3071
3072 u8 pas[0][0x40];
3073};
3074
3075struct mlx5_ifc_query_srq_in_bits {
3076 u8 opcode[0x10];
3077 u8 reserved_0[0x10];
3078
3079 u8 reserved_1[0x10];
3080 u8 op_mod[0x10];
3081
3082 u8 reserved_2[0x8];
3083 u8 srqn[0x18];
3084
3085 u8 reserved_3[0x20];
3086};
3087
3088struct mlx5_ifc_query_sq_out_bits {
3089 u8 status[0x8];
3090 u8 reserved_0[0x18];
3091
3092 u8 syndrome[0x20];
3093
3094 u8 reserved_1[0xc0];
3095
3096 struct mlx5_ifc_sqc_bits sq_context;
3097};
3098
3099struct mlx5_ifc_query_sq_in_bits {
3100 u8 opcode[0x10];
3101 u8 reserved_0[0x10];
3102
3103 u8 reserved_1[0x10];
3104 u8 op_mod[0x10];
3105
3106 u8 reserved_2[0x8];
3107 u8 sqn[0x18];
3108
3109 u8 reserved_3[0x20];
3110};
3111
3112struct mlx5_ifc_query_special_contexts_out_bits {
3113 u8 status[0x8];
3114 u8 reserved_0[0x18];
3115
3116 u8 syndrome[0x20];
3117
3118 u8 reserved_1[0x20];
3119
3120 u8 resd_lkey[0x20];
3121};
3122
3123struct mlx5_ifc_query_special_contexts_in_bits {
3124 u8 opcode[0x10];
3125 u8 reserved_0[0x10];
3126
3127 u8 reserved_1[0x10];
3128 u8 op_mod[0x10];
3129
3130 u8 reserved_2[0x40];
3131};
3132
3133struct mlx5_ifc_query_rqt_out_bits {
3134 u8 status[0x8];
3135 u8 reserved_0[0x18];
3136
3137 u8 syndrome[0x20];
3138
3139 u8 reserved_1[0xc0];
3140
3141 struct mlx5_ifc_rqtc_bits rqt_context;
3142};
3143
3144struct mlx5_ifc_query_rqt_in_bits {
3145 u8 opcode[0x10];
3146 u8 reserved_0[0x10];
3147
3148 u8 reserved_1[0x10];
3149 u8 op_mod[0x10];
3150
3151 u8 reserved_2[0x8];
3152 u8 rqtn[0x18];
3153
3154 u8 reserved_3[0x20];
3155};
3156
3157struct mlx5_ifc_query_rq_out_bits {
3158 u8 status[0x8];
3159 u8 reserved_0[0x18];
3160
3161 u8 syndrome[0x20];
3162
3163 u8 reserved_1[0xc0];
3164
3165 struct mlx5_ifc_rqc_bits rq_context;
3166};
3167
3168struct mlx5_ifc_query_rq_in_bits {
3169 u8 opcode[0x10];
3170 u8 reserved_0[0x10];
3171
3172 u8 reserved_1[0x10];
3173 u8 op_mod[0x10];
3174
3175 u8 reserved_2[0x8];
3176 u8 rqn[0x18];
3177
3178 u8 reserved_3[0x20];
3179};
3180
3181struct mlx5_ifc_query_roce_address_out_bits {
3182 u8 status[0x8];
3183 u8 reserved_0[0x18];
3184
3185 u8 syndrome[0x20];
3186
3187 u8 reserved_1[0x40];
3188
3189 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3190};
3191
3192struct mlx5_ifc_query_roce_address_in_bits {
3193 u8 opcode[0x10];
3194 u8 reserved_0[0x10];
3195
3196 u8 reserved_1[0x10];
3197 u8 op_mod[0x10];
3198
3199 u8 roce_address_index[0x10];
3200 u8 reserved_2[0x10];
3201
3202 u8 reserved_3[0x20];
3203};
3204
3205struct mlx5_ifc_query_rmp_out_bits {
3206 u8 status[0x8];
3207 u8 reserved_0[0x18];
3208
3209 u8 syndrome[0x20];
3210
3211 u8 reserved_1[0xc0];
3212
3213 struct mlx5_ifc_rmpc_bits rmp_context;
3214};
3215
3216struct mlx5_ifc_query_rmp_in_bits {
3217 u8 opcode[0x10];
3218 u8 reserved_0[0x10];
3219
3220 u8 reserved_1[0x10];
3221 u8 op_mod[0x10];
3222
3223 u8 reserved_2[0x8];
3224 u8 rmpn[0x18];
3225
3226 u8 reserved_3[0x20];
3227};
3228
3229struct mlx5_ifc_query_qp_out_bits {
3230 u8 status[0x8];
3231 u8 reserved_0[0x18];
3232
3233 u8 syndrome[0x20];
3234
3235 u8 reserved_1[0x40];
3236
3237 u8 opt_param_mask[0x20];
3238
3239 u8 reserved_2[0x20];
3240
3241 struct mlx5_ifc_qpc_bits qpc;
3242
3243 u8 reserved_3[0x80];
3244
3245 u8 pas[0][0x40];
3246};
3247
3248struct mlx5_ifc_query_qp_in_bits {
3249 u8 opcode[0x10];
3250 u8 reserved_0[0x10];
3251
3252 u8 reserved_1[0x10];
3253 u8 op_mod[0x10];
3254
3255 u8 reserved_2[0x8];
3256 u8 qpn[0x18];
3257
3258 u8 reserved_3[0x20];
3259};
3260
3261struct mlx5_ifc_query_q_counter_out_bits {
3262 u8 status[0x8];
3263 u8 reserved_0[0x18];
3264
3265 u8 syndrome[0x20];
3266
3267 u8 reserved_1[0x40];
3268
3269 u8 rx_write_requests[0x20];
3270
3271 u8 reserved_2[0x20];
3272
3273 u8 rx_read_requests[0x20];
3274
3275 u8 reserved_3[0x20];
3276
3277 u8 rx_atomic_requests[0x20];
3278
3279 u8 reserved_4[0x20];
3280
3281 u8 rx_dct_connect[0x20];
3282
3283 u8 reserved_5[0x20];
3284
3285 u8 out_of_buffer[0x20];
3286
3287 u8 reserved_6[0x20];
3288
3289 u8 out_of_sequence[0x20];
3290
3291 u8 reserved_7[0x620];
3292};
3293
3294struct mlx5_ifc_query_q_counter_in_bits {
3295 u8 opcode[0x10];
3296 u8 reserved_0[0x10];
3297
3298 u8 reserved_1[0x10];
3299 u8 op_mod[0x10];
3300
3301 u8 reserved_2[0x80];
3302
3303 u8 clear[0x1];
3304 u8 reserved_3[0x1f];
3305
3306 u8 reserved_4[0x18];
3307 u8 counter_set_id[0x8];
3308};
3309
3310struct mlx5_ifc_query_pages_out_bits {
3311 u8 status[0x8];
3312 u8 reserved_0[0x18];
3313
3314 u8 syndrome[0x20];
3315
3316 u8 reserved_1[0x10];
3317 u8 function_id[0x10];
3318
3319 u8 num_pages[0x20];
3320};
3321
3322enum {
3323 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
3324 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
3325 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
3326};
3327
3328struct mlx5_ifc_query_pages_in_bits {
3329 u8 opcode[0x10];
3330 u8 reserved_0[0x10];
3331
3332 u8 reserved_1[0x10];
3333 u8 op_mod[0x10];
3334
3335 u8 reserved_2[0x10];
3336 u8 function_id[0x10];
3337
3338 u8 reserved_3[0x20];
3339};
3340
3341struct mlx5_ifc_query_nic_vport_context_out_bits {
3342 u8 status[0x8];
3343 u8 reserved_0[0x18];
3344
3345 u8 syndrome[0x20];
3346
3347 u8 reserved_1[0x40];
3348
3349 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
3350};
3351
3352struct mlx5_ifc_query_nic_vport_context_in_bits {
3353 u8 opcode[0x10];
3354 u8 reserved_0[0x10];
3355
3356 u8 reserved_1[0x10];
3357 u8 op_mod[0x10];
3358
3359 u8 other_vport[0x1];
3360 u8 reserved_2[0xf];
3361 u8 vport_number[0x10];
3362
3363 u8 reserved_3[0x5];
3364 u8 allowed_list_type[0x3];
3365 u8 reserved_4[0x18];
3366};
3367
3368struct mlx5_ifc_query_mkey_out_bits {
3369 u8 status[0x8];
3370 u8 reserved_0[0x18];
3371
3372 u8 syndrome[0x20];
3373
3374 u8 reserved_1[0x40];
3375
3376 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
3377
3378 u8 reserved_2[0x600];
3379
3380 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
3381
3382 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
3383};
3384
3385struct mlx5_ifc_query_mkey_in_bits {
3386 u8 opcode[0x10];
3387 u8 reserved_0[0x10];
3388
3389 u8 reserved_1[0x10];
3390 u8 op_mod[0x10];
3391
3392 u8 reserved_2[0x8];
3393 u8 mkey_index[0x18];
3394
3395 u8 pg_access[0x1];
3396 u8 reserved_3[0x1f];
3397};
3398
3399struct mlx5_ifc_query_mad_demux_out_bits {
3400 u8 status[0x8];
3401 u8 reserved_0[0x18];
3402
3403 u8 syndrome[0x20];
3404
3405 u8 reserved_1[0x40];
3406
3407 u8 mad_dumux_parameters_block[0x20];
3408};
3409
3410struct mlx5_ifc_query_mad_demux_in_bits {
320 u8 opcode[0x10]; 3411 u8 opcode[0x10];
321 u8 reserved_0[0x10]; 3412 u8 reserved_0[0x10];
322 3413
@@ -326,6 +3417,143 @@ struct mlx5_ifc_query_hca_cap_in_bits {
326 u8 reserved_2[0x40]; 3417 u8 reserved_2[0x40];
327}; 3418};
328 3419
3420struct mlx5_ifc_query_l2_table_entry_out_bits {
3421 u8 status[0x8];
3422 u8 reserved_0[0x18];
3423
3424 u8 syndrome[0x20];
3425
3426 u8 reserved_1[0xa0];
3427
3428 u8 reserved_2[0x13];
3429 u8 vlan_valid[0x1];
3430 u8 vlan[0xc];
3431
3432 struct mlx5_ifc_mac_address_layout_bits mac_address;
3433
3434 u8 reserved_3[0xc0];
3435};
3436
3437struct mlx5_ifc_query_l2_table_entry_in_bits {
3438 u8 opcode[0x10];
3439 u8 reserved_0[0x10];
3440
3441 u8 reserved_1[0x10];
3442 u8 op_mod[0x10];
3443
3444 u8 reserved_2[0x60];
3445
3446 u8 reserved_3[0x8];
3447 u8 table_index[0x18];
3448
3449 u8 reserved_4[0x140];
3450};
3451
3452struct mlx5_ifc_query_issi_out_bits {
3453 u8 status[0x8];
3454 u8 reserved_0[0x18];
3455
3456 u8 syndrome[0x20];
3457
3458 u8 reserved_1[0x10];
3459 u8 current_issi[0x10];
3460
3461 u8 reserved_2[0xa0];
3462
3463 u8 supported_issi_reserved[76][0x8];
3464 u8 supported_issi_dw0[0x20];
3465};
3466
3467struct mlx5_ifc_query_issi_in_bits {
3468 u8 opcode[0x10];
3469 u8 reserved_0[0x10];
3470
3471 u8 reserved_1[0x10];
3472 u8 op_mod[0x10];
3473
3474 u8 reserved_2[0x40];
3475};
3476
3477struct mlx5_ifc_query_hca_vport_pkey_out_bits {
3478 u8 status[0x8];
3479 u8 reserved_0[0x18];
3480
3481 u8 syndrome[0x20];
3482
3483 u8 reserved_1[0x40];
3484
3485 struct mlx5_ifc_pkey_bits pkey[0];
3486};
3487
3488struct mlx5_ifc_query_hca_vport_pkey_in_bits {
3489 u8 opcode[0x10];
3490 u8 reserved_0[0x10];
3491
3492 u8 reserved_1[0x10];
3493 u8 op_mod[0x10];
3494
3495 u8 other_vport[0x1];
3496 u8 reserved_2[0xf];
3497 u8 vport_number[0x10];
3498
3499 u8 reserved_3[0x10];
3500 u8 pkey_index[0x10];
3501};
3502
3503struct mlx5_ifc_query_hca_vport_gid_out_bits {
3504 u8 status[0x8];
3505 u8 reserved_0[0x18];
3506
3507 u8 syndrome[0x20];
3508
3509 u8 reserved_1[0x20];
3510
3511 u8 gids_num[0x10];
3512 u8 reserved_2[0x10];
3513
3514 struct mlx5_ifc_array128_auto_bits gid[0];
3515};
3516
3517struct mlx5_ifc_query_hca_vport_gid_in_bits {
3518 u8 opcode[0x10];
3519 u8 reserved_0[0x10];
3520
3521 u8 reserved_1[0x10];
3522 u8 op_mod[0x10];
3523
3524 u8 other_vport[0x1];
3525 u8 reserved_2[0xf];
3526 u8 vport_number[0x10];
3527
3528 u8 reserved_3[0x10];
3529 u8 gid_index[0x10];
3530};
3531
3532struct mlx5_ifc_query_hca_vport_context_out_bits {
3533 u8 status[0x8];
3534 u8 reserved_0[0x18];
3535
3536 u8 syndrome[0x20];
3537
3538 u8 reserved_1[0x40];
3539
3540 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
3541};
3542
3543struct mlx5_ifc_query_hca_vport_context_in_bits {
3544 u8 opcode[0x10];
3545 u8 reserved_0[0x10];
3546
3547 u8 reserved_1[0x10];
3548 u8 op_mod[0x10];
3549
3550 u8 other_vport[0x1];
3551 u8 reserved_2[0xf];
3552 u8 vport_number[0x10];
3553
3554 u8 reserved_3[0x20];
3555};
3556
329struct mlx5_ifc_query_hca_cap_out_bits { 3557struct mlx5_ifc_query_hca_cap_out_bits {
330 u8 status[0x8]; 3558 u8 status[0x8];
331 u8 reserved_0[0x18]; 3559 u8 reserved_0[0x18];
@@ -334,16 +3562,3208 @@ struct mlx5_ifc_query_hca_cap_out_bits {
334 3562
335 u8 reserved_1[0x40]; 3563 u8 reserved_1[0x40];
336 3564
337 u8 capability_struct[256][0x8]; 3565 union mlx5_ifc_hca_cap_union_bits capability;
338}; 3566};
339 3567
340struct mlx5_ifc_set_hca_cap_out_bits { 3568struct mlx5_ifc_query_hca_cap_in_bits {
3569 u8 opcode[0x10];
3570 u8 reserved_0[0x10];
3571
3572 u8 reserved_1[0x10];
3573 u8 op_mod[0x10];
3574
3575 u8 reserved_2[0x40];
3576};
3577
3578struct mlx5_ifc_query_flow_table_out_bits {
3579 u8 status[0x8];
3580 u8 reserved_0[0x18];
3581
3582 u8 syndrome[0x20];
3583
3584 u8 reserved_1[0x80];
3585
3586 u8 reserved_2[0x8];
3587 u8 level[0x8];
3588 u8 reserved_3[0x8];
3589 u8 log_size[0x8];
3590
3591 u8 reserved_4[0x120];
3592};
3593
3594struct mlx5_ifc_query_flow_table_in_bits {
3595 u8 opcode[0x10];
3596 u8 reserved_0[0x10];
3597
3598 u8 reserved_1[0x10];
3599 u8 op_mod[0x10];
3600
3601 u8 reserved_2[0x40];
3602
3603 u8 table_type[0x8];
3604 u8 reserved_3[0x18];
3605
3606 u8 reserved_4[0x8];
3607 u8 table_id[0x18];
3608
3609 u8 reserved_5[0x140];
3610};
3611
3612struct mlx5_ifc_query_fte_out_bits {
3613 u8 status[0x8];
3614 u8 reserved_0[0x18];
3615
3616 u8 syndrome[0x20];
3617
3618 u8 reserved_1[0x1c0];
3619
3620 struct mlx5_ifc_flow_context_bits flow_context;
3621};
3622
3623struct mlx5_ifc_query_fte_in_bits {
3624 u8 opcode[0x10];
3625 u8 reserved_0[0x10];
3626
3627 u8 reserved_1[0x10];
3628 u8 op_mod[0x10];
3629
3630 u8 reserved_2[0x40];
3631
3632 u8 table_type[0x8];
3633 u8 reserved_3[0x18];
3634
3635 u8 reserved_4[0x8];
3636 u8 table_id[0x18];
3637
3638 u8 reserved_5[0x40];
3639
3640 u8 flow_index[0x20];
3641
3642 u8 reserved_6[0xe0];
3643};
3644
3645enum {
3646 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
3647 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
3648 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
3649};
3650
3651struct mlx5_ifc_query_flow_group_out_bits {
3652 u8 status[0x8];
3653 u8 reserved_0[0x18];
3654
3655 u8 syndrome[0x20];
3656
3657 u8 reserved_1[0xa0];
3658
3659 u8 start_flow_index[0x20];
3660
3661 u8 reserved_2[0x20];
3662
3663 u8 end_flow_index[0x20];
3664
3665 u8 reserved_3[0xa0];
3666
3667 u8 reserved_4[0x18];
3668 u8 match_criteria_enable[0x8];
3669
3670 struct mlx5_ifc_fte_match_param_bits match_criteria;
3671
3672 u8 reserved_5[0xe00];
3673};
3674
3675struct mlx5_ifc_query_flow_group_in_bits {
3676 u8 opcode[0x10];
3677 u8 reserved_0[0x10];
3678
3679 u8 reserved_1[0x10];
3680 u8 op_mod[0x10];
3681
3682 u8 reserved_2[0x40];
3683
3684 u8 table_type[0x8];
3685 u8 reserved_3[0x18];
3686
3687 u8 reserved_4[0x8];
3688 u8 table_id[0x18];
3689
3690 u8 group_id[0x20];
3691
3692 u8 reserved_5[0x120];
3693};
3694
3695struct mlx5_ifc_query_eq_out_bits {
3696 u8 status[0x8];
3697 u8 reserved_0[0x18];
3698
3699 u8 syndrome[0x20];
3700
3701 u8 reserved_1[0x40];
3702
3703 struct mlx5_ifc_eqc_bits eq_context_entry;
3704
3705 u8 reserved_2[0x40];
3706
3707 u8 event_bitmask[0x40];
3708
3709 u8 reserved_3[0x580];
3710
3711 u8 pas[0][0x40];
3712};
3713
3714struct mlx5_ifc_query_eq_in_bits {
3715 u8 opcode[0x10];
3716 u8 reserved_0[0x10];
3717
3718 u8 reserved_1[0x10];
3719 u8 op_mod[0x10];
3720
3721 u8 reserved_2[0x18];
3722 u8 eq_number[0x8];
3723
3724 u8 reserved_3[0x20];
3725};
3726
3727struct mlx5_ifc_query_dct_out_bits {
3728 u8 status[0x8];
3729 u8 reserved_0[0x18];
3730
3731 u8 syndrome[0x20];
3732
3733 u8 reserved_1[0x40];
3734
3735 struct mlx5_ifc_dctc_bits dct_context_entry;
3736
3737 u8 reserved_2[0x180];
3738};
3739
3740struct mlx5_ifc_query_dct_in_bits {
3741 u8 opcode[0x10];
3742 u8 reserved_0[0x10];
3743
3744 u8 reserved_1[0x10];
3745 u8 op_mod[0x10];
3746
3747 u8 reserved_2[0x8];
3748 u8 dctn[0x18];
3749
3750 u8 reserved_3[0x20];
3751};
3752
3753struct mlx5_ifc_query_cq_out_bits {
3754 u8 status[0x8];
3755 u8 reserved_0[0x18];
3756
3757 u8 syndrome[0x20];
3758
3759 u8 reserved_1[0x40];
3760
3761 struct mlx5_ifc_cqc_bits cq_context;
3762
3763 u8 reserved_2[0x600];
3764
3765 u8 pas[0][0x40];
3766};
3767
3768struct mlx5_ifc_query_cq_in_bits {
3769 u8 opcode[0x10];
3770 u8 reserved_0[0x10];
3771
3772 u8 reserved_1[0x10];
3773 u8 op_mod[0x10];
3774
3775 u8 reserved_2[0x8];
3776 u8 cqn[0x18];
3777
3778 u8 reserved_3[0x20];
3779};
3780
3781struct mlx5_ifc_query_cong_status_out_bits {
3782 u8 status[0x8];
3783 u8 reserved_0[0x18];
3784
3785 u8 syndrome[0x20];
3786
3787 u8 reserved_1[0x20];
3788
3789 u8 enable[0x1];
3790 u8 tag_enable[0x1];
3791 u8 reserved_2[0x1e];
3792};
3793
3794struct mlx5_ifc_query_cong_status_in_bits {
3795 u8 opcode[0x10];
3796 u8 reserved_0[0x10];
3797
3798 u8 reserved_1[0x10];
3799 u8 op_mod[0x10];
3800
3801 u8 reserved_2[0x18];
3802 u8 priority[0x4];
3803 u8 cong_protocol[0x4];
3804
3805 u8 reserved_3[0x20];
3806};
3807
3808struct mlx5_ifc_query_cong_statistics_out_bits {
3809 u8 status[0x8];
3810 u8 reserved_0[0x18];
3811
3812 u8 syndrome[0x20];
3813
3814 u8 reserved_1[0x40];
3815
3816 u8 cur_flows[0x20];
3817
3818 u8 sum_flows[0x20];
3819
3820 u8 cnp_ignored_high[0x20];
3821
3822 u8 cnp_ignored_low[0x20];
3823
3824 u8 cnp_handled_high[0x20];
3825
3826 u8 cnp_handled_low[0x20];
3827
3828 u8 reserved_2[0x100];
3829
3830 u8 time_stamp_high[0x20];
3831
3832 u8 time_stamp_low[0x20];
3833
3834 u8 accumulators_period[0x20];
3835
3836 u8 ecn_marked_roce_packets_high[0x20];
3837
3838 u8 ecn_marked_roce_packets_low[0x20];
3839
3840 u8 cnps_sent_high[0x20];
3841
3842 u8 cnps_sent_low[0x20];
3843
3844 u8 reserved_3[0x560];
3845};
3846
3847struct mlx5_ifc_query_cong_statistics_in_bits {
3848 u8 opcode[0x10];
3849 u8 reserved_0[0x10];
3850
3851 u8 reserved_1[0x10];
3852 u8 op_mod[0x10];
3853
3854 u8 clear[0x1];
3855 u8 reserved_2[0x1f];
3856
3857 u8 reserved_3[0x20];
3858};
3859
3860struct mlx5_ifc_query_cong_params_out_bits {
3861 u8 status[0x8];
3862 u8 reserved_0[0x18];
3863
3864 u8 syndrome[0x20];
3865
3866 u8 reserved_1[0x40];
3867
3868 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
3869};
3870
3871struct mlx5_ifc_query_cong_params_in_bits {
3872 u8 opcode[0x10];
3873 u8 reserved_0[0x10];
3874
3875 u8 reserved_1[0x10];
3876 u8 op_mod[0x10];
3877
3878 u8 reserved_2[0x1c];
3879 u8 cong_protocol[0x4];
3880
3881 u8 reserved_3[0x20];
3882};
3883
3884struct mlx5_ifc_query_adapter_out_bits {
341 u8 status[0x8]; 3885 u8 status[0x8];
342 u8 reserved_0[0x18]; 3886 u8 reserved_0[0x18];
343 3887
344 u8 syndrome[0x20]; 3888 u8 syndrome[0x20];
345 3889
346 u8 reserved_1[0x40]; 3890 u8 reserved_1[0x40];
3891
3892 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
3893};
3894
3895struct mlx5_ifc_query_adapter_in_bits {
3896 u8 opcode[0x10];
3897 u8 reserved_0[0x10];
3898
3899 u8 reserved_1[0x10];
3900 u8 op_mod[0x10];
3901
3902 u8 reserved_2[0x40];
3903};
3904
3905struct mlx5_ifc_qp_2rst_out_bits {
3906 u8 status[0x8];
3907 u8 reserved_0[0x18];
3908
3909 u8 syndrome[0x20];
3910
3911 u8 reserved_1[0x40];
3912};
3913
3914struct mlx5_ifc_qp_2rst_in_bits {
3915 u8 opcode[0x10];
3916 u8 reserved_0[0x10];
3917
3918 u8 reserved_1[0x10];
3919 u8 op_mod[0x10];
3920
3921 u8 reserved_2[0x8];
3922 u8 qpn[0x18];
3923
3924 u8 reserved_3[0x20];
3925};
3926
3927struct mlx5_ifc_qp_2err_out_bits {
3928 u8 status[0x8];
3929 u8 reserved_0[0x18];
3930
3931 u8 syndrome[0x20];
3932
3933 u8 reserved_1[0x40];
3934};
3935
3936struct mlx5_ifc_qp_2err_in_bits {
3937 u8 opcode[0x10];
3938 u8 reserved_0[0x10];
3939
3940 u8 reserved_1[0x10];
3941 u8 op_mod[0x10];
3942
3943 u8 reserved_2[0x8];
3944 u8 qpn[0x18];
3945
3946 u8 reserved_3[0x20];
3947};
3948
3949struct mlx5_ifc_page_fault_resume_out_bits {
3950 u8 status[0x8];
3951 u8 reserved_0[0x18];
3952
3953 u8 syndrome[0x20];
3954
3955 u8 reserved_1[0x40];
3956};
3957
3958struct mlx5_ifc_page_fault_resume_in_bits {
3959 u8 opcode[0x10];
3960 u8 reserved_0[0x10];
3961
3962 u8 reserved_1[0x10];
3963 u8 op_mod[0x10];
3964
3965 u8 error[0x1];
3966 u8 reserved_2[0x4];
3967 u8 rdma[0x1];
3968 u8 read_write[0x1];
3969 u8 req_res[0x1];
3970 u8 qpn[0x18];
3971
3972 u8 reserved_3[0x20];
3973};
3974
3975struct mlx5_ifc_nop_out_bits {
3976 u8 status[0x8];
3977 u8 reserved_0[0x18];
3978
3979 u8 syndrome[0x20];
3980
3981 u8 reserved_1[0x40];
3982};
3983
3984struct mlx5_ifc_nop_in_bits {
3985 u8 opcode[0x10];
3986 u8 reserved_0[0x10];
3987
3988 u8 reserved_1[0x10];
3989 u8 op_mod[0x10];
3990
3991 u8 reserved_2[0x40];
3992};
3993
3994struct mlx5_ifc_modify_vport_state_out_bits {
3995 u8 status[0x8];
3996 u8 reserved_0[0x18];
3997
3998 u8 syndrome[0x20];
3999
4000 u8 reserved_1[0x40];
4001};
4002
4003struct mlx5_ifc_modify_vport_state_in_bits {
4004 u8 opcode[0x10];
4005 u8 reserved_0[0x10];
4006
4007 u8 reserved_1[0x10];
4008 u8 op_mod[0x10];
4009
4010 u8 other_vport[0x1];
4011 u8 reserved_2[0xf];
4012 u8 vport_number[0x10];
4013
4014 u8 reserved_3[0x18];
4015 u8 admin_state[0x4];
4016 u8 reserved_4[0x4];
4017};
4018
4019struct mlx5_ifc_modify_tis_out_bits {
4020 u8 status[0x8];
4021 u8 reserved_0[0x18];
4022
4023 u8 syndrome[0x20];
4024
4025 u8 reserved_1[0x40];
4026};
4027
4028struct mlx5_ifc_modify_tis_in_bits {
4029 u8 opcode[0x10];
4030 u8 reserved_0[0x10];
4031
4032 u8 reserved_1[0x10];
4033 u8 op_mod[0x10];
4034
4035 u8 reserved_2[0x8];
4036 u8 tisn[0x18];
4037
4038 u8 reserved_3[0x20];
4039
4040 u8 modify_bitmask[0x40];
4041
4042 u8 reserved_4[0x40];
4043
4044 struct mlx5_ifc_tisc_bits ctx;
4045};
4046
4047struct mlx5_ifc_modify_tir_out_bits {
4048 u8 status[0x8];
4049 u8 reserved_0[0x18];
4050
4051 u8 syndrome[0x20];
4052
4053 u8 reserved_1[0x40];
4054};
4055
4056struct mlx5_ifc_modify_tir_in_bits {
4057 u8 opcode[0x10];
4058 u8 reserved_0[0x10];
4059
4060 u8 reserved_1[0x10];
4061 u8 op_mod[0x10];
4062
4063 u8 reserved_2[0x8];
4064 u8 tirn[0x18];
4065
4066 u8 reserved_3[0x20];
4067
4068 u8 modify_bitmask[0x40];
4069
4070 u8 reserved_4[0x40];
4071
4072 struct mlx5_ifc_tirc_bits ctx;
4073};
4074
4075struct mlx5_ifc_modify_sq_out_bits {
4076 u8 status[0x8];
4077 u8 reserved_0[0x18];
4078
4079 u8 syndrome[0x20];
4080
4081 u8 reserved_1[0x40];
4082};
4083
4084struct mlx5_ifc_modify_sq_in_bits {
4085 u8 opcode[0x10];
4086 u8 reserved_0[0x10];
4087
4088 u8 reserved_1[0x10];
4089 u8 op_mod[0x10];
4090
4091 u8 sq_state[0x4];
4092 u8 reserved_2[0x4];
4093 u8 sqn[0x18];
4094
4095 u8 reserved_3[0x20];
4096
4097 u8 modify_bitmask[0x40];
4098
4099 u8 reserved_4[0x40];
4100
4101 struct mlx5_ifc_sqc_bits ctx;
4102};
4103
4104struct mlx5_ifc_modify_rqt_out_bits {
4105 u8 status[0x8];
4106 u8 reserved_0[0x18];
4107
4108 u8 syndrome[0x20];
4109
4110 u8 reserved_1[0x40];
4111};
4112
4113struct mlx5_ifc_modify_rqt_in_bits {
4114 u8 opcode[0x10];
4115 u8 reserved_0[0x10];
4116
4117 u8 reserved_1[0x10];
4118 u8 op_mod[0x10];
4119
4120 u8 reserved_2[0x8];
4121 u8 rqtn[0x18];
4122
4123 u8 reserved_3[0x20];
4124
4125 u8 modify_bitmask[0x40];
4126
4127 u8 reserved_4[0x40];
4128
4129 struct mlx5_ifc_rqtc_bits ctx;
4130};
4131
4132struct mlx5_ifc_modify_rq_out_bits {
4133 u8 status[0x8];
4134 u8 reserved_0[0x18];
4135
4136 u8 syndrome[0x20];
4137
4138 u8 reserved_1[0x40];
4139};
4140
4141struct mlx5_ifc_modify_rq_in_bits {
4142 u8 opcode[0x10];
4143 u8 reserved_0[0x10];
4144
4145 u8 reserved_1[0x10];
4146 u8 op_mod[0x10];
4147
4148 u8 rq_state[0x4];
4149 u8 reserved_2[0x4];
4150 u8 rqn[0x18];
4151
4152 u8 reserved_3[0x20];
4153
4154 u8 modify_bitmask[0x40];
4155
4156 u8 reserved_4[0x40];
4157
4158 struct mlx5_ifc_rqc_bits ctx;
4159};
4160
4161struct mlx5_ifc_modify_rmp_out_bits {
4162 u8 status[0x8];
4163 u8 reserved_0[0x18];
4164
4165 u8 syndrome[0x20];
4166
4167 u8 reserved_1[0x40];
4168};
4169
4170struct mlx5_ifc_modify_rmp_in_bits {
4171 u8 opcode[0x10];
4172 u8 reserved_0[0x10];
4173
4174 u8 reserved_1[0x10];
4175 u8 op_mod[0x10];
4176
4177 u8 rmp_state[0x4];
4178 u8 reserved_2[0x4];
4179 u8 rmpn[0x18];
4180
4181 u8 reserved_3[0x20];
4182
4183 u8 modify_bitmask[0x40];
4184
4185 u8 reserved_4[0x40];
4186
4187 struct mlx5_ifc_rmpc_bits ctx;
4188};
4189
4190struct mlx5_ifc_modify_nic_vport_context_out_bits {
4191 u8 status[0x8];
4192 u8 reserved_0[0x18];
4193
4194 u8 syndrome[0x20];
4195
4196 u8 reserved_1[0x40];
4197};
4198
4199struct mlx5_ifc_modify_nic_vport_field_select_bits {
4200 u8 reserved_0[0x1c];
4201 u8 permanent_address[0x1];
4202 u8 addresses_list[0x1];
4203 u8 roce_en[0x1];
4204 u8 reserved_1[0x1];
4205};
4206
4207struct mlx5_ifc_modify_nic_vport_context_in_bits {
4208 u8 opcode[0x10];
4209 u8 reserved_0[0x10];
4210
4211 u8 reserved_1[0x10];
4212 u8 op_mod[0x10];
4213
4214 u8 other_vport[0x1];
4215 u8 reserved_2[0xf];
4216 u8 vport_number[0x10];
4217
4218 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
4219
4220 u8 reserved_3[0x780];
4221
4222 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4223};
4224
4225struct mlx5_ifc_modify_hca_vport_context_out_bits {
4226 u8 status[0x8];
4227 u8 reserved_0[0x18];
4228
4229 u8 syndrome[0x20];
4230
4231 u8 reserved_1[0x40];
4232};
4233
4234struct mlx5_ifc_modify_hca_vport_context_in_bits {
4235 u8 opcode[0x10];
4236 u8 reserved_0[0x10];
4237
4238 u8 reserved_1[0x10];
4239 u8 op_mod[0x10];
4240
4241 u8 other_vport[0x1];
4242 u8 reserved_2[0xf];
4243 u8 vport_number[0x10];
4244
4245 u8 reserved_3[0x20];
4246
4247 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4248};
4249
4250struct mlx5_ifc_modify_cq_out_bits {
4251 u8 status[0x8];
4252 u8 reserved_0[0x18];
4253
4254 u8 syndrome[0x20];
4255
4256 u8 reserved_1[0x40];
4257};
4258
4259enum {
4260 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
4261 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
4262};
4263
4264struct mlx5_ifc_modify_cq_in_bits {
4265 u8 opcode[0x10];
4266 u8 reserved_0[0x10];
4267
4268 u8 reserved_1[0x10];
4269 u8 op_mod[0x10];
4270
4271 u8 reserved_2[0x8];
4272 u8 cqn[0x18];
4273
4274 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
4275
4276 struct mlx5_ifc_cqc_bits cq_context;
4277
4278 u8 reserved_3[0x600];
4279
4280 u8 pas[0][0x40];
4281};
4282
4283struct mlx5_ifc_modify_cong_status_out_bits {
4284 u8 status[0x8];
4285 u8 reserved_0[0x18];
4286
4287 u8 syndrome[0x20];
4288
4289 u8 reserved_1[0x40];
4290};
4291
4292struct mlx5_ifc_modify_cong_status_in_bits {
4293 u8 opcode[0x10];
4294 u8 reserved_0[0x10];
4295
4296 u8 reserved_1[0x10];
4297 u8 op_mod[0x10];
4298
4299 u8 reserved_2[0x18];
4300 u8 priority[0x4];
4301 u8 cong_protocol[0x4];
4302
4303 u8 enable[0x1];
4304 u8 tag_enable[0x1];
4305 u8 reserved_3[0x1e];
4306};
4307
4308struct mlx5_ifc_modify_cong_params_out_bits {
4309 u8 status[0x8];
4310 u8 reserved_0[0x18];
4311
4312 u8 syndrome[0x20];
4313
4314 u8 reserved_1[0x40];
4315};
4316
4317struct mlx5_ifc_modify_cong_params_in_bits {
4318 u8 opcode[0x10];
4319 u8 reserved_0[0x10];
4320
4321 u8 reserved_1[0x10];
4322 u8 op_mod[0x10];
4323
4324 u8 reserved_2[0x1c];
4325 u8 cong_protocol[0x4];
4326
4327 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
4328
4329 u8 reserved_3[0x80];
4330
4331 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4332};
4333
4334struct mlx5_ifc_manage_pages_out_bits {
4335 u8 status[0x8];
4336 u8 reserved_0[0x18];
4337
4338 u8 syndrome[0x20];
4339
4340 u8 output_num_entries[0x20];
4341
4342 u8 reserved_1[0x20];
4343
4344 u8 pas[0][0x40];
4345};
4346
4347enum {
4348 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
4349 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
4350 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
4351};
4352
4353struct mlx5_ifc_manage_pages_in_bits {
4354 u8 opcode[0x10];
4355 u8 reserved_0[0x10];
4356
4357 u8 reserved_1[0x10];
4358 u8 op_mod[0x10];
4359
4360 u8 reserved_2[0x10];
4361 u8 function_id[0x10];
4362
4363 u8 input_num_entries[0x20];
4364
4365 u8 pas[0][0x40];
4366};
4367
4368struct mlx5_ifc_mad_ifc_out_bits {
4369 u8 status[0x8];
4370 u8 reserved_0[0x18];
4371
4372 u8 syndrome[0x20];
4373
4374 u8 reserved_1[0x40];
4375
4376 u8 response_mad_packet[256][0x8];
4377};
4378
4379struct mlx5_ifc_mad_ifc_in_bits {
4380 u8 opcode[0x10];
4381 u8 reserved_0[0x10];
4382
4383 u8 reserved_1[0x10];
4384 u8 op_mod[0x10];
4385
4386 u8 remote_lid[0x10];
4387 u8 reserved_2[0x8];
4388 u8 port[0x8];
4389
4390 u8 reserved_3[0x20];
4391
4392 u8 mad[256][0x8];
4393};
4394
4395struct mlx5_ifc_init_hca_out_bits {
4396 u8 status[0x8];
4397 u8 reserved_0[0x18];
4398
4399 u8 syndrome[0x20];
4400
4401 u8 reserved_1[0x40];
4402};
4403
4404struct mlx5_ifc_init_hca_in_bits {
4405 u8 opcode[0x10];
4406 u8 reserved_0[0x10];
4407
4408 u8 reserved_1[0x10];
4409 u8 op_mod[0x10];
4410
4411 u8 reserved_2[0x40];
4412};
4413
4414struct mlx5_ifc_init2rtr_qp_out_bits {
4415 u8 status[0x8];
4416 u8 reserved_0[0x18];
4417
4418 u8 syndrome[0x20];
4419
4420 u8 reserved_1[0x40];
4421};
4422
4423struct mlx5_ifc_init2rtr_qp_in_bits {
4424 u8 opcode[0x10];
4425 u8 reserved_0[0x10];
4426
4427 u8 reserved_1[0x10];
4428 u8 op_mod[0x10];
4429
4430 u8 reserved_2[0x8];
4431 u8 qpn[0x18];
4432
4433 u8 reserved_3[0x20];
4434
4435 u8 opt_param_mask[0x20];
4436
4437 u8 reserved_4[0x20];
4438
4439 struct mlx5_ifc_qpc_bits qpc;
4440
4441 u8 reserved_5[0x80];
4442};
4443
4444struct mlx5_ifc_init2init_qp_out_bits {
4445 u8 status[0x8];
4446 u8 reserved_0[0x18];
4447
4448 u8 syndrome[0x20];
4449
4450 u8 reserved_1[0x40];
4451};
4452
4453struct mlx5_ifc_init2init_qp_in_bits {
4454 u8 opcode[0x10];
4455 u8 reserved_0[0x10];
4456
4457 u8 reserved_1[0x10];
4458 u8 op_mod[0x10];
4459
4460 u8 reserved_2[0x8];
4461 u8 qpn[0x18];
4462
4463 u8 reserved_3[0x20];
4464
4465 u8 opt_param_mask[0x20];
4466
4467 u8 reserved_4[0x20];
4468
4469 struct mlx5_ifc_qpc_bits qpc;
4470
4471 u8 reserved_5[0x80];
4472};
4473
4474struct mlx5_ifc_get_dropped_packet_log_out_bits {
4475 u8 status[0x8];
4476 u8 reserved_0[0x18];
4477
4478 u8 syndrome[0x20];
4479
4480 u8 reserved_1[0x40];
4481
4482 u8 packet_headers_log[128][0x8];
4483
4484 u8 packet_syndrome[64][0x8];
4485};
4486
4487struct mlx5_ifc_get_dropped_packet_log_in_bits {
4488 u8 opcode[0x10];
4489 u8 reserved_0[0x10];
4490
4491 u8 reserved_1[0x10];
4492 u8 op_mod[0x10];
4493
4494 u8 reserved_2[0x40];
4495};
4496
4497struct mlx5_ifc_gen_eqe_in_bits {
4498 u8 opcode[0x10];
4499 u8 reserved_0[0x10];
4500
4501 u8 reserved_1[0x10];
4502 u8 op_mod[0x10];
4503
4504 u8 reserved_2[0x18];
4505 u8 eq_number[0x8];
4506
4507 u8 reserved_3[0x20];
4508
4509 u8 eqe[64][0x8];
4510};
4511
4512struct mlx5_ifc_gen_eq_out_bits {
4513 u8 status[0x8];
4514 u8 reserved_0[0x18];
4515
4516 u8 syndrome[0x20];
4517
4518 u8 reserved_1[0x40];
4519};
4520
4521struct mlx5_ifc_enable_hca_out_bits {
4522 u8 status[0x8];
4523 u8 reserved_0[0x18];
4524
4525 u8 syndrome[0x20];
4526
4527 u8 reserved_1[0x20];
4528};
4529
4530struct mlx5_ifc_enable_hca_in_bits {
4531 u8 opcode[0x10];
4532 u8 reserved_0[0x10];
4533
4534 u8 reserved_1[0x10];
4535 u8 op_mod[0x10];
4536
4537 u8 reserved_2[0x10];
4538 u8 function_id[0x10];
4539
4540 u8 reserved_3[0x20];
4541};
4542
4543struct mlx5_ifc_drain_dct_out_bits {
4544 u8 status[0x8];
4545 u8 reserved_0[0x18];
4546
4547 u8 syndrome[0x20];
4548
4549 u8 reserved_1[0x40];
4550};
4551
4552struct mlx5_ifc_drain_dct_in_bits {
4553 u8 opcode[0x10];
4554 u8 reserved_0[0x10];
4555
4556 u8 reserved_1[0x10];
4557 u8 op_mod[0x10];
4558
4559 u8 reserved_2[0x8];
4560 u8 dctn[0x18];
4561
4562 u8 reserved_3[0x20];
4563};
4564
4565struct mlx5_ifc_disable_hca_out_bits {
4566 u8 status[0x8];
4567 u8 reserved_0[0x18];
4568
4569 u8 syndrome[0x20];
4570
4571 u8 reserved_1[0x20];
4572};
4573
4574struct mlx5_ifc_disable_hca_in_bits {
4575 u8 opcode[0x10];
4576 u8 reserved_0[0x10];
4577
4578 u8 reserved_1[0x10];
4579 u8 op_mod[0x10];
4580
4581 u8 reserved_2[0x10];
4582 u8 function_id[0x10];
4583
4584 u8 reserved_3[0x20];
4585};
4586
4587struct mlx5_ifc_detach_from_mcg_out_bits {
4588 u8 status[0x8];
4589 u8 reserved_0[0x18];
4590
4591 u8 syndrome[0x20];
4592
4593 u8 reserved_1[0x40];
4594};
4595
4596struct mlx5_ifc_detach_from_mcg_in_bits {
4597 u8 opcode[0x10];
4598 u8 reserved_0[0x10];
4599
4600 u8 reserved_1[0x10];
4601 u8 op_mod[0x10];
4602
4603 u8 reserved_2[0x8];
4604 u8 qpn[0x18];
4605
4606 u8 reserved_3[0x20];
4607
4608 u8 multicast_gid[16][0x8];
4609};
4610
4611struct mlx5_ifc_destroy_xrc_srq_out_bits {
4612 u8 status[0x8];
4613 u8 reserved_0[0x18];
4614
4615 u8 syndrome[0x20];
4616
4617 u8 reserved_1[0x40];
4618};
4619
4620struct mlx5_ifc_destroy_xrc_srq_in_bits {
4621 u8 opcode[0x10];
4622 u8 reserved_0[0x10];
4623
4624 u8 reserved_1[0x10];
4625 u8 op_mod[0x10];
4626
4627 u8 reserved_2[0x8];
4628 u8 xrc_srqn[0x18];
4629
4630 u8 reserved_3[0x20];
4631};
4632
4633struct mlx5_ifc_destroy_tis_out_bits {
4634 u8 status[0x8];
4635 u8 reserved_0[0x18];
4636
4637 u8 syndrome[0x20];
4638
4639 u8 reserved_1[0x40];
4640};
4641
4642struct mlx5_ifc_destroy_tis_in_bits {
4643 u8 opcode[0x10];
4644 u8 reserved_0[0x10];
4645
4646 u8 reserved_1[0x10];
4647 u8 op_mod[0x10];
4648
4649 u8 reserved_2[0x8];
4650 u8 tisn[0x18];
4651
4652 u8 reserved_3[0x20];
4653};
4654
4655struct mlx5_ifc_destroy_tir_out_bits {
4656 u8 status[0x8];
4657 u8 reserved_0[0x18];
4658
4659 u8 syndrome[0x20];
4660
4661 u8 reserved_1[0x40];
4662};
4663
4664struct mlx5_ifc_destroy_tir_in_bits {
4665 u8 opcode[0x10];
4666 u8 reserved_0[0x10];
4667
4668 u8 reserved_1[0x10];
4669 u8 op_mod[0x10];
4670
4671 u8 reserved_2[0x8];
4672 u8 tirn[0x18];
4673
4674 u8 reserved_3[0x20];
4675};
4676
4677struct mlx5_ifc_destroy_srq_out_bits {
4678 u8 status[0x8];
4679 u8 reserved_0[0x18];
4680
4681 u8 syndrome[0x20];
4682
4683 u8 reserved_1[0x40];
4684};
4685
4686struct mlx5_ifc_destroy_srq_in_bits {
4687 u8 opcode[0x10];
4688 u8 reserved_0[0x10];
4689
4690 u8 reserved_1[0x10];
4691 u8 op_mod[0x10];
4692
4693 u8 reserved_2[0x8];
4694 u8 srqn[0x18];
4695
4696 u8 reserved_3[0x20];
4697};
4698
4699struct mlx5_ifc_destroy_sq_out_bits {
4700 u8 status[0x8];
4701 u8 reserved_0[0x18];
4702
4703 u8 syndrome[0x20];
4704
4705 u8 reserved_1[0x40];
4706};
4707
4708struct mlx5_ifc_destroy_sq_in_bits {
4709 u8 opcode[0x10];
4710 u8 reserved_0[0x10];
4711
4712 u8 reserved_1[0x10];
4713 u8 op_mod[0x10];
4714
4715 u8 reserved_2[0x8];
4716 u8 sqn[0x18];
4717
4718 u8 reserved_3[0x20];
4719};
4720
4721struct mlx5_ifc_destroy_rqt_out_bits {
4722 u8 status[0x8];
4723 u8 reserved_0[0x18];
4724
4725 u8 syndrome[0x20];
4726
4727 u8 reserved_1[0x40];
4728};
4729
4730struct mlx5_ifc_destroy_rqt_in_bits {
4731 u8 opcode[0x10];
4732 u8 reserved_0[0x10];
4733
4734 u8 reserved_1[0x10];
4735 u8 op_mod[0x10];
4736
4737 u8 reserved_2[0x8];
4738 u8 rqtn[0x18];
4739
4740 u8 reserved_3[0x20];
4741};
4742
4743struct mlx5_ifc_destroy_rq_out_bits {
4744 u8 status[0x8];
4745 u8 reserved_0[0x18];
4746
4747 u8 syndrome[0x20];
4748
4749 u8 reserved_1[0x40];
4750};
4751
4752struct mlx5_ifc_destroy_rq_in_bits {
4753 u8 opcode[0x10];
4754 u8 reserved_0[0x10];
4755
4756 u8 reserved_1[0x10];
4757 u8 op_mod[0x10];
4758
4759 u8 reserved_2[0x8];
4760 u8 rqn[0x18];
4761
4762 u8 reserved_3[0x20];
4763};
4764
4765struct mlx5_ifc_destroy_rmp_out_bits {
4766 u8 status[0x8];
4767 u8 reserved_0[0x18];
4768
4769 u8 syndrome[0x20];
4770
4771 u8 reserved_1[0x40];
4772};
4773
4774struct mlx5_ifc_destroy_rmp_in_bits {
4775 u8 opcode[0x10];
4776 u8 reserved_0[0x10];
4777
4778 u8 reserved_1[0x10];
4779 u8 op_mod[0x10];
4780
4781 u8 reserved_2[0x8];
4782 u8 rmpn[0x18];
4783
4784 u8 reserved_3[0x20];
4785};
4786
4787struct mlx5_ifc_destroy_qp_out_bits {
4788 u8 status[0x8];
4789 u8 reserved_0[0x18];
4790
4791 u8 syndrome[0x20];
4792
4793 u8 reserved_1[0x40];
4794};
4795
4796struct mlx5_ifc_destroy_qp_in_bits {
4797 u8 opcode[0x10];
4798 u8 reserved_0[0x10];
4799
4800 u8 reserved_1[0x10];
4801 u8 op_mod[0x10];
4802
4803 u8 reserved_2[0x8];
4804 u8 qpn[0x18];
4805
4806 u8 reserved_3[0x20];
4807};
4808
4809struct mlx5_ifc_destroy_psv_out_bits {
4810 u8 status[0x8];
4811 u8 reserved_0[0x18];
4812
4813 u8 syndrome[0x20];
4814
4815 u8 reserved_1[0x40];
4816};
4817
4818struct mlx5_ifc_destroy_psv_in_bits {
4819 u8 opcode[0x10];
4820 u8 reserved_0[0x10];
4821
4822 u8 reserved_1[0x10];
4823 u8 op_mod[0x10];
4824
4825 u8 reserved_2[0x8];
4826 u8 psvn[0x18];
4827
4828 u8 reserved_3[0x20];
4829};
4830
4831struct mlx5_ifc_destroy_mkey_out_bits {
4832 u8 status[0x8];
4833 u8 reserved_0[0x18];
4834
4835 u8 syndrome[0x20];
4836
4837 u8 reserved_1[0x40];
4838};
4839
4840struct mlx5_ifc_destroy_mkey_in_bits {
4841 u8 opcode[0x10];
4842 u8 reserved_0[0x10];
4843
4844 u8 reserved_1[0x10];
4845 u8 op_mod[0x10];
4846
4847 u8 reserved_2[0x8];
4848 u8 mkey_index[0x18];
4849
4850 u8 reserved_3[0x20];
4851};
4852
4853struct mlx5_ifc_destroy_flow_table_out_bits {
4854 u8 status[0x8];
4855 u8 reserved_0[0x18];
4856
4857 u8 syndrome[0x20];
4858
4859 u8 reserved_1[0x40];
4860};
4861
4862struct mlx5_ifc_destroy_flow_table_in_bits {
4863 u8 opcode[0x10];
4864 u8 reserved_0[0x10];
4865
4866 u8 reserved_1[0x10];
4867 u8 op_mod[0x10];
4868
4869 u8 reserved_2[0x40];
4870
4871 u8 table_type[0x8];
4872 u8 reserved_3[0x18];
4873
4874 u8 reserved_4[0x8];
4875 u8 table_id[0x18];
4876
4877 u8 reserved_5[0x140];
4878};
4879
4880struct mlx5_ifc_destroy_flow_group_out_bits {
4881 u8 status[0x8];
4882 u8 reserved_0[0x18];
4883
4884 u8 syndrome[0x20];
4885
4886 u8 reserved_1[0x40];
4887};
4888
4889struct mlx5_ifc_destroy_flow_group_in_bits {
4890 u8 opcode[0x10];
4891 u8 reserved_0[0x10];
4892
4893 u8 reserved_1[0x10];
4894 u8 op_mod[0x10];
4895
4896 u8 reserved_2[0x40];
4897
4898 u8 table_type[0x8];
4899 u8 reserved_3[0x18];
4900
4901 u8 reserved_4[0x8];
4902 u8 table_id[0x18];
4903
4904 u8 group_id[0x20];
4905
4906 u8 reserved_5[0x120];
4907};
4908
4909struct mlx5_ifc_destroy_eq_out_bits {
4910 u8 status[0x8];
4911 u8 reserved_0[0x18];
4912
4913 u8 syndrome[0x20];
4914
4915 u8 reserved_1[0x40];
4916};
4917
4918struct mlx5_ifc_destroy_eq_in_bits {
4919 u8 opcode[0x10];
4920 u8 reserved_0[0x10];
4921
4922 u8 reserved_1[0x10];
4923 u8 op_mod[0x10];
4924
4925 u8 reserved_2[0x18];
4926 u8 eq_number[0x8];
4927
4928 u8 reserved_3[0x20];
4929};
4930
4931struct mlx5_ifc_destroy_dct_out_bits {
4932 u8 status[0x8];
4933 u8 reserved_0[0x18];
4934
4935 u8 syndrome[0x20];
4936
4937 u8 reserved_1[0x40];
4938};
4939
4940struct mlx5_ifc_destroy_dct_in_bits {
4941 u8 opcode[0x10];
4942 u8 reserved_0[0x10];
4943
4944 u8 reserved_1[0x10];
4945 u8 op_mod[0x10];
4946
4947 u8 reserved_2[0x8];
4948 u8 dctn[0x18];
4949
4950 u8 reserved_3[0x20];
4951};
4952
4953struct mlx5_ifc_destroy_cq_out_bits {
4954 u8 status[0x8];
4955 u8 reserved_0[0x18];
4956
4957 u8 syndrome[0x20];
4958
4959 u8 reserved_1[0x40];
4960};
4961
4962struct mlx5_ifc_destroy_cq_in_bits {
4963 u8 opcode[0x10];
4964 u8 reserved_0[0x10];
4965
4966 u8 reserved_1[0x10];
4967 u8 op_mod[0x10];
4968
4969 u8 reserved_2[0x8];
4970 u8 cqn[0x18];
4971
4972 u8 reserved_3[0x20];
4973};
4974
4975struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
4976 u8 status[0x8];
4977 u8 reserved_0[0x18];
4978
4979 u8 syndrome[0x20];
4980
4981 u8 reserved_1[0x40];
4982};
4983
4984struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
4985 u8 opcode[0x10];
4986 u8 reserved_0[0x10];
4987
4988 u8 reserved_1[0x10];
4989 u8 op_mod[0x10];
4990
4991 u8 reserved_2[0x20];
4992
4993 u8 reserved_3[0x10];
4994 u8 vxlan_udp_port[0x10];
4995};
4996
4997struct mlx5_ifc_delete_l2_table_entry_out_bits {
4998 u8 status[0x8];
4999 u8 reserved_0[0x18];
5000
5001 u8 syndrome[0x20];
5002
5003 u8 reserved_1[0x40];
5004};
5005
5006struct mlx5_ifc_delete_l2_table_entry_in_bits {
5007 u8 opcode[0x10];
5008 u8 reserved_0[0x10];
5009
5010 u8 reserved_1[0x10];
5011 u8 op_mod[0x10];
5012
5013 u8 reserved_2[0x60];
5014
5015 u8 reserved_3[0x8];
5016 u8 table_index[0x18];
5017
5018 u8 reserved_4[0x140];
5019};
5020
5021struct mlx5_ifc_delete_fte_out_bits {
5022 u8 status[0x8];
5023 u8 reserved_0[0x18];
5024
5025 u8 syndrome[0x20];
5026
5027 u8 reserved_1[0x40];
5028};
5029
5030struct mlx5_ifc_delete_fte_in_bits {
5031 u8 opcode[0x10];
5032 u8 reserved_0[0x10];
5033
5034 u8 reserved_1[0x10];
5035 u8 op_mod[0x10];
5036
5037 u8 reserved_2[0x40];
5038
5039 u8 table_type[0x8];
5040 u8 reserved_3[0x18];
5041
5042 u8 reserved_4[0x8];
5043 u8 table_id[0x18];
5044
5045 u8 reserved_5[0x40];
5046
5047 u8 flow_index[0x20];
5048
5049 u8 reserved_6[0xe0];
5050};
5051
5052struct mlx5_ifc_dealloc_xrcd_out_bits {
5053 u8 status[0x8];
5054 u8 reserved_0[0x18];
5055
5056 u8 syndrome[0x20];
5057
5058 u8 reserved_1[0x40];
5059};
5060
5061struct mlx5_ifc_dealloc_xrcd_in_bits {
5062 u8 opcode[0x10];
5063 u8 reserved_0[0x10];
5064
5065 u8 reserved_1[0x10];
5066 u8 op_mod[0x10];
5067
5068 u8 reserved_2[0x8];
5069 u8 xrcd[0x18];
5070
5071 u8 reserved_3[0x20];
5072};
5073
5074struct mlx5_ifc_dealloc_uar_out_bits {
5075 u8 status[0x8];
5076 u8 reserved_0[0x18];
5077
5078 u8 syndrome[0x20];
5079
5080 u8 reserved_1[0x40];
5081};
5082
5083struct mlx5_ifc_dealloc_uar_in_bits {
5084 u8 opcode[0x10];
5085 u8 reserved_0[0x10];
5086
5087 u8 reserved_1[0x10];
5088 u8 op_mod[0x10];
5089
5090 u8 reserved_2[0x8];
5091 u8 uar[0x18];
5092
5093 u8 reserved_3[0x20];
5094};
5095
5096struct mlx5_ifc_dealloc_transport_domain_out_bits {
5097 u8 status[0x8];
5098 u8 reserved_0[0x18];
5099
5100 u8 syndrome[0x20];
5101
5102 u8 reserved_1[0x40];
5103};
5104
5105struct mlx5_ifc_dealloc_transport_domain_in_bits {
5106 u8 opcode[0x10];
5107 u8 reserved_0[0x10];
5108
5109 u8 reserved_1[0x10];
5110 u8 op_mod[0x10];
5111
5112 u8 reserved_2[0x8];
5113 u8 transport_domain[0x18];
5114
5115 u8 reserved_3[0x20];
5116};
5117
5118struct mlx5_ifc_dealloc_q_counter_out_bits {
5119 u8 status[0x8];
5120 u8 reserved_0[0x18];
5121
5122 u8 syndrome[0x20];
5123
5124 u8 reserved_1[0x40];
5125};
5126
5127struct mlx5_ifc_dealloc_q_counter_in_bits {
5128 u8 opcode[0x10];
5129 u8 reserved_0[0x10];
5130
5131 u8 reserved_1[0x10];
5132 u8 op_mod[0x10];
5133
5134 u8 reserved_2[0x18];
5135 u8 counter_set_id[0x8];
5136
5137 u8 reserved_3[0x20];
5138};
5139
5140struct mlx5_ifc_dealloc_pd_out_bits {
5141 u8 status[0x8];
5142 u8 reserved_0[0x18];
5143
5144 u8 syndrome[0x20];
5145
5146 u8 reserved_1[0x40];
5147};
5148
5149struct mlx5_ifc_dealloc_pd_in_bits {
5150 u8 opcode[0x10];
5151 u8 reserved_0[0x10];
5152
5153 u8 reserved_1[0x10];
5154 u8 op_mod[0x10];
5155
5156 u8 reserved_2[0x8];
5157 u8 pd[0x18];
5158
5159 u8 reserved_3[0x20];
5160};
5161
5162struct mlx5_ifc_create_xrc_srq_out_bits {
5163 u8 status[0x8];
5164 u8 reserved_0[0x18];
5165
5166 u8 syndrome[0x20];
5167
5168 u8 reserved_1[0x8];
5169 u8 xrc_srqn[0x18];
5170
5171 u8 reserved_2[0x20];
5172};
5173
5174struct mlx5_ifc_create_xrc_srq_in_bits {
5175 u8 opcode[0x10];
5176 u8 reserved_0[0x10];
5177
5178 u8 reserved_1[0x10];
5179 u8 op_mod[0x10];
5180
5181 u8 reserved_2[0x40];
5182
5183 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
5184
5185 u8 reserved_3[0x600];
5186
5187 u8 pas[0][0x40];
5188};
5189
5190struct mlx5_ifc_create_tis_out_bits {
5191 u8 status[0x8];
5192 u8 reserved_0[0x18];
5193
5194 u8 syndrome[0x20];
5195
5196 u8 reserved_1[0x8];
5197 u8 tisn[0x18];
5198
5199 u8 reserved_2[0x20];
5200};
5201
5202struct mlx5_ifc_create_tis_in_bits {
5203 u8 opcode[0x10];
5204 u8 reserved_0[0x10];
5205
5206 u8 reserved_1[0x10];
5207 u8 op_mod[0x10];
5208
5209 u8 reserved_2[0xc0];
5210
5211 struct mlx5_ifc_tisc_bits ctx;
5212};
5213
5214struct mlx5_ifc_create_tir_out_bits {
5215 u8 status[0x8];
5216 u8 reserved_0[0x18];
5217
5218 u8 syndrome[0x20];
5219
5220 u8 reserved_1[0x8];
5221 u8 tirn[0x18];
5222
5223 u8 reserved_2[0x20];
5224};
5225
5226struct mlx5_ifc_create_tir_in_bits {
5227 u8 opcode[0x10];
5228 u8 reserved_0[0x10];
5229
5230 u8 reserved_1[0x10];
5231 u8 op_mod[0x10];
5232
5233 u8 reserved_2[0xc0];
5234
5235 struct mlx5_ifc_tirc_bits ctx;
5236};
5237
5238struct mlx5_ifc_create_srq_out_bits {
5239 u8 status[0x8];
5240 u8 reserved_0[0x18];
5241
5242 u8 syndrome[0x20];
5243
5244 u8 reserved_1[0x8];
5245 u8 srqn[0x18];
5246
5247 u8 reserved_2[0x20];
5248};
5249
5250struct mlx5_ifc_create_srq_in_bits {
5251 u8 opcode[0x10];
5252 u8 reserved_0[0x10];
5253
5254 u8 reserved_1[0x10];
5255 u8 op_mod[0x10];
5256
5257 u8 reserved_2[0x40];
5258
5259 struct mlx5_ifc_srqc_bits srq_context_entry;
5260
5261 u8 reserved_3[0x600];
5262
5263 u8 pas[0][0x40];
5264};
5265
5266struct mlx5_ifc_create_sq_out_bits {
5267 u8 status[0x8];
5268 u8 reserved_0[0x18];
5269
5270 u8 syndrome[0x20];
5271
5272 u8 reserved_1[0x8];
5273 u8 sqn[0x18];
5274
5275 u8 reserved_2[0x20];
5276};
5277
5278struct mlx5_ifc_create_sq_in_bits {
5279 u8 opcode[0x10];
5280 u8 reserved_0[0x10];
5281
5282 u8 reserved_1[0x10];
5283 u8 op_mod[0x10];
5284
5285 u8 reserved_2[0xc0];
5286
5287 struct mlx5_ifc_sqc_bits ctx;
5288};
5289
5290struct mlx5_ifc_create_rqt_out_bits {
5291 u8 status[0x8];
5292 u8 reserved_0[0x18];
5293
5294 u8 syndrome[0x20];
5295
5296 u8 reserved_1[0x8];
5297 u8 rqtn[0x18];
5298
5299 u8 reserved_2[0x20];
5300};
5301
5302struct mlx5_ifc_create_rqt_in_bits {
5303 u8 opcode[0x10];
5304 u8 reserved_0[0x10];
5305
5306 u8 reserved_1[0x10];
5307 u8 op_mod[0x10];
5308
5309 u8 reserved_2[0xc0];
5310
5311 struct mlx5_ifc_rqtc_bits rqt_context;
5312};
5313
5314struct mlx5_ifc_create_rq_out_bits {
5315 u8 status[0x8];
5316 u8 reserved_0[0x18];
5317
5318 u8 syndrome[0x20];
5319
5320 u8 reserved_1[0x8];
5321 u8 rqn[0x18];
5322
5323 u8 reserved_2[0x20];
5324};
5325
5326struct mlx5_ifc_create_rq_in_bits {
5327 u8 opcode[0x10];
5328 u8 reserved_0[0x10];
5329
5330 u8 reserved_1[0x10];
5331 u8 op_mod[0x10];
5332
5333 u8 reserved_2[0xc0];
5334
5335 struct mlx5_ifc_rqc_bits ctx;
5336};
5337
5338struct mlx5_ifc_create_rmp_out_bits {
5339 u8 status[0x8];
5340 u8 reserved_0[0x18];
5341
5342 u8 syndrome[0x20];
5343
5344 u8 reserved_1[0x8];
5345 u8 rmpn[0x18];
5346
5347 u8 reserved_2[0x20];
5348};
5349
5350struct mlx5_ifc_create_rmp_in_bits {
5351 u8 opcode[0x10];
5352 u8 reserved_0[0x10];
5353
5354 u8 reserved_1[0x10];
5355 u8 op_mod[0x10];
5356
5357 u8 reserved_2[0xc0];
5358
5359 struct mlx5_ifc_rmpc_bits ctx;
5360};
5361
5362struct mlx5_ifc_create_qp_out_bits {
5363 u8 status[0x8];
5364 u8 reserved_0[0x18];
5365
5366 u8 syndrome[0x20];
5367
5368 u8 reserved_1[0x8];
5369 u8 qpn[0x18];
5370
5371 u8 reserved_2[0x20];
5372};
5373
5374struct mlx5_ifc_create_qp_in_bits {
5375 u8 opcode[0x10];
5376 u8 reserved_0[0x10];
5377
5378 u8 reserved_1[0x10];
5379 u8 op_mod[0x10];
5380
5381 u8 reserved_2[0x40];
5382
5383 u8 opt_param_mask[0x20];
5384
5385 u8 reserved_3[0x20];
5386
5387 struct mlx5_ifc_qpc_bits qpc;
5388
5389 u8 reserved_4[0x80];
5390
5391 u8 pas[0][0x40];
5392};
5393
5394struct mlx5_ifc_create_psv_out_bits {
5395 u8 status[0x8];
5396 u8 reserved_0[0x18];
5397
5398 u8 syndrome[0x20];
5399
5400 u8 reserved_1[0x40];
5401
5402 u8 reserved_2[0x8];
5403 u8 psv0_index[0x18];
5404
5405 u8 reserved_3[0x8];
5406 u8 psv1_index[0x18];
5407
5408 u8 reserved_4[0x8];
5409 u8 psv2_index[0x18];
5410
5411 u8 reserved_5[0x8];
5412 u8 psv3_index[0x18];
5413};
5414
5415struct mlx5_ifc_create_psv_in_bits {
5416 u8 opcode[0x10];
5417 u8 reserved_0[0x10];
5418
5419 u8 reserved_1[0x10];
5420 u8 op_mod[0x10];
5421
5422 u8 num_psv[0x4];
5423 u8 reserved_2[0x4];
5424 u8 pd[0x18];
5425
5426 u8 reserved_3[0x20];
5427};
5428
5429struct mlx5_ifc_create_mkey_out_bits {
5430 u8 status[0x8];
5431 u8 reserved_0[0x18];
5432
5433 u8 syndrome[0x20];
5434
5435 u8 reserved_1[0x8];
5436 u8 mkey_index[0x18];
5437
5438 u8 reserved_2[0x20];
5439};
5440
5441struct mlx5_ifc_create_mkey_in_bits {
5442 u8 opcode[0x10];
5443 u8 reserved_0[0x10];
5444
5445 u8 reserved_1[0x10];
5446 u8 op_mod[0x10];
5447
5448 u8 reserved_2[0x20];
5449
5450 u8 pg_access[0x1];
5451 u8 reserved_3[0x1f];
5452
5453 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5454
5455 u8 reserved_4[0x80];
5456
5457 u8 translations_octword_actual_size[0x20];
5458
5459 u8 reserved_5[0x560];
5460
5461 u8 klm_pas_mtt[0][0x20];
5462};
5463
5464struct mlx5_ifc_create_flow_table_out_bits {
5465 u8 status[0x8];
5466 u8 reserved_0[0x18];
5467
5468 u8 syndrome[0x20];
5469
5470 u8 reserved_1[0x8];
5471 u8 table_id[0x18];
5472
5473 u8 reserved_2[0x20];
5474};
5475
5476struct mlx5_ifc_create_flow_table_in_bits {
5477 u8 opcode[0x10];
5478 u8 reserved_0[0x10];
5479
5480 u8 reserved_1[0x10];
5481 u8 op_mod[0x10];
5482
5483 u8 reserved_2[0x40];
5484
5485 u8 table_type[0x8];
5486 u8 reserved_3[0x18];
5487
5488 u8 reserved_4[0x20];
5489
5490 u8 reserved_5[0x8];
5491 u8 level[0x8];
5492 u8 reserved_6[0x8];
5493 u8 log_size[0x8];
5494
5495 u8 reserved_7[0x120];
5496};
5497
5498struct mlx5_ifc_create_flow_group_out_bits {
5499 u8 status[0x8];
5500 u8 reserved_0[0x18];
5501
5502 u8 syndrome[0x20];
5503
5504 u8 reserved_1[0x8];
5505 u8 group_id[0x18];
5506
5507 u8 reserved_2[0x20];
5508};
5509
5510enum {
5511 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
5512 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
5513 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
5514};
5515
5516struct mlx5_ifc_create_flow_group_in_bits {
5517 u8 opcode[0x10];
5518 u8 reserved_0[0x10];
5519
5520 u8 reserved_1[0x10];
5521 u8 op_mod[0x10];
5522
5523 u8 reserved_2[0x40];
5524
5525 u8 table_type[0x8];
5526 u8 reserved_3[0x18];
5527
5528 u8 reserved_4[0x8];
5529 u8 table_id[0x18];
5530
5531 u8 reserved_5[0x20];
5532
5533 u8 start_flow_index[0x20];
5534
5535 u8 reserved_6[0x20];
5536
5537 u8 end_flow_index[0x20];
5538
5539 u8 reserved_7[0xa0];
5540
5541 u8 reserved_8[0x18];
5542 u8 match_criteria_enable[0x8];
5543
5544 struct mlx5_ifc_fte_match_param_bits match_criteria;
5545
5546 u8 reserved_9[0xe00];
5547};
5548
5549struct mlx5_ifc_create_eq_out_bits {
5550 u8 status[0x8];
5551 u8 reserved_0[0x18];
5552
5553 u8 syndrome[0x20];
5554
5555 u8 reserved_1[0x18];
5556 u8 eq_number[0x8];
5557
5558 u8 reserved_2[0x20];
5559};
5560
5561struct mlx5_ifc_create_eq_in_bits {
5562 u8 opcode[0x10];
5563 u8 reserved_0[0x10];
5564
5565 u8 reserved_1[0x10];
5566 u8 op_mod[0x10];
5567
5568 u8 reserved_2[0x40];
5569
5570 struct mlx5_ifc_eqc_bits eq_context_entry;
5571
5572 u8 reserved_3[0x40];
5573
5574 u8 event_bitmask[0x40];
5575
5576 u8 reserved_4[0x580];
5577
5578 u8 pas[0][0x40];
5579};
5580
5581struct mlx5_ifc_create_dct_out_bits {
5582 u8 status[0x8];
5583 u8 reserved_0[0x18];
5584
5585 u8 syndrome[0x20];
5586
5587 u8 reserved_1[0x8];
5588 u8 dctn[0x18];
5589
5590 u8 reserved_2[0x20];
5591};
5592
5593struct mlx5_ifc_create_dct_in_bits {
5594 u8 opcode[0x10];
5595 u8 reserved_0[0x10];
5596
5597 u8 reserved_1[0x10];
5598 u8 op_mod[0x10];
5599
5600 u8 reserved_2[0x40];
5601
5602 struct mlx5_ifc_dctc_bits dct_context_entry;
5603
5604 u8 reserved_3[0x180];
5605};
5606
5607struct mlx5_ifc_create_cq_out_bits {
5608 u8 status[0x8];
5609 u8 reserved_0[0x18];
5610
5611 u8 syndrome[0x20];
5612
5613 u8 reserved_1[0x8];
5614 u8 cqn[0x18];
5615
5616 u8 reserved_2[0x20];
5617};
5618
5619struct mlx5_ifc_create_cq_in_bits {
5620 u8 opcode[0x10];
5621 u8 reserved_0[0x10];
5622
5623 u8 reserved_1[0x10];
5624 u8 op_mod[0x10];
5625
5626 u8 reserved_2[0x40];
5627
5628 struct mlx5_ifc_cqc_bits cq_context;
5629
5630 u8 reserved_3[0x600];
5631
5632 u8 pas[0][0x40];
5633};
5634
5635struct mlx5_ifc_config_int_moderation_out_bits {
5636 u8 status[0x8];
5637 u8 reserved_0[0x18];
5638
5639 u8 syndrome[0x20];
5640
5641 u8 reserved_1[0x4];
5642 u8 min_delay[0xc];
5643 u8 int_vector[0x10];
5644
5645 u8 reserved_2[0x20];
5646};
5647
5648enum {
5649 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
5650 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
5651};
5652
5653struct mlx5_ifc_config_int_moderation_in_bits {
5654 u8 opcode[0x10];
5655 u8 reserved_0[0x10];
5656
5657 u8 reserved_1[0x10];
5658 u8 op_mod[0x10];
5659
5660 u8 reserved_2[0x4];
5661 u8 min_delay[0xc];
5662 u8 int_vector[0x10];
5663
5664 u8 reserved_3[0x20];
5665};
5666
5667struct mlx5_ifc_attach_to_mcg_out_bits {
5668 u8 status[0x8];
5669 u8 reserved_0[0x18];
5670
5671 u8 syndrome[0x20];
5672
5673 u8 reserved_1[0x40];
5674};
5675
5676struct mlx5_ifc_attach_to_mcg_in_bits {
5677 u8 opcode[0x10];
5678 u8 reserved_0[0x10];
5679
5680 u8 reserved_1[0x10];
5681 u8 op_mod[0x10];
5682
5683 u8 reserved_2[0x8];
5684 u8 qpn[0x18];
5685
5686 u8 reserved_3[0x20];
5687
5688 u8 multicast_gid[16][0x8];
5689};
5690
5691struct mlx5_ifc_arm_xrc_srq_out_bits {
5692 u8 status[0x8];
5693 u8 reserved_0[0x18];
5694
5695 u8 syndrome[0x20];
5696
5697 u8 reserved_1[0x40];
5698};
5699
5700enum {
5701 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
5702};
5703
5704struct mlx5_ifc_arm_xrc_srq_in_bits {
5705 u8 opcode[0x10];
5706 u8 reserved_0[0x10];
5707
5708 u8 reserved_1[0x10];
5709 u8 op_mod[0x10];
5710
5711 u8 reserved_2[0x8];
5712 u8 xrc_srqn[0x18];
5713
5714 u8 reserved_3[0x10];
5715 u8 lwm[0x10];
5716};
5717
5718struct mlx5_ifc_arm_rq_out_bits {
5719 u8 status[0x8];
5720 u8 reserved_0[0x18];
5721
5722 u8 syndrome[0x20];
5723
5724 u8 reserved_1[0x40];
5725};
5726
5727enum {
5728 MLX5_ARM_RQ_IN_OP_MOD_SRQ_ = 0x1,
5729};
5730
5731struct mlx5_ifc_arm_rq_in_bits {
5732 u8 opcode[0x10];
5733 u8 reserved_0[0x10];
5734
5735 u8 reserved_1[0x10];
5736 u8 op_mod[0x10];
5737
5738 u8 reserved_2[0x8];
5739 u8 srq_number[0x18];
5740
5741 u8 reserved_3[0x10];
5742 u8 lwm[0x10];
5743};
5744
5745struct mlx5_ifc_arm_dct_out_bits {
5746 u8 status[0x8];
5747 u8 reserved_0[0x18];
5748
5749 u8 syndrome[0x20];
5750
5751 u8 reserved_1[0x40];
5752};
5753
5754struct mlx5_ifc_arm_dct_in_bits {
5755 u8 opcode[0x10];
5756 u8 reserved_0[0x10];
5757
5758 u8 reserved_1[0x10];
5759 u8 op_mod[0x10];
5760
5761 u8 reserved_2[0x8];
5762 u8 dct_number[0x18];
5763
5764 u8 reserved_3[0x20];
5765};
5766
5767struct mlx5_ifc_alloc_xrcd_out_bits {
5768 u8 status[0x8];
5769 u8 reserved_0[0x18];
5770
5771 u8 syndrome[0x20];
5772
5773 u8 reserved_1[0x8];
5774 u8 xrcd[0x18];
5775
5776 u8 reserved_2[0x20];
5777};
5778
5779struct mlx5_ifc_alloc_xrcd_in_bits {
5780 u8 opcode[0x10];
5781 u8 reserved_0[0x10];
5782
5783 u8 reserved_1[0x10];
5784 u8 op_mod[0x10];
5785
5786 u8 reserved_2[0x40];
5787};
5788
5789struct mlx5_ifc_alloc_uar_out_bits {
5790 u8 status[0x8];
5791 u8 reserved_0[0x18];
5792
5793 u8 syndrome[0x20];
5794
5795 u8 reserved_1[0x8];
5796 u8 uar[0x18];
5797
5798 u8 reserved_2[0x20];
5799};
5800
5801struct mlx5_ifc_alloc_uar_in_bits {
5802 u8 opcode[0x10];
5803 u8 reserved_0[0x10];
5804
5805 u8 reserved_1[0x10];
5806 u8 op_mod[0x10];
5807
5808 u8 reserved_2[0x40];
5809};
5810
5811struct mlx5_ifc_alloc_transport_domain_out_bits {
5812 u8 status[0x8];
5813 u8 reserved_0[0x18];
5814
5815 u8 syndrome[0x20];
5816
5817 u8 reserved_1[0x8];
5818 u8 transport_domain[0x18];
5819
5820 u8 reserved_2[0x20];
5821};
5822
5823struct mlx5_ifc_alloc_transport_domain_in_bits {
5824 u8 opcode[0x10];
5825 u8 reserved_0[0x10];
5826
5827 u8 reserved_1[0x10];
5828 u8 op_mod[0x10];
5829
5830 u8 reserved_2[0x40];
5831};
5832
5833struct mlx5_ifc_alloc_q_counter_out_bits {
5834 u8 status[0x8];
5835 u8 reserved_0[0x18];
5836
5837 u8 syndrome[0x20];
5838
5839 u8 reserved_1[0x18];
5840 u8 counter_set_id[0x8];
5841
5842 u8 reserved_2[0x20];
5843};
5844
5845struct mlx5_ifc_alloc_q_counter_in_bits {
5846 u8 opcode[0x10];
5847 u8 reserved_0[0x10];
5848
5849 u8 reserved_1[0x10];
5850 u8 op_mod[0x10];
5851
5852 u8 reserved_2[0x40];
5853};
5854
5855struct mlx5_ifc_alloc_pd_out_bits {
5856 u8 status[0x8];
5857 u8 reserved_0[0x18];
5858
5859 u8 syndrome[0x20];
5860
5861 u8 reserved_1[0x8];
5862 u8 pd[0x18];
5863
5864 u8 reserved_2[0x20];
5865};
5866
5867struct mlx5_ifc_alloc_pd_in_bits {
5868 u8 opcode[0x10];
5869 u8 reserved_0[0x10];
5870
5871 u8 reserved_1[0x10];
5872 u8 op_mod[0x10];
5873
5874 u8 reserved_2[0x40];
5875};
5876
5877struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
5878 u8 status[0x8];
5879 u8 reserved_0[0x18];
5880
5881 u8 syndrome[0x20];
5882
5883 u8 reserved_1[0x40];
5884};
5885
5886struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
5887 u8 opcode[0x10];
5888 u8 reserved_0[0x10];
5889
5890 u8 reserved_1[0x10];
5891 u8 op_mod[0x10];
5892
5893 u8 reserved_2[0x20];
5894
5895 u8 reserved_3[0x10];
5896 u8 vxlan_udp_port[0x10];
5897};
5898
5899struct mlx5_ifc_access_register_out_bits {
5900 u8 status[0x8];
5901 u8 reserved_0[0x18];
5902
5903 u8 syndrome[0x20];
5904
5905 u8 reserved_1[0x40];
5906
5907 u8 register_data[0][0x20];
5908};
5909
5910enum {
5911 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
5912 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
5913};
5914
5915struct mlx5_ifc_access_register_in_bits {
5916 u8 opcode[0x10];
5917 u8 reserved_0[0x10];
5918
5919 u8 reserved_1[0x10];
5920 u8 op_mod[0x10];
5921
5922 u8 reserved_2[0x10];
5923 u8 register_id[0x10];
5924
5925 u8 argument[0x20];
5926
5927 u8 register_data[0][0x20];
5928};
5929
5930struct mlx5_ifc_sltp_reg_bits {
5931 u8 status[0x4];
5932 u8 version[0x4];
5933 u8 local_port[0x8];
5934 u8 pnat[0x2];
5935 u8 reserved_0[0x2];
5936 u8 lane[0x4];
5937 u8 reserved_1[0x8];
5938
5939 u8 reserved_2[0x20];
5940
5941 u8 reserved_3[0x7];
5942 u8 polarity[0x1];
5943 u8 ob_tap0[0x8];
5944 u8 ob_tap1[0x8];
5945 u8 ob_tap2[0x8];
5946
5947 u8 reserved_4[0xc];
5948 u8 ob_preemp_mode[0x4];
5949 u8 ob_reg[0x8];
5950 u8 ob_bias[0x8];
5951
5952 u8 reserved_5[0x20];
5953};
5954
5955struct mlx5_ifc_slrg_reg_bits {
5956 u8 status[0x4];
5957 u8 version[0x4];
5958 u8 local_port[0x8];
5959 u8 pnat[0x2];
5960 u8 reserved_0[0x2];
5961 u8 lane[0x4];
5962 u8 reserved_1[0x8];
5963
5964 u8 time_to_link_up[0x10];
5965 u8 reserved_2[0xc];
5966 u8 grade_lane_speed[0x4];
5967
5968 u8 grade_version[0x8];
5969 u8 grade[0x18];
5970
5971 u8 reserved_3[0x4];
5972 u8 height_grade_type[0x4];
5973 u8 height_grade[0x18];
5974
5975 u8 height_dz[0x10];
5976 u8 height_dv[0x10];
5977
5978 u8 reserved_4[0x10];
5979 u8 height_sigma[0x10];
5980
5981 u8 reserved_5[0x20];
5982
5983 u8 reserved_6[0x4];
5984 u8 phase_grade_type[0x4];
5985 u8 phase_grade[0x18];
5986
5987 u8 reserved_7[0x8];
5988 u8 phase_eo_pos[0x8];
5989 u8 reserved_8[0x8];
5990 u8 phase_eo_neg[0x8];
5991
5992 u8 ffe_set_tested[0x10];
5993 u8 test_errors_per_lane[0x10];
5994};
5995
5996struct mlx5_ifc_pvlc_reg_bits {
5997 u8 reserved_0[0x8];
5998 u8 local_port[0x8];
5999 u8 reserved_1[0x10];
6000
6001 u8 reserved_2[0x1c];
6002 u8 vl_hw_cap[0x4];
6003
6004 u8 reserved_3[0x1c];
6005 u8 vl_admin[0x4];
6006
6007 u8 reserved_4[0x1c];
6008 u8 vl_operational[0x4];
6009};
6010
6011struct mlx5_ifc_pude_reg_bits {
6012 u8 swid[0x8];
6013 u8 local_port[0x8];
6014 u8 reserved_0[0x4];
6015 u8 admin_status[0x4];
6016 u8 reserved_1[0x4];
6017 u8 oper_status[0x4];
6018
6019 u8 reserved_2[0x60];
6020};
6021
6022struct mlx5_ifc_ptys_reg_bits {
6023 u8 reserved_0[0x8];
6024 u8 local_port[0x8];
6025 u8 reserved_1[0xd];
6026 u8 proto_mask[0x3];
6027
6028 u8 reserved_2[0x40];
6029
6030 u8 eth_proto_capability[0x20];
6031
6032 u8 ib_link_width_capability[0x10];
6033 u8 ib_proto_capability[0x10];
6034
6035 u8 reserved_3[0x20];
6036
6037 u8 eth_proto_admin[0x20];
6038
6039 u8 ib_link_width_admin[0x10];
6040 u8 ib_proto_admin[0x10];
6041
6042 u8 reserved_4[0x20];
6043
6044 u8 eth_proto_oper[0x20];
6045
6046 u8 ib_link_width_oper[0x10];
6047 u8 ib_proto_oper[0x10];
6048
6049 u8 reserved_5[0x20];
6050
6051 u8 eth_proto_lp_advertise[0x20];
6052
6053 u8 reserved_6[0x60];
6054};
6055
6056struct mlx5_ifc_ptas_reg_bits {
6057 u8 reserved_0[0x20];
6058
6059 u8 algorithm_options[0x10];
6060 u8 reserved_1[0x4];
6061 u8 repetitions_mode[0x4];
6062 u8 num_of_repetitions[0x8];
6063
6064 u8 grade_version[0x8];
6065 u8 height_grade_type[0x4];
6066 u8 phase_grade_type[0x4];
6067 u8 height_grade_weight[0x8];
6068 u8 phase_grade_weight[0x8];
6069
6070 u8 gisim_measure_bits[0x10];
6071 u8 adaptive_tap_measure_bits[0x10];
6072
6073 u8 ber_bath_high_error_threshold[0x10];
6074 u8 ber_bath_mid_error_threshold[0x10];
6075
6076 u8 ber_bath_low_error_threshold[0x10];
6077 u8 one_ratio_high_threshold[0x10];
6078
6079 u8 one_ratio_high_mid_threshold[0x10];
6080 u8 one_ratio_low_mid_threshold[0x10];
6081
6082 u8 one_ratio_low_threshold[0x10];
6083 u8 ndeo_error_threshold[0x10];
6084
6085 u8 mixer_offset_step_size[0x10];
6086 u8 reserved_2[0x8];
6087 u8 mix90_phase_for_voltage_bath[0x8];
6088
6089 u8 mixer_offset_start[0x10];
6090 u8 mixer_offset_end[0x10];
6091
6092 u8 reserved_3[0x15];
6093 u8 ber_test_time[0xb];
6094};
6095
6096struct mlx5_ifc_pspa_reg_bits {
6097 u8 swid[0x8];
6098 u8 local_port[0x8];
6099 u8 sub_port[0x8];
6100 u8 reserved_0[0x8];
6101
6102 u8 reserved_1[0x20];
6103};
6104
6105struct mlx5_ifc_pqdr_reg_bits {
6106 u8 reserved_0[0x8];
6107 u8 local_port[0x8];
6108 u8 reserved_1[0x5];
6109 u8 prio[0x3];
6110 u8 reserved_2[0x6];
6111 u8 mode[0x2];
6112
6113 u8 reserved_3[0x20];
6114
6115 u8 reserved_4[0x10];
6116 u8 min_threshold[0x10];
6117
6118 u8 reserved_5[0x10];
6119 u8 max_threshold[0x10];
6120
6121 u8 reserved_6[0x10];
6122 u8 mark_probability_denominator[0x10];
6123
6124 u8 reserved_7[0x60];
6125};
6126
6127struct mlx5_ifc_ppsc_reg_bits {
6128 u8 reserved_0[0x8];
6129 u8 local_port[0x8];
6130 u8 reserved_1[0x10];
6131
6132 u8 reserved_2[0x60];
6133
6134 u8 reserved_3[0x1c];
6135 u8 wrps_admin[0x4];
6136
6137 u8 reserved_4[0x1c];
6138 u8 wrps_status[0x4];
6139
6140 u8 reserved_5[0x8];
6141 u8 up_threshold[0x8];
6142 u8 reserved_6[0x8];
6143 u8 down_threshold[0x8];
6144
6145 u8 reserved_7[0x20];
6146
6147 u8 reserved_8[0x1c];
6148 u8 srps_admin[0x4];
6149
6150 u8 reserved_9[0x1c];
6151 u8 srps_status[0x4];
6152
6153 u8 reserved_10[0x40];
6154};
6155
6156struct mlx5_ifc_pplr_reg_bits {
6157 u8 reserved_0[0x8];
6158 u8 local_port[0x8];
6159 u8 reserved_1[0x10];
6160
6161 u8 reserved_2[0x8];
6162 u8 lb_cap[0x8];
6163 u8 reserved_3[0x8];
6164 u8 lb_en[0x8];
6165};
6166
6167struct mlx5_ifc_pplm_reg_bits {
6168 u8 reserved_0[0x8];
6169 u8 local_port[0x8];
6170 u8 reserved_1[0x10];
6171
6172 u8 reserved_2[0x20];
6173
6174 u8 port_profile_mode[0x8];
6175 u8 static_port_profile[0x8];
6176 u8 active_port_profile[0x8];
6177 u8 reserved_3[0x8];
6178
6179 u8 retransmission_active[0x8];
6180 u8 fec_mode_active[0x18];
6181
6182 u8 reserved_4[0x20];
6183};
6184
6185struct mlx5_ifc_ppcnt_reg_bits {
6186 u8 swid[0x8];
6187 u8 local_port[0x8];
6188 u8 pnat[0x2];
6189 u8 reserved_0[0x8];
6190 u8 grp[0x6];
6191
6192 u8 clr[0x1];
6193 u8 reserved_1[0x1c];
6194 u8 prio_tc[0x3];
6195
6196 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
6197};
6198
6199struct mlx5_ifc_ppad_reg_bits {
6200 u8 reserved_0[0x3];
6201 u8 single_mac[0x1];
6202 u8 reserved_1[0x4];
6203 u8 local_port[0x8];
6204 u8 mac_47_32[0x10];
6205
6206 u8 mac_31_0[0x20];
6207
6208 u8 reserved_2[0x40];
6209};
6210
6211struct mlx5_ifc_pmtu_reg_bits {
6212 u8 reserved_0[0x8];
6213 u8 local_port[0x8];
6214 u8 reserved_1[0x10];
6215
6216 u8 max_mtu[0x10];
6217 u8 reserved_2[0x10];
6218
6219 u8 admin_mtu[0x10];
6220 u8 reserved_3[0x10];
6221
6222 u8 oper_mtu[0x10];
6223 u8 reserved_4[0x10];
6224};
6225
6226struct mlx5_ifc_pmpr_reg_bits {
6227 u8 reserved_0[0x8];
6228 u8 module[0x8];
6229 u8 reserved_1[0x10];
6230
6231 u8 reserved_2[0x18];
6232 u8 attenuation_5g[0x8];
6233
6234 u8 reserved_3[0x18];
6235 u8 attenuation_7g[0x8];
6236
6237 u8 reserved_4[0x18];
6238 u8 attenuation_12g[0x8];
6239};
6240
6241struct mlx5_ifc_pmpe_reg_bits {
6242 u8 reserved_0[0x8];
6243 u8 module[0x8];
6244 u8 reserved_1[0xc];
6245 u8 module_status[0x4];
6246
6247 u8 reserved_2[0x60];
6248};
6249
6250struct mlx5_ifc_pmpc_reg_bits {
6251 u8 module_state_updated[32][0x8];
6252};
6253
6254struct mlx5_ifc_pmlpn_reg_bits {
6255 u8 reserved_0[0x4];
6256 u8 mlpn_status[0x4];
6257 u8 local_port[0x8];
6258 u8 reserved_1[0x10];
6259
6260 u8 e[0x1];
6261 u8 reserved_2[0x1f];
6262};
6263
6264struct mlx5_ifc_pmlp_reg_bits {
6265 u8 rxtx[0x1];
6266 u8 reserved_0[0x7];
6267 u8 local_port[0x8];
6268 u8 reserved_1[0x8];
6269 u8 width[0x8];
6270
6271 u8 lane0_module_mapping[0x20];
6272
6273 u8 lane1_module_mapping[0x20];
6274
6275 u8 lane2_module_mapping[0x20];
6276
6277 u8 lane3_module_mapping[0x20];
6278
6279 u8 reserved_2[0x160];
6280};
6281
6282struct mlx5_ifc_pmaos_reg_bits {
6283 u8 reserved_0[0x8];
6284 u8 module[0x8];
6285 u8 reserved_1[0x4];
6286 u8 admin_status[0x4];
6287 u8 reserved_2[0x4];
6288 u8 oper_status[0x4];
6289
6290 u8 ase[0x1];
6291 u8 ee[0x1];
6292 u8 reserved_3[0x1c];
6293 u8 e[0x2];
6294
6295 u8 reserved_4[0x40];
6296};
6297
6298struct mlx5_ifc_plpc_reg_bits {
6299 u8 reserved_0[0x4];
6300 u8 profile_id[0xc];
6301 u8 reserved_1[0x4];
6302 u8 proto_mask[0x4];
6303 u8 reserved_2[0x8];
6304
6305 u8 reserved_3[0x10];
6306 u8 lane_speed[0x10];
6307
6308 u8 reserved_4[0x17];
6309 u8 lpbf[0x1];
6310 u8 fec_mode_policy[0x8];
6311
6312 u8 retransmission_capability[0x8];
6313 u8 fec_mode_capability[0x18];
6314
6315 u8 retransmission_support_admin[0x8];
6316 u8 fec_mode_support_admin[0x18];
6317
6318 u8 retransmission_request_admin[0x8];
6319 u8 fec_mode_request_admin[0x18];
6320
6321 u8 reserved_5[0x80];
6322};
6323
6324struct mlx5_ifc_plib_reg_bits {
6325 u8 reserved_0[0x8];
6326 u8 local_port[0x8];
6327 u8 reserved_1[0x8];
6328 u8 ib_port[0x8];
6329
6330 u8 reserved_2[0x60];
6331};
6332
6333struct mlx5_ifc_plbf_reg_bits {
6334 u8 reserved_0[0x8];
6335 u8 local_port[0x8];
6336 u8 reserved_1[0xd];
6337 u8 lbf_mode[0x3];
6338
6339 u8 reserved_2[0x20];
6340};
6341
6342struct mlx5_ifc_pipg_reg_bits {
6343 u8 reserved_0[0x8];
6344 u8 local_port[0x8];
6345 u8 reserved_1[0x10];
6346
6347 u8 dic[0x1];
6348 u8 reserved_2[0x19];
6349 u8 ipg[0x4];
6350 u8 reserved_3[0x2];
6351};
6352
6353struct mlx5_ifc_pifr_reg_bits {
6354 u8 reserved_0[0x8];
6355 u8 local_port[0x8];
6356 u8 reserved_1[0x10];
6357
6358 u8 reserved_2[0xe0];
6359
6360 u8 port_filter[8][0x20];
6361
6362 u8 port_filter_update_en[8][0x20];
6363};
6364
6365struct mlx5_ifc_pfcc_reg_bits {
6366 u8 reserved_0[0x8];
6367 u8 local_port[0x8];
6368 u8 reserved_1[0x10];
6369
6370 u8 ppan[0x4];
6371 u8 reserved_2[0x4];
6372 u8 prio_mask_tx[0x8];
6373 u8 reserved_3[0x8];
6374 u8 prio_mask_rx[0x8];
6375
6376 u8 pptx[0x1];
6377 u8 aptx[0x1];
6378 u8 reserved_4[0x6];
6379 u8 pfctx[0x8];
6380 u8 reserved_5[0x10];
6381
6382 u8 pprx[0x1];
6383 u8 aprx[0x1];
6384 u8 reserved_6[0x6];
6385 u8 pfcrx[0x8];
6386 u8 reserved_7[0x10];
6387
6388 u8 reserved_8[0x80];
6389};
6390
6391struct mlx5_ifc_pelc_reg_bits {
6392 u8 op[0x4];
6393 u8 reserved_0[0x4];
6394 u8 local_port[0x8];
6395 u8 reserved_1[0x10];
6396
6397 u8 op_admin[0x8];
6398 u8 op_capability[0x8];
6399 u8 op_request[0x8];
6400 u8 op_active[0x8];
6401
6402 u8 admin[0x40];
6403
6404 u8 capability[0x40];
6405
6406 u8 request[0x40];
6407
6408 u8 active[0x40];
6409
6410 u8 reserved_2[0x80];
6411};
6412
6413struct mlx5_ifc_peir_reg_bits {
6414 u8 reserved_0[0x8];
6415 u8 local_port[0x8];
6416 u8 reserved_1[0x10];
6417
6418 u8 reserved_2[0xc];
6419 u8 error_count[0x4];
6420 u8 reserved_3[0x10];
6421
6422 u8 reserved_4[0xc];
6423 u8 lane[0x4];
6424 u8 reserved_5[0x8];
6425 u8 error_type[0x8];
6426};
6427
6428struct mlx5_ifc_pcap_reg_bits {
6429 u8 reserved_0[0x8];
6430 u8 local_port[0x8];
6431 u8 reserved_1[0x10];
6432
6433 u8 port_capability_mask[4][0x20];
6434};
6435
6436struct mlx5_ifc_paos_reg_bits {
6437 u8 swid[0x8];
6438 u8 local_port[0x8];
6439 u8 reserved_0[0x4];
6440 u8 admin_status[0x4];
6441 u8 reserved_1[0x4];
6442 u8 oper_status[0x4];
6443
6444 u8 ase[0x1];
6445 u8 ee[0x1];
6446 u8 reserved_2[0x1c];
6447 u8 e[0x2];
6448
6449 u8 reserved_3[0x40];
6450};
6451
6452struct mlx5_ifc_pamp_reg_bits {
6453 u8 reserved_0[0x8];
6454 u8 opamp_group[0x8];
6455 u8 reserved_1[0xc];
6456 u8 opamp_group_type[0x4];
6457
6458 u8 start_index[0x10];
6459 u8 reserved_2[0x4];
6460 u8 num_of_indices[0xc];
6461
6462 u8 index_data[18][0x10];
6463};
6464
6465struct mlx5_ifc_lane_2_module_mapping_bits {
6466 u8 reserved_0[0x6];
6467 u8 rx_lane[0x2];
6468 u8 reserved_1[0x6];
6469 u8 tx_lane[0x2];
6470 u8 reserved_2[0x8];
6471 u8 module[0x8];
6472};
6473
6474struct mlx5_ifc_bufferx_reg_bits {
6475 u8 reserved_0[0x6];
6476 u8 lossy[0x1];
6477 u8 epsb[0x1];
6478 u8 reserved_1[0xc];
6479 u8 size[0xc];
6480
6481 u8 xoff_threshold[0x10];
6482 u8 xon_threshold[0x10];
6483};
6484
6485struct mlx5_ifc_set_node_in_bits {
6486 u8 node_description[64][0x8];
6487};
6488
6489struct mlx5_ifc_register_power_settings_bits {
6490 u8 reserved_0[0x18];
6491 u8 power_settings_level[0x8];
6492
6493 u8 reserved_1[0x60];
6494};
6495
6496struct mlx5_ifc_register_host_endianness_bits {
6497 u8 he[0x1];
6498 u8 reserved_0[0x1f];
6499
6500 u8 reserved_1[0x60];
6501};
6502
6503struct mlx5_ifc_umr_pointer_desc_argument_bits {
6504 u8 reserved_0[0x20];
6505
6506 u8 mkey[0x20];
6507
6508 u8 addressh_63_32[0x20];
6509
6510 u8 addressl_31_0[0x20];
6511};
6512
6513struct mlx5_ifc_ud_adrs_vector_bits {
6514 u8 dc_key[0x40];
6515
6516 u8 ext[0x1];
6517 u8 reserved_0[0x7];
6518 u8 destination_qp_dct[0x18];
6519
6520 u8 static_rate[0x4];
6521 u8 sl_eth_prio[0x4];
6522 u8 fl[0x1];
6523 u8 mlid[0x7];
6524 u8 rlid_udp_sport[0x10];
6525
6526 u8 reserved_1[0x20];
6527
6528 u8 rmac_47_16[0x20];
6529
6530 u8 rmac_15_0[0x10];
6531 u8 tclass[0x8];
6532 u8 hop_limit[0x8];
6533
6534 u8 reserved_2[0x1];
6535 u8 grh[0x1];
6536 u8 reserved_3[0x2];
6537 u8 src_addr_index[0x8];
6538 u8 flow_label[0x14];
6539
6540 u8 rgid_rip[16][0x8];
6541};
6542
6543struct mlx5_ifc_pages_req_event_bits {
6544 u8 reserved_0[0x10];
6545 u8 function_id[0x10];
6546
6547 u8 num_pages[0x20];
6548
6549 u8 reserved_1[0xa0];
6550};
6551
6552struct mlx5_ifc_eqe_bits {
6553 u8 reserved_0[0x8];
6554 u8 event_type[0x8];
6555 u8 reserved_1[0x8];
6556 u8 event_sub_type[0x8];
6557
6558 u8 reserved_2[0xe0];
6559
6560 union mlx5_ifc_event_auto_bits event_data;
6561
6562 u8 reserved_3[0x10];
6563 u8 signature[0x8];
6564 u8 reserved_4[0x7];
6565 u8 owner[0x1];
6566};
6567
6568enum {
6569 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
6570};
6571
6572struct mlx5_ifc_cmd_queue_entry_bits {
6573 u8 type[0x8];
6574 u8 reserved_0[0x18];
6575
6576 u8 input_length[0x20];
6577
6578 u8 input_mailbox_pointer_63_32[0x20];
6579
6580 u8 input_mailbox_pointer_31_9[0x17];
6581 u8 reserved_1[0x9];
6582
6583 u8 command_input_inline_data[16][0x8];
6584
6585 u8 command_output_inline_data[16][0x8];
6586
6587 u8 output_mailbox_pointer_63_32[0x20];
6588
6589 u8 output_mailbox_pointer_31_9[0x17];
6590 u8 reserved_2[0x9];
6591
6592 u8 output_length[0x20];
6593
6594 u8 token[0x8];
6595 u8 signature[0x8];
6596 u8 reserved_3[0x8];
6597 u8 status[0x7];
6598 u8 ownership[0x1];
6599};
6600
6601struct mlx5_ifc_cmd_out_bits {
6602 u8 status[0x8];
6603 u8 reserved_0[0x18];
6604
6605 u8 syndrome[0x20];
6606
6607 u8 command_output[0x20];
6608};
6609
6610struct mlx5_ifc_cmd_in_bits {
6611 u8 opcode[0x10];
6612 u8 reserved_0[0x10];
6613
6614 u8 reserved_1[0x10];
6615 u8 op_mod[0x10];
6616
6617 u8 command[0][0x20];
6618};
6619
6620struct mlx5_ifc_cmd_if_box_bits {
6621 u8 mailbox_data[512][0x8];
6622
6623 u8 reserved_0[0x180];
6624
6625 u8 next_pointer_63_32[0x20];
6626
6627 u8 next_pointer_31_10[0x16];
6628 u8 reserved_1[0xa];
6629
6630 u8 block_number[0x20];
6631
6632 u8 reserved_2[0x8];
6633 u8 token[0x8];
6634 u8 ctrl_signature[0x8];
6635 u8 signature[0x8];
6636};
6637
6638struct mlx5_ifc_mtt_bits {
6639 u8 ptag_63_32[0x20];
6640
6641 u8 ptag_31_8[0x18];
6642 u8 reserved_0[0x6];
6643 u8 wr_en[0x1];
6644 u8 rd_en[0x1];
6645};
6646
6647enum {
6648 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
6649 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
6650 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
6651};
6652
6653enum {
6654 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
6655 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
6656 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
6657};
6658
6659enum {
6660 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
6661 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
6662 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
6663 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
6664 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
6665 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
6666 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
6667 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
6668 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
6669 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
6670 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
6671};
6672
6673struct mlx5_ifc_initial_seg_bits {
6674 u8 fw_rev_minor[0x10];
6675 u8 fw_rev_major[0x10];
6676
6677 u8 cmd_interface_rev[0x10];
6678 u8 fw_rev_subminor[0x10];
6679
6680 u8 reserved_0[0x40];
6681
6682 u8 cmdq_phy_addr_63_32[0x20];
6683
6684 u8 cmdq_phy_addr_31_12[0x14];
6685 u8 reserved_1[0x2];
6686 u8 nic_interface[0x2];
6687 u8 log_cmdq_size[0x4];
6688 u8 log_cmdq_stride[0x4];
6689
6690 u8 command_doorbell_vector[0x20];
6691
6692 u8 reserved_2[0xf00];
6693
6694 u8 initializing[0x1];
6695 u8 reserved_3[0x4];
6696 u8 nic_interface_supported[0x3];
6697 u8 reserved_4[0x18];
6698
6699 struct mlx5_ifc_health_buffer_bits health_buffer;
6700
6701 u8 no_dram_nic_offset[0x20];
6702
6703 u8 reserved_5[0x6e40];
6704
6705 u8 reserved_6[0x1f];
6706 u8 clear_int[0x1];
6707
6708 u8 health_syndrome[0x8];
6709 u8 health_counter[0x18];
6710
6711 u8 reserved_7[0x17fc0];
6712};
6713
6714union mlx5_ifc_ports_control_registers_document_bits {
6715 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
6716 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
6717 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
6718 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
6719 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
6720 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
6721 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
6722 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
6723 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
6724 struct mlx5_ifc_pamp_reg_bits pamp_reg;
6725 struct mlx5_ifc_paos_reg_bits paos_reg;
6726 struct mlx5_ifc_pcap_reg_bits pcap_reg;
6727 struct mlx5_ifc_peir_reg_bits peir_reg;
6728 struct mlx5_ifc_pelc_reg_bits pelc_reg;
6729 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
6730 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
6731 struct mlx5_ifc_pifr_reg_bits pifr_reg;
6732 struct mlx5_ifc_pipg_reg_bits pipg_reg;
6733 struct mlx5_ifc_plbf_reg_bits plbf_reg;
6734 struct mlx5_ifc_plib_reg_bits plib_reg;
6735 struct mlx5_ifc_plpc_reg_bits plpc_reg;
6736 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
6737 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
6738 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
6739 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
6740 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
6741 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
6742 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
6743 struct mlx5_ifc_ppad_reg_bits ppad_reg;
6744 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
6745 struct mlx5_ifc_pplm_reg_bits pplm_reg;
6746 struct mlx5_ifc_pplr_reg_bits pplr_reg;
6747 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
6748 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
6749 struct mlx5_ifc_pspa_reg_bits pspa_reg;
6750 struct mlx5_ifc_ptas_reg_bits ptas_reg;
6751 struct mlx5_ifc_ptys_reg_bits ptys_reg;
6752 struct mlx5_ifc_pude_reg_bits pude_reg;
6753 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
6754 struct mlx5_ifc_slrg_reg_bits slrg_reg;
6755 struct mlx5_ifc_sltp_reg_bits sltp_reg;
6756 u8 reserved_0[0x60e0];
6757};
6758
6759union mlx5_ifc_debug_enhancements_document_bits {
6760 struct mlx5_ifc_health_buffer_bits health_buffer;
6761 u8 reserved_0[0x200];
6762};
6763
6764union mlx5_ifc_uplink_pci_interface_document_bits {
6765 struct mlx5_ifc_initial_seg_bits initial_seg;
6766 u8 reserved_0[0x20060];
347}; 6767};
348 6768
349#endif /* MLX5_IFC_H */ 6769#endif /* MLX5_IFC_H */
diff --git a/include/linux/mlx5/qp.h b/include/linux/mlx5/qp.h
index 310b5f7fd6ae..f079fb1a31f7 100644
--- a/include/linux/mlx5/qp.h
+++ b/include/linux/mlx5/qp.h
@@ -134,13 +134,21 @@ enum {
134 134
135enum { 135enum {
136 MLX5_WQE_CTRL_CQ_UPDATE = 2 << 2, 136 MLX5_WQE_CTRL_CQ_UPDATE = 2 << 2,
137 MLX5_WQE_CTRL_CQ_UPDATE_AND_EQE = 3 << 2,
137 MLX5_WQE_CTRL_SOLICITED = 1 << 1, 138 MLX5_WQE_CTRL_SOLICITED = 1 << 1,
138}; 139};
139 140
140enum { 141enum {
142 MLX5_SEND_WQE_DS = 16,
141 MLX5_SEND_WQE_BB = 64, 143 MLX5_SEND_WQE_BB = 64,
142}; 144};
143 145
146#define MLX5_SEND_WQEBB_NUM_DS (MLX5_SEND_WQE_BB / MLX5_SEND_WQE_DS)
147
148enum {
149 MLX5_SEND_WQE_MAX_WQEBBS = 16,
150};
151
144enum { 152enum {
145 MLX5_WQE_FMR_PERM_LOCAL_READ = 1 << 27, 153 MLX5_WQE_FMR_PERM_LOCAL_READ = 1 << 27,
146 MLX5_WQE_FMR_PERM_LOCAL_WRITE = 1 << 28, 154 MLX5_WQE_FMR_PERM_LOCAL_WRITE = 1 << 28,
@@ -200,6 +208,23 @@ struct mlx5_wqe_ctrl_seg {
200#define MLX5_WQE_CTRL_WQE_INDEX_MASK 0x00ffff00 208#define MLX5_WQE_CTRL_WQE_INDEX_MASK 0x00ffff00
201#define MLX5_WQE_CTRL_WQE_INDEX_SHIFT 8 209#define MLX5_WQE_CTRL_WQE_INDEX_SHIFT 8
202 210
211enum {
212 MLX5_ETH_WQE_L3_INNER_CSUM = 1 << 4,
213 MLX5_ETH_WQE_L4_INNER_CSUM = 1 << 5,
214 MLX5_ETH_WQE_L3_CSUM = 1 << 6,
215 MLX5_ETH_WQE_L4_CSUM = 1 << 7,
216};
217
218struct mlx5_wqe_eth_seg {
219 u8 rsvd0[4];
220 u8 cs_flags;
221 u8 rsvd1;
222 __be16 mss;
223 __be32 rsvd2;
224 __be16 inline_hdr_sz;
225 u8 inline_hdr_start[2];
226};
227
203struct mlx5_wqe_xrc_seg { 228struct mlx5_wqe_xrc_seg {
204 __be32 xrc_srqn; 229 __be32 xrc_srqn;
205 u8 rsvd[12]; 230 u8 rsvd[12];
generated by cgit v1.2.2 (git 2.25.0) at 2026-04-18 22:15:07 -0400