mfd: stmpe: Rework registers access

this update allows to use registers map as following :
regs[reg_index + offset] instead of
regs[reg_index] + offset

This makes code clearer and will facilitate the addition of STMPE1600
on which LSB and MSB registers are respectively located at addr and addr + 1.
Despite for all others STMPE variant, LSB and MSB registers are respectively
located in reverse order at addr + 1 and addr.

For variant which have 3 registers's bank, we use LSB,CSB and MSB indexes
which contains respectively LSB (or LOW), CSB (or MID) and MSB (or HIGH)
register addresses (STMPE1801/STMPE24xx).
For variant which have 2 registers's bank, we use LSB and CSB indexes only.
In this case the CSB index contains the MSB regs address (STMPE 1601).

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>

1 files changed, 18 insertions, 0 deletions

diff --git a/include/linux/mfd/stmpe.h b/include/linux/mfd/stmpe.h
index eb8b73bd139f..6b26661a640e 100644
--- a/include/linux/mfd/stmpe.h
+++ b/include/linux/mfd/stmpe.h
@@ -43,20 +43,38 @@ enum {
         STMPE_IDX_SYS_CTRL2,
         STMPE_IDX_ICR_LSB,
         STMPE_IDX_IER_LSB,
+        STMPE_IDX_IER_MSB,
         STMPE_IDX_ISR_LSB,
         STMPE_IDX_ISR_MSB,
         STMPE_IDX_GPMR_LSB,
+        STMPE_IDX_GPMR_CSB,
+        STMPE_IDX_GPMR_MSB,
         STMPE_IDX_GPSR_LSB,
+        STMPE_IDX_GPSR_CSB,
+        STMPE_IDX_GPSR_MSB,
         STMPE_IDX_GPCR_LSB,
+        STMPE_IDX_GPCR_CSB,
+        STMPE_IDX_GPCR_MSB,
         STMPE_IDX_GPDR_LSB,
+        STMPE_IDX_GPDR_CSB,
+        STMPE_IDX_GPDR_MSB,
+        STMPE_IDX_GPEDR_LSB,
+        STMPE_IDX_GPEDR_CSB,
         STMPE_IDX_GPEDR_MSB,
         STMPE_IDX_GPRER_LSB,
+        STMPE_IDX_GPRER_CSB,
+        STMPE_IDX_GPRER_MSB,
         STMPE_IDX_GPFER_LSB,
+        STMPE_IDX_GPFER_CSB,
+        STMPE_IDX_GPFER_MSB,
         STMPE_IDX_GPPUR_LSB,
         STMPE_IDX_GPPDR_LSB,
         STMPE_IDX_GPAFR_U_MSB,
         STMPE_IDX_IEGPIOR_LSB,
+        STMPE_IDX_IEGPIOR_CSB,
+        STMPE_IDX_IEGPIOR_MSB,
         STMPE_IDX_ISGPIOR_LSB,
+        STMPE_IDX_ISGPIOR_CSB,
         STMPE_IDX_ISGPIOR_MSB,
         STMPE_IDX_MAX,
 };