diff options
| author | Hauke Mehrtens <hauke@hauke-m.de> | 2013-08-23 18:32:33 -0400 |
|---|---|---|
| committer | John W. Linville <linville@tuxdriver.com> | 2013-08-26 14:09:03 -0400 |
| commit | 521deea64088bc885a76bd174241eaa3d3a6876f (patch) | |
| tree | a86d49829ec72acb03a15355f3b90420d06db336 /include/linux/bcma | |
| parent | 780335acc815802dcee63d75f5589d43c3ccb402 (diff) | |
bcma: add bcma_core_pci_power_save()
This enables or disables power saving on the PCIe bus when the wifi is
in operation or not.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'include/linux/bcma')
| -rw-r--r-- | include/linux/bcma/bcma_driver_pci.h | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/include/linux/bcma/bcma_driver_pci.h b/include/linux/bcma/bcma_driver_pci.h index 0234955aa9c7..d66033f418c9 100644 --- a/include/linux/bcma/bcma_driver_pci.h +++ b/include/linux/bcma/bcma_driver_pci.h | |||
| @@ -181,6 +181,26 @@ struct pci_dev; | |||
| 181 | 181 | ||
| 182 | #define BCMA_CORE_PCI_CFG_DEVCTRL 0xd8 | 182 | #define BCMA_CORE_PCI_CFG_DEVCTRL 0xd8 |
| 183 | 183 | ||
| 184 | #define BCMA_CORE_PCI_ | ||
| 185 | |||
| 186 | /* MDIO devices (SERDES modules) */ | ||
| 187 | #define BCMA_CORE_PCI_MDIO_IEEE0 0x000 | ||
| 188 | #define BCMA_CORE_PCI_MDIO_IEEE1 0x001 | ||
| 189 | #define BCMA_CORE_PCI_MDIO_BLK0 0x800 | ||
| 190 | #define BCMA_CORE_PCI_MDIO_BLK1 0x801 | ||
| 191 | #define BCMA_CORE_PCI_MDIO_BLK1_MGMT0 0x16 | ||
| 192 | #define BCMA_CORE_PCI_MDIO_BLK1_MGMT1 0x17 | ||
| 193 | #define BCMA_CORE_PCI_MDIO_BLK1_MGMT2 0x18 | ||
| 194 | #define BCMA_CORE_PCI_MDIO_BLK1_MGMT3 0x19 | ||
| 195 | #define BCMA_CORE_PCI_MDIO_BLK1_MGMT4 0x1A | ||
| 196 | #define BCMA_CORE_PCI_MDIO_BLK2 0x802 | ||
| 197 | #define BCMA_CORE_PCI_MDIO_BLK3 0x803 | ||
| 198 | #define BCMA_CORE_PCI_MDIO_BLK4 0x804 | ||
| 199 | #define BCMA_CORE_PCI_MDIO_TXPLL 0x808 /* TXPLL register block idx */ | ||
| 200 | #define BCMA_CORE_PCI_MDIO_TXCTRL0 0x820 | ||
| 201 | #define BCMA_CORE_PCI_MDIO_SERDESID 0x831 | ||
| 202 | #define BCMA_CORE_PCI_MDIO_RXCTRL0 0x840 | ||
| 203 | |||
| 184 | /* PCIE Root Capability Register bits (Host mode only) */ | 204 | /* PCIE Root Capability Register bits (Host mode only) */ |
| 185 | #define BCMA_CORE_PCI_RC_CRS_VISIBILITY 0x0001 | 205 | #define BCMA_CORE_PCI_RC_CRS_VISIBILITY 0x0001 |
| 186 | 206 | ||
