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authorDave Airlie <airlied@redhat.com>2015-12-14 19:25:21 -0500
committerDave Airlie <airlied@redhat.com>2015-12-14 19:25:21 -0500
commit2344164a27f00f138f5744d1c6ff1e1a3cf8a125 (patch)
treed5bde4dddd4e65c4a1694e5c1dd1d7cf93cc3ca5 /drivers
parent8e13c10a7ce4eac9e47b999c0952c9812b32545d (diff)
parent634b3a4a476e96816d5d6cd5bb9f8900a53f56ba (diff)
Merge tag 'drm-intel-fixes-2015-12-11' of git://anongit.freedesktop.org/drm-intel into drm-fixes
Here are some i915 fixes for v4.4, sorry for being late this week. * tag 'drm-intel-fixes-2015-12-11' of git://anongit.freedesktop.org/drm-intel: drm/i915: Do a better job at disabling primary plane in the noatomic case. drm/i915/skl: Double RC6 WRL always on drm/i915/skl: Disable coarse power gating up until F0 drm/i915: Remove incorrect warning in context cleanup
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/drm/i915/i915_gem_context.c2
-rw-r--r--drivers/gpu/drm/i915/intel_display.c4
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c5
3 files changed, 5 insertions, 6 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 8c688a5f1589..02ceb7a4b481 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -141,8 +141,6 @@ static void i915_gem_context_clean(struct intel_context *ctx)
141 if (!ppgtt) 141 if (!ppgtt)
142 return; 142 return;
143 143
144 WARN_ON(!list_empty(&ppgtt->base.active_list));
145
146 list_for_each_entry_safe(vma, next, &ppgtt->base.inactive_list, 144 list_for_each_entry_safe(vma, next, &ppgtt->base.inactive_list,
147 mm_list) { 145 mm_list) {
148 if (WARN_ON(__i915_vma_unbind_no_wait(vma))) 146 if (WARN_ON(__i915_vma_unbind_no_wait(vma)))
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 22e86d2e408d..62211abe4922 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6309,9 +6309,11 @@ static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6309 if (to_intel_plane_state(crtc->primary->state)->visible) { 6309 if (to_intel_plane_state(crtc->primary->state)->visible) {
6310 intel_crtc_wait_for_pending_flips(crtc); 6310 intel_crtc_wait_for_pending_flips(crtc);
6311 intel_pre_disable_primary(crtc); 6311 intel_pre_disable_primary(crtc);
6312
6313 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6314 to_intel_plane_state(crtc->primary->state)->visible = false;
6312 } 6315 }
6313 6316
6314 intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
6315 dev_priv->display.crtc_disable(crtc); 6317 dev_priv->display.crtc_disable(crtc);
6316 intel_crtc->active = false; 6318 intel_crtc->active = false;
6317 intel_update_watermarks(crtc); 6319 intel_update_watermarks(crtc);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 071a76b9ac52..f091ad12d694 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4782,8 +4782,7 @@ static void gen9_enable_rc6(struct drm_device *dev)
4782 /* 2b: Program RC6 thresholds.*/ 4782 /* 2b: Program RC6 thresholds.*/
4783 4783
4784 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */ 4784 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
4785 if (IS_SKYLAKE(dev) && !((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && 4785 if (IS_SKYLAKE(dev))
4786 (INTEL_REVID(dev) <= SKL_REVID_E0)))
4787 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16); 4786 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
4788 else 4787 else
4789 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16); 4788 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
@@ -4825,7 +4824,7 @@ static void gen9_enable_rc6(struct drm_device *dev)
4825 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6. 4824 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
4826 */ 4825 */
4827 if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) || 4826 if ((IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) ||
4828 ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && (INTEL_REVID(dev) <= SKL_REVID_E0))) 4827 ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && (INTEL_REVID(dev) <= SKL_REVID_F0)))
4829 I915_WRITE(GEN9_PG_ENABLE, 0); 4828 I915_WRITE(GEN9_PG_ENABLE, 0);
4830 else 4829 else
4831 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? 4830 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?