diff options
author | Shawn Guo <shawn.guo@linaro.org> | 2011-06-24 14:04:33 -0400 |
---|---|---|
committer | Shawn Guo <shawn.guo@linaro.org> | 2011-07-26 21:30:38 -0400 |
commit | fe6b540ac033be6e9fa00dab1c8902dea0ad4016 (patch) | |
tree | b71e37f03ba8e35667a1128b0d0356b46c6597b3 /drivers/tty | |
parent | b0189cd087aa82bd23277cb5c8960ab030e13e5c (diff) |
serial/imx: get rid of the uses of cpu_is_mx1()
The patch removes all the uses of cpu_is_mx1(). Instead, it uses
the .id_table of platform_driver to distinguish the uart device type,
IMX1_UART and IMX21_UART. The IMX21_UART type runs on all i.mx
except i.mx1.
A couple of !cpu_is_mx1 logic gets turned into is_imx21_uart,
as the codes wrapped there are really IMX21 type uart specific.
It also removes macro MX1_UCR3_REF25 and MX1_UCR3_REF30 which are
not used anywhere.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Alan Cox <alan@linux.intel.com>
Cc: Greg Kroah-Hartman <gregkh@suse.de>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Diffstat (limited to 'drivers/tty')
-rw-r--r-- | drivers/tty/serial/imx.c | 85 |
1 files changed, 69 insertions, 16 deletions
diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c index 22fe801cce31..2d5eac20c5cd 100644 --- a/drivers/tty/serial/imx.c +++ b/drivers/tty/serial/imx.c | |||
@@ -48,7 +48,6 @@ | |||
48 | 48 | ||
49 | #include <asm/io.h> | 49 | #include <asm/io.h> |
50 | #include <asm/irq.h> | 50 | #include <asm/irq.h> |
51 | #include <mach/hardware.h> | ||
52 | #include <mach/imx-uart.h> | 51 | #include <mach/imx-uart.h> |
53 | 52 | ||
54 | /* Register definitions */ | 53 | /* Register definitions */ |
@@ -66,8 +65,9 @@ | |||
66 | #define UBIR 0xa4 /* BRM Incremental Register */ | 65 | #define UBIR 0xa4 /* BRM Incremental Register */ |
67 | #define UBMR 0xa8 /* BRM Modulator Register */ | 66 | #define UBMR 0xa8 /* BRM Modulator Register */ |
68 | #define UBRC 0xac /* Baud Rate Count Register */ | 67 | #define UBRC 0xac /* Baud Rate Count Register */ |
69 | #define MX2_ONEMS 0xb0 /* One Millisecond register */ | 68 | #define IMX21_ONEMS 0xb0 /* One Millisecond register */ |
70 | #define UTS (cpu_is_mx1() ? 0xd0 : 0xb4) /* UART Test Register */ | 69 | #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */ |
70 | #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/ | ||
71 | 71 | ||
72 | /* UART Control Register Bit Fields.*/ | 72 | /* UART Control Register Bit Fields.*/ |
73 | #define URXD_CHARRDY (1<<15) | 73 | #define URXD_CHARRDY (1<<15) |
@@ -87,7 +87,7 @@ | |||
87 | #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ | 87 | #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ |
88 | #define UCR1_SNDBRK (1<<4) /* Send break */ | 88 | #define UCR1_SNDBRK (1<<4) /* Send break */ |
89 | #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ | 89 | #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ |
90 | #define MX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, mx1 only */ | 90 | #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */ |
91 | #define UCR1_DOZE (1<<1) /* Doze */ | 91 | #define UCR1_DOZE (1<<1) /* Doze */ |
92 | #define UCR1_UARTEN (1<<0) /* UART enabled */ | 92 | #define UCR1_UARTEN (1<<0) /* UART enabled */ |
93 | #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ | 93 | #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ |
@@ -113,9 +113,7 @@ | |||
113 | #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ | 113 | #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ |
114 | #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ | 114 | #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ |
115 | #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ | 115 | #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ |
116 | #define MX1_UCR3_REF25 (1<<3) /* Ref freq 25 MHz, only on mx1 */ | 116 | #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */ |
117 | #define MX1_UCR3_REF30 (1<<2) /* Ref Freq 30 MHz, only on mx1 */ | ||
118 | #define MX2_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select, on mx2/mx3 */ | ||
119 | #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ | 117 | #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ |
120 | #define UCR3_BPEN (1<<0) /* Preset registers enable */ | 118 | #define UCR3_BPEN (1<<0) /* Preset registers enable */ |
121 | #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */ | 119 | #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */ |
@@ -181,6 +179,18 @@ | |||
181 | 179 | ||
182 | #define UART_NR 8 | 180 | #define UART_NR 8 |
183 | 181 | ||
182 | /* i.mx21 type uart runs on all i.mx except i.mx1 */ | ||
183 | enum imx_uart_type { | ||
184 | IMX1_UART, | ||
185 | IMX21_UART, | ||
186 | }; | ||
187 | |||
188 | /* device type dependent stuff */ | ||
189 | struct imx_uart_data { | ||
190 | unsigned uts_reg; | ||
191 | enum imx_uart_type devtype; | ||
192 | }; | ||
193 | |||
184 | struct imx_port { | 194 | struct imx_port { |
185 | struct uart_port port; | 195 | struct uart_port port; |
186 | struct timer_list timer; | 196 | struct timer_list timer; |
@@ -192,6 +202,7 @@ struct imx_port { | |||
192 | unsigned int irda_inv_tx:1; | 202 | unsigned int irda_inv_tx:1; |
193 | unsigned short trcv_delay; /* transceiver delay */ | 203 | unsigned short trcv_delay; /* transceiver delay */ |
194 | struct clk *clk; | 204 | struct clk *clk; |
205 | struct imx_uart_data *devdata; | ||
195 | }; | 206 | }; |
196 | 207 | ||
197 | #ifdef CONFIG_IRDA | 208 | #ifdef CONFIG_IRDA |
@@ -200,6 +211,45 @@ struct imx_port { | |||
200 | #define USE_IRDA(sport) (0) | 211 | #define USE_IRDA(sport) (0) |
201 | #endif | 212 | #endif |
202 | 213 | ||
214 | static struct imx_uart_data imx_uart_devdata[] = { | ||
215 | [IMX1_UART] = { | ||
216 | .uts_reg = IMX1_UTS, | ||
217 | .devtype = IMX1_UART, | ||
218 | }, | ||
219 | [IMX21_UART] = { | ||
220 | .uts_reg = IMX21_UTS, | ||
221 | .devtype = IMX21_UART, | ||
222 | }, | ||
223 | }; | ||
224 | |||
225 | static struct platform_device_id imx_uart_devtype[] = { | ||
226 | { | ||
227 | .name = "imx1-uart", | ||
228 | .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART], | ||
229 | }, { | ||
230 | .name = "imx21-uart", | ||
231 | .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART], | ||
232 | }, { | ||
233 | /* sentinel */ | ||
234 | } | ||
235 | }; | ||
236 | MODULE_DEVICE_TABLE(platform, imx_uart_devtype); | ||
237 | |||
238 | static inline unsigned uts_reg(struct imx_port *sport) | ||
239 | { | ||
240 | return sport->devdata->uts_reg; | ||
241 | } | ||
242 | |||
243 | static inline int is_imx1_uart(struct imx_port *sport) | ||
244 | { | ||
245 | return sport->devdata->devtype == IMX1_UART; | ||
246 | } | ||
247 | |||
248 | static inline int is_imx21_uart(struct imx_port *sport) | ||
249 | { | ||
250 | return sport->devdata->devtype == IMX21_UART; | ||
251 | } | ||
252 | |||
203 | /* | 253 | /* |
204 | * Handle any change of modem status signal since we were last called. | 254 | * Handle any change of modem status signal since we were last called. |
205 | */ | 255 | */ |
@@ -326,7 +376,8 @@ static inline void imx_transmit_buffer(struct imx_port *sport) | |||
326 | struct circ_buf *xmit = &sport->port.state->xmit; | 376 | struct circ_buf *xmit = &sport->port.state->xmit; |
327 | 377 | ||
328 | while (!uart_circ_empty(xmit) && | 378 | while (!uart_circ_empty(xmit) && |
329 | !(readl(sport->port.membase + UTS) & UTS_TXFULL)) { | 379 | !(readl(sport->port.membase + uts_reg(sport)) |
380 | & UTS_TXFULL)) { | ||
330 | /* send xmit->buf[xmit->tail] | 381 | /* send xmit->buf[xmit->tail] |
331 | * out the port here */ | 382 | * out the port here */ |
332 | writel(xmit->buf[xmit->tail], sport->port.membase + URTX0); | 383 | writel(xmit->buf[xmit->tail], sport->port.membase + URTX0); |
@@ -373,7 +424,7 @@ static void imx_start_tx(struct uart_port *port) | |||
373 | writel(temp, sport->port.membase + UCR4); | 424 | writel(temp, sport->port.membase + UCR4); |
374 | } | 425 | } |
375 | 426 | ||
376 | if (readl(sport->port.membase + UTS) & UTS_TXEMPTY) | 427 | if (readl(sport->port.membase + uts_reg(sport)) & UTS_TXEMPTY) |
377 | imx_transmit_buffer(sport); | 428 | imx_transmit_buffer(sport); |
378 | } | 429 | } |
379 | 430 | ||
@@ -689,9 +740,9 @@ static int imx_startup(struct uart_port *port) | |||
689 | } | 740 | } |
690 | } | 741 | } |
691 | 742 | ||
692 | if (!cpu_is_mx1()) { | 743 | if (is_imx21_uart(sport)) { |
693 | temp = readl(sport->port.membase + UCR3); | 744 | temp = readl(sport->port.membase + UCR3); |
694 | temp |= MX2_UCR3_RXDMUXSEL; | 745 | temp |= IMX21_UCR3_RXDMUXSEL; |
695 | writel(temp, sport->port.membase + UCR3); | 746 | writel(temp, sport->port.membase + UCR3); |
696 | } | 747 | } |
697 | 748 | ||
@@ -923,9 +974,9 @@ imx_set_termios(struct uart_port *port, struct ktermios *termios, | |||
923 | writel(num, sport->port.membase + UBIR); | 974 | writel(num, sport->port.membase + UBIR); |
924 | writel(denom, sport->port.membase + UBMR); | 975 | writel(denom, sport->port.membase + UBMR); |
925 | 976 | ||
926 | if (!cpu_is_mx1()) | 977 | if (is_imx21_uart(sport)) |
927 | writel(sport->port.uartclk / div / 1000, | 978 | writel(sport->port.uartclk / div / 1000, |
928 | sport->port.membase + MX2_ONEMS); | 979 | sport->port.membase + IMX21_ONEMS); |
929 | 980 | ||
930 | writel(old_ucr1, sport->port.membase + UCR1); | 981 | writel(old_ucr1, sport->port.membase + UCR1); |
931 | 982 | ||
@@ -1041,7 +1092,7 @@ static void imx_console_putchar(struct uart_port *port, int ch) | |||
1041 | { | 1092 | { |
1042 | struct imx_port *sport = (struct imx_port *)port; | 1093 | struct imx_port *sport = (struct imx_port *)port; |
1043 | 1094 | ||
1044 | while (readl(sport->port.membase + UTS) & UTS_TXFULL) | 1095 | while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL) |
1045 | barrier(); | 1096 | barrier(); |
1046 | 1097 | ||
1047 | writel(ch, sport->port.membase + URTX0); | 1098 | writel(ch, sport->port.membase + URTX0); |
@@ -1062,8 +1113,8 @@ imx_console_write(struct console *co, const char *s, unsigned int count) | |||
1062 | ucr1 = old_ucr1 = readl(sport->port.membase + UCR1); | 1113 | ucr1 = old_ucr1 = readl(sport->port.membase + UCR1); |
1063 | old_ucr2 = readl(sport->port.membase + UCR2); | 1114 | old_ucr2 = readl(sport->port.membase + UCR2); |
1064 | 1115 | ||
1065 | if (cpu_is_mx1()) | 1116 | if (is_imx1_uart(sport)) |
1066 | ucr1 |= MX1_UCR1_UARTCLKEN; | 1117 | ucr1 |= IMX1_UCR1_UARTCLKEN; |
1067 | ucr1 |= UCR1_UARTEN; | 1118 | ucr1 |= UCR1_UARTEN; |
1068 | ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN); | 1119 | ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN); |
1069 | 1120 | ||
@@ -1262,6 +1313,7 @@ static int serial_imx_probe(struct platform_device *pdev) | |||
1262 | init_timer(&sport->timer); | 1313 | init_timer(&sport->timer); |
1263 | sport->timer.function = imx_timeout; | 1314 | sport->timer.function = imx_timeout; |
1264 | sport->timer.data = (unsigned long)sport; | 1315 | sport->timer.data = (unsigned long)sport; |
1316 | sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data; | ||
1265 | 1317 | ||
1266 | sport->clk = clk_get(&pdev->dev, "uart"); | 1318 | sport->clk = clk_get(&pdev->dev, "uart"); |
1267 | if (IS_ERR(sport->clk)) { | 1319 | if (IS_ERR(sport->clk)) { |
@@ -1340,6 +1392,7 @@ static struct platform_driver serial_imx_driver = { | |||
1340 | 1392 | ||
1341 | .suspend = serial_imx_suspend, | 1393 | .suspend = serial_imx_suspend, |
1342 | .resume = serial_imx_resume, | 1394 | .resume = serial_imx_resume, |
1395 | .id_table = imx_uart_devtype, | ||
1343 | .driver = { | 1396 | .driver = { |
1344 | .name = "imx-uart", | 1397 | .name = "imx-uart", |
1345 | .owner = THIS_MODULE, | 1398 | .owner = THIS_MODULE, |