spi: sun4i: allow transfers to set transmission speed

Allow transfers to set the transmission speed rather than using the
device max_speed_hz value. The SPI core makes sure that the speed_hz
value is always set on the transfer.

Signed-off-by: Marcus Weseloh <mweseloh42@gmail.com>
Signed-off-by: Mark Brown <broonie@kernel.org>

2 files changed, 8 insertions, 8 deletions

diff --git a/drivers/spi/spi-sun4i.c b/drivers/spi/spi-sun4i.c
index fbb0a4d74e91..f60a6d634d61 100644
--- a/drivers/spi/spi-sun4i.c
+++ b/drivers/spi/spi-sun4i.c
@@ -229,8 +229,8 @@ static int sun4i_spi_transfer_one(struct spi_master *master,
 
         /* Ensure that we have a parent clock fast enough */
         mclk_rate = clk_get_rate(sspi->mclk);
-        if (mclk_rate < (2 * spi->max_speed_hz)) {
-                clk_set_rate(sspi->mclk, 2 * spi->max_speed_hz);
+        if (mclk_rate < (2 * tfr->speed_hz)) {
+                clk_set_rate(sspi->mclk, 2 * tfr->speed_hz);
                 mclk_rate = clk_get_rate(sspi->mclk);
         }
 
@@ -248,14 +248,14 @@ static int sun4i_spi_transfer_one(struct spi_master *master,
          * First try CDR2, and if we can't reach the expected
          * frequency, fall back to CDR1.
          */
-        div = mclk_rate / (2 * spi->max_speed_hz);
+        div = mclk_rate / (2 * tfr->speed_hz);
         if (div <= (SUN4I_CLK_CTL_CDR2_MASK + 1)) {
                 if (div > 0)
                         div--;
 
                 reg = SUN4I_CLK_CTL_CDR2(div) | SUN4I_CLK_CTL_DRS;
         } else {
-                div = ilog2(mclk_rate) - ilog2(spi->max_speed_hz);
+                div = ilog2(mclk_rate) - ilog2(tfr->speed_hz);
                 reg = SUN4I_CLK_CTL_CDR1(div);
         }
 
diff --git a/drivers/spi/spi-sun6i.c b/drivers/spi/spi-sun6i.c
index ac48f59705a8..42e2c4bd690a 100644
--- a/drivers/spi/spi-sun6i.c
+++ b/drivers/spi/spi-sun6i.c
@@ -217,8 +217,8 @@ static int sun6i_spi_transfer_one(struct spi_master *master,
 
         /* Ensure that we have a parent clock fast enough */
         mclk_rate = clk_get_rate(sspi->mclk);
-        if (mclk_rate < (2 * spi->max_speed_hz)) {
-                clk_set_rate(sspi->mclk, 2 * spi->max_speed_hz);
+        if (mclk_rate < (2 * tfr->speed_hz)) {
+                clk_set_rate(sspi->mclk, 2 * tfr->speed_hz);
                 mclk_rate = clk_get_rate(sspi->mclk);
         }
 
@@ -236,14 +236,14 @@ static int sun6i_spi_transfer_one(struct spi_master *master,
          * First try CDR2, and if we can't reach the expected
          * frequency, fall back to CDR1.
          */
-        div = mclk_rate / (2 * spi->max_speed_hz);
+        div = mclk_rate / (2 * tfr->speed_hz);
         if (div <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) {
                 if (div > 0)
                         div--;
 
                 reg = SUN6I_CLK_CTL_CDR2(div) | SUN6I_CLK_CTL_DRS;
         } else {
-                div = ilog2(mclk_rate) - ilog2(spi->max_speed_hz);
+                div = ilog2(mclk_rate) - ilog2(tfr->speed_hz);
                 reg = SUN6I_CLK_CTL_CDR1(div);
         }