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authorHaojian Zhuang <haojian.zhuang@linaro.org>2013-03-13 04:23:57 -0400
committerLinus Walleij <linus.walleij@linaro.org>2013-03-27 17:19:50 -0400
commit62194200e5e383af2085faf35b6f009364446069 (patch)
treef88cc882cdc66084d4e532fd9516650aeecaf003 /drivers/pinctrl/pinctrl-pxa3xx.h
parentfdba2d065cb2891b3006424b50fbc6406ce66672 (diff)
pinctrl: remove pxa pinctrl driver
pinctrl-pxa driver doesn't support well on DT mode. Now pinctrl-single could support DT mode & pin configuration. Use pinctrl-single driver to support MMP/PXA silicons instead. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/pinctrl-pxa3xx.h')
-rw-r--r--drivers/pinctrl/pinctrl-pxa3xx.h262
1 files changed, 0 insertions, 262 deletions
diff --git a/drivers/pinctrl/pinctrl-pxa3xx.h b/drivers/pinctrl/pinctrl-pxa3xx.h
deleted file mode 100644
index 92fad0880834..000000000000
--- a/drivers/pinctrl/pinctrl-pxa3xx.h
+++ /dev/null
@@ -1,262 +0,0 @@
1/*
2 * linux/drivers/pinctrl/pinctrl-pxa3xx.h
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * publishhed by the Free Software Foundation.
7 *
8 * Copyright (C) 2011, Marvell Technology Group Ltd.
9 *
10 * Author: Haojian Zhuang <haojian.zhuang@marvell.com>
11 *
12 */
13
14#ifndef __PINCTRL_PXA3XX_H
15
16#include <linux/pinctrl/pinctrl.h>
17#include <linux/pinctrl/pinmux.h>
18
19#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x)
20
21#define PXA3xx_MUX_GPIO 0
22
23#define PXA3xx_MAX_MUX 8
24#define MFPR_FUNC_MASK 0x7
25
26enum pxa_cpu_type {
27 PINCTRL_INVALID = 0,
28 PINCTRL_PXA300,
29 PINCTRL_PXA310,
30 PINCTRL_PXA320,
31 PINCTRL_PXA168,
32 PINCTRL_PXA910,
33 PINCTRL_PXA930,
34 PINCTRL_PXA955,
35 PINCTRL_MMP2,
36 PINCTRL_MAX,
37};
38
39struct pxa3xx_mfp_pin {
40 const char *name;
41 const unsigned int pin;
42 const unsigned int mfpr; /* register offset */
43 const unsigned short func[8];
44};
45
46struct pxa3xx_pin_group {
47 const char *name;
48 const unsigned mux;
49 const unsigned *pins;
50 const unsigned npins;
51};
52
53struct pxa3xx_pmx_func {
54 const char *name;
55 const char * const * groups;
56 const unsigned num_groups;
57};
58
59struct pxa3xx_pinmux_info {
60 struct device *dev;
61 struct pinctrl_dev *pctrl;
62 enum pxa_cpu_type cputype;
63 void __iomem *virt_base;
64
65 struct pxa3xx_mfp_pin *mfp;
66 unsigned int num_mfp;
67 struct pxa3xx_pin_group *grps;
68 unsigned int num_grps;
69 struct pxa3xx_pmx_func *funcs;
70 unsigned int num_funcs;
71 unsigned int num_gpio;
72 struct pinctrl_desc *desc;
73 struct pinctrl_pin_desc *pads;
74 unsigned int num_pads;
75
76 unsigned ds_mask; /* drive strength mask */
77 unsigned ds_shift; /* drive strength shift */
78 unsigned slp_mask; /* sleep mask */
79 unsigned slp_input_low;
80 unsigned slp_input_high;
81 unsigned slp_output_low;
82 unsigned slp_output_high;
83 unsigned slp_float;
84};
85
86enum pxa3xx_pin_list {
87 GPIO0 = 0,
88 GPIO1,
89 GPIO2,
90 GPIO3,
91 GPIO4,
92 GPIO5,
93 GPIO6,
94 GPIO7,
95 GPIO8,
96 GPIO9,
97 GPIO10, /* 10 */
98 GPIO11,
99 GPIO12,
100 GPIO13,
101 GPIO14,
102 GPIO15,
103 GPIO16,
104 GPIO17,
105 GPIO18,
106 GPIO19,
107 GPIO20, /* 20 */
108 GPIO21,
109 GPIO22,
110 GPIO23,
111 GPIO24,
112 GPIO25,
113 GPIO26,
114 GPIO27,
115 GPIO28,
116 GPIO29,
117 GPIO30, /* 30 */
118 GPIO31,
119 GPIO32,
120 GPIO33,
121 GPIO34,
122 GPIO35,
123 GPIO36,
124 GPIO37,
125 GPIO38,
126 GPIO39,
127 GPIO40, /* 40 */
128 GPIO41,
129 GPIO42,
130 GPIO43,
131 GPIO44,
132 GPIO45,
133 GPIO46,
134 GPIO47,
135 GPIO48,
136 GPIO49,
137 GPIO50, /* 50 */
138 GPIO51,
139 GPIO52,
140 GPIO53,
141 GPIO54,
142 GPIO55,
143 GPIO56,
144 GPIO57,
145 GPIO58,
146 GPIO59,
147 GPIO60, /* 60 */
148 GPIO61,
149 GPIO62,
150 GPIO63,
151 GPIO64,
152 GPIO65,
153 GPIO66,
154 GPIO67,
155 GPIO68,
156 GPIO69,
157 GPIO70, /* 70 */
158 GPIO71,
159 GPIO72,
160 GPIO73,
161 GPIO74,
162 GPIO75,
163 GPIO76,
164 GPIO77,
165 GPIO78,
166 GPIO79,
167 GPIO80, /* 80 */
168 GPIO81,
169 GPIO82,
170 GPIO83,
171 GPIO84,
172 GPIO85,
173 GPIO86,
174 GPIO87,
175 GPIO88,
176 GPIO89,
177 GPIO90, /* 90 */
178 GPIO91,
179 GPIO92,
180 GPIO93,
181 GPIO94,
182 GPIO95,
183 GPIO96,
184 GPIO97,
185 GPIO98,
186 GPIO99,
187 GPIO100, /* 100 */
188 GPIO101,
189 GPIO102,
190 GPIO103,
191 GPIO104,
192 GPIO105,
193 GPIO106,
194 GPIO107,
195 GPIO108,
196 GPIO109,
197 GPIO110, /* 110 */
198 GPIO111,
199 GPIO112,
200 GPIO113,
201 GPIO114,
202 GPIO115,
203 GPIO116,
204 GPIO117,
205 GPIO118,
206 GPIO119,
207 GPIO120, /* 120 */
208 GPIO121,
209 GPIO122,
210 GPIO123,
211 GPIO124,
212 GPIO125,
213 GPIO126,
214 GPIO127,
215 GPIO128,
216 GPIO129,
217 GPIO130, /* 130 */
218 GPIO131,
219 GPIO132,
220 GPIO133,
221 GPIO134,
222 GPIO135,
223 GPIO136,
224 GPIO137,
225 GPIO138,
226 GPIO139,
227 GPIO140, /* 140 */
228 GPIO141,
229 GPIO142,
230 GPIO143,
231 GPIO144,
232 GPIO145,
233 GPIO146,
234 GPIO147,
235 GPIO148,
236 GPIO149,
237 GPIO150, /* 150 */
238 GPIO151,
239 GPIO152,
240 GPIO153,
241 GPIO154,
242 GPIO155,
243 GPIO156,
244 GPIO157,
245 GPIO158,
246 GPIO159,
247 GPIO160, /* 160 */
248 GPIO161,
249 GPIO162,
250 GPIO163,
251 GPIO164,
252 GPIO165,
253 GPIO166,
254 GPIO167,
255 GPIO168,
256 GPIO169,
257};
258
259extern int pxa3xx_pinctrl_register(struct platform_device *pdev,
260 struct pxa3xx_pinmux_info *info);
261extern int pxa3xx_pinctrl_unregister(struct platform_device *pdev);
262#endif /* __PINCTRL_PXA3XX_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-25 10:32:15 -0500