diff options
author | Vasanthakumar Thiagarajan <vasanth@atheros.com> | 2011-04-19 09:59:19 -0400 |
---|---|---|
committer | John W. Linville <linville@tuxdriver.com> | 2011-04-25 14:50:13 -0400 |
commit | 79d1d2b8a34fd36e63cc7f5267cf79217a44edcc (patch) | |
tree | 54ad5882a17f27abd6b54735f73725befe833c8e /drivers/net/wireless/ath/ath9k/mac.c | |
parent | ecb1d385ad61001ff85407e5370a40934a1cc50b (diff) |
ath9k_hw: Disable INTR_HOST1_FATAL to avoid interrupt strom with ar9430
Signed-off-by: Vasanthakumar Thiagarajan <vasanth@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/ath/ath9k/mac.c')
-rw-r--r-- | drivers/net/wireless/ath/ath9k/mac.c | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/drivers/net/wireless/ath/ath9k/mac.c b/drivers/net/wireless/ath/ath9k/mac.c index 6f431cbff38a..d86b8393b8dd 100644 --- a/drivers/net/wireless/ath/ath9k/mac.c +++ b/drivers/net/wireless/ath/ath9k/mac.c | |||
@@ -793,10 +793,14 @@ EXPORT_SYMBOL(ath9k_hw_disable_interrupts); | |||
793 | void ath9k_hw_enable_interrupts(struct ath_hw *ah) | 793 | void ath9k_hw_enable_interrupts(struct ath_hw *ah) |
794 | { | 794 | { |
795 | struct ath_common *common = ath9k_hw_common(ah); | 795 | struct ath_common *common = ath9k_hw_common(ah); |
796 | u32 sync_default = AR_INTR_SYNC_DEFAULT; | ||
796 | 797 | ||
797 | if (!(ah->imask & ATH9K_INT_GLOBAL)) | 798 | if (!(ah->imask & ATH9K_INT_GLOBAL)) |
798 | return; | 799 | return; |
799 | 800 | ||
801 | if (AR_SREV_9340(ah)) | ||
802 | sync_default &= ~AR_INTR_SYNC_HOST1_FATAL; | ||
803 | |||
800 | ath_dbg(common, ATH_DBG_INTERRUPT, "enable IER\n"); | 804 | ath_dbg(common, ATH_DBG_INTERRUPT, "enable IER\n"); |
801 | REG_WRITE(ah, AR_IER, AR_IER_ENABLE); | 805 | REG_WRITE(ah, AR_IER, AR_IER_ENABLE); |
802 | if (!AR_SREV_9100(ah)) { | 806 | if (!AR_SREV_9100(ah)) { |
@@ -805,10 +809,8 @@ void ath9k_hw_enable_interrupts(struct ath_hw *ah) | |||
805 | REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ); | 809 | REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ); |
806 | 810 | ||
807 | 811 | ||
808 | REG_WRITE(ah, AR_INTR_SYNC_ENABLE, | 812 | REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default); |
809 | AR_INTR_SYNC_DEFAULT); | 813 | REG_WRITE(ah, AR_INTR_SYNC_MASK, sync_default); |
810 | REG_WRITE(ah, AR_INTR_SYNC_MASK, | ||
811 | AR_INTR_SYNC_DEFAULT); | ||
812 | } | 814 | } |
813 | ath_dbg(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n", | 815 | ath_dbg(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n", |
814 | REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER)); | 816 | REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER)); |