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authorYaniv Rosner <yaniv.rosner@broadcom.com>2012-04-03 14:41:31 -0400
committerDavid S. Miller <davem@davemloft.net>2012-04-04 01:38:00 -0400
commit8f73f0b97208d9e1142fd32236b5d990ee4ed4b3 (patch)
treeb6a12441335460d010d0861bfdba28c1fa123017 /drivers/net/ethernet/broadcom
parent963052348fd33221d9ae4212d6cdaa2346e2678e (diff)
bnx2x: Change comments and white spaces
A semantic patch, fixing style issues in the bnx2x's link code. Signed-off-by: Yaniv Rosner <yaniv.rosner@broadcom.com> Signed-off-by: Yuval Mintz <yuvalmin@broadcom.com> Signed-off-by: Eilon Greenstein <eilong@broadcom> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/broadcom')
-rw-r--r--drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c660
1 files changed, 241 insertions, 419 deletions
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c
index e255cc49f81f..71e5bd00e8be 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c
@@ -138,7 +138,6 @@
138 138
139 139
140 140
141/* */
142#define SFP_EEPROM_CON_TYPE_ADDR 0x2 141#define SFP_EEPROM_CON_TYPE_ADDR 0x2
143 #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7 142 #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7
144 #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21 143 #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21
@@ -404,8 +403,7 @@ static void bnx2x_ets_e2e3a0_disabled(struct link_params *params)
404 403
405 DP(NETIF_MSG_LINK, "ETS E2E3 disabled configuration\n"); 404 DP(NETIF_MSG_LINK, "ETS E2E3 disabled configuration\n");
406 405
407 /* 406 /* mapping between entry priority to client number (0,1,2 -debug and
408 * mapping between entry priority to client number (0,1,2 -debug and
409 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST) 407 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
410 * 3bits client num. 408 * 3bits client num.
411 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0 409 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
@@ -413,8 +411,7 @@ static void bnx2x_ets_e2e3a0_disabled(struct link_params *params)
413 */ 411 */
414 412
415 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688); 413 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);
416 /* 414 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
417 * Bitmap of 5bits length. Each bit specifies whether the entry behaves
418 * as strict. Bits 0,1,2 - debug and management entries, 3 - 415 * as strict. Bits 0,1,2 - debug and management entries, 3 -
419 * COS0 entry, 4 - COS1 entry. 416 * COS0 entry, 4 - COS1 entry.
420 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT 417 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
@@ -425,13 +422,11 @@ static void bnx2x_ets_e2e3a0_disabled(struct link_params *params)
425 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7); 422 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
426 /* defines which entries (clients) are subjected to WFQ arbitration */ 423 /* defines which entries (clients) are subjected to WFQ arbitration */
427 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0); 424 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
428 /* 425 /* For strict priority entries defines the number of consecutive
429 * For strict priority entries defines the number of consecutive
430 * slots for the highest priority. 426 * slots for the highest priority.
431 */ 427 */
432 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); 428 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
433 /* 429 /* mapping between the CREDIT_WEIGHT registers and actual client
434 * mapping between the CREDIT_WEIGHT registers and actual client
435 * numbers 430 * numbers
436 */ 431 */
437 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0); 432 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);
@@ -443,8 +438,7 @@ static void bnx2x_ets_e2e3a0_disabled(struct link_params *params)
443 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0); 438 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);
444 /* ETS mode disable */ 439 /* ETS mode disable */
445 REG_WR(bp, PBF_REG_ETS_ENABLED, 0); 440 REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
446 /* 441 /* If ETS mode is enabled (there is no strict priority) defines a WFQ
447 * If ETS mode is enabled (there is no strict priority) defines a WFQ
448 * weight for COS0/COS1. 442 * weight for COS0/COS1.
449 */ 443 */
450 REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710); 444 REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710);
@@ -471,10 +465,9 @@ static u32 bnx2x_ets_get_min_w_val_nig(const struct link_vars *vars)
471 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS; 465 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS;
472 } else 466 } else
473 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS; 467 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
474 /** 468 /* If the link isn't up (static configuration for example ) The
475 * If the link isn't up (static configuration for example ) The 469 * link will be according to 20GBPS.
476 * link will be according to 20GBPS. 470 */
477 */
478 return min_w_val; 471 return min_w_val;
479} 472}
480/****************************************************************************** 473/******************************************************************************
@@ -538,8 +531,7 @@ static void bnx2x_ets_e3b0_nig_disabled(const struct link_params *params,
538 struct bnx2x *bp = params->bp; 531 struct bnx2x *bp = params->bp;
539 const u8 port = params->port; 532 const u8 port = params->port;
540 const u32 min_w_val = bnx2x_ets_get_min_w_val_nig(vars); 533 const u32 min_w_val = bnx2x_ets_get_min_w_val_nig(vars);
541 /** 534 /* Mapping between entry priority to client number (0,1,2 -debug and
542 * mapping between entry priority to client number (0,1,2 -debug and
543 * management clients, 3 - COS0 client, 4 - COS1, ... 8 - 535 * management clients, 3 - COS0 client, 4 - COS1, ... 8 -
544 * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by 536 * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by
545 * reset value or init tool 537 * reset value or init tool
@@ -551,18 +543,14 @@ static void bnx2x_ets_e3b0_nig_disabled(const struct link_params *params,
551 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210); 543 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210);
552 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8); 544 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8);
553 } 545 }
554 /** 546 /* For strict priority entries defines the number of consecutive
555 * For strict priority entries defines the number of consecutive 547 * slots for the highest priority.
556 * slots for the highest priority. 548 */
557 */
558 /* TODO_ETS - Should be done by reset value or init tool */
559 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS : 549 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS :
560 NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); 550 NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
561 /** 551 /* Mapping between the CREDIT_WEIGHT registers and actual client
562 * mapping between the CREDIT_WEIGHT registers and actual client
563 * numbers 552 * numbers
564 */ 553 */
565 /* TODO_ETS - Should be done by reset value or init tool */
566 if (port) { 554 if (port) {
567 /*Port 1 has 6 COS*/ 555 /*Port 1 has 6 COS*/
568 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543); 556 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543);
@@ -574,8 +562,7 @@ static void bnx2x_ets_e3b0_nig_disabled(const struct link_params *params,
574 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5); 562 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5);
575 } 563 }
576 564
577 /** 565 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
578 * Bitmap of 5bits length. Each bit specifies whether the entry behaves
579 * as strict. Bits 0,1,2 - debug and management entries, 3 - 566 * as strict. Bits 0,1,2 - debug and management entries, 3 -
580 * COS0 entry, 4 - COS1 entry. 567 * COS0 entry, 4 - COS1 entry.
581 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT 568 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
@@ -590,13 +577,12 @@ static void bnx2x_ets_e3b0_nig_disabled(const struct link_params *params,
590 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ : 577 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
591 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0); 578 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
592 579
593 /** 580 /* Please notice the register address are note continuous and a
594 * Please notice the register address are note continuous and a 581 * for here is note appropriate.In 2 port mode port0 only COS0-5
595 * for here is note appropriate.In 2 port mode port0 only COS0-5 582 * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4
596 * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4 583 * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT
597 * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT 584 * are never used for WFQ
598 * are never used for WFQ 585 */
599 */
600 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 : 586 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
601 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0); 587 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0);
602 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 : 588 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
@@ -633,10 +619,9 @@ static void bnx2x_ets_e3b0_set_credit_upper_bound_pbf(
633 u32 base_upper_bound = 0; 619 u32 base_upper_bound = 0;
634 u8 max_cos = 0; 620 u8 max_cos = 0;
635 u8 i = 0; 621 u8 i = 0;
636 /** 622 /* In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4
637 * In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4 623 * port mode port1 has COS0-2 that can be used for WFQ.
638 * port mode port1 has COS0-2 that can be used for WFQ. 624 */
639 */
640 if (!port) { 625 if (!port) {
641 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0; 626 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0;
642 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0; 627 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
@@ -666,8 +651,7 @@ static void bnx2x_ets_e3b0_pbf_disabled(const struct link_params *params)
666 u32 base_weight = 0; 651 u32 base_weight = 0;
667 u8 max_cos = 0; 652 u8 max_cos = 0;
668 653
669 /** 654 /* Mapping between entry priority to client number 0 - COS0
670 * mapping between entry priority to client number 0 - COS0
671 * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num. 655 * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num.
672 * TODO_ETS - Should be done by reset value or init tool 656 * TODO_ETS - Should be done by reset value or init tool
673 */ 657 */
@@ -695,10 +679,9 @@ static void bnx2x_ets_e3b0_pbf_disabled(const struct link_params *params)
695 679
696 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 : 680 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
697 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0); 681 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0);
698 /** 682 /* In 2 port mode port0 has COS0-5 that can be used for WFQ.
699 * In 2 port mode port0 has COS0-5 that can be used for WFQ. 683 * In 4 port mode port1 has COS0-2 that can be used for WFQ.
700 * In 4 port mode port1 has COS0-2 that can be used for WFQ. 684 */
701 */
702 if (!port) { 685 if (!port) {
703 base_weight = PBF_REG_COS0_WEIGHT_P0; 686 base_weight = PBF_REG_COS0_WEIGHT_P0;
704 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0; 687 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
@@ -738,7 +721,7 @@ static int bnx2x_ets_e3b0_disabled(const struct link_params *params,
738/****************************************************************************** 721/******************************************************************************
739* Description: 722* Description:
740* Disable will return basicly the values to init values. 723* Disable will return basicly the values to init values.
741*. 724*
742******************************************************************************/ 725******************************************************************************/
743int bnx2x_ets_disabled(struct link_params *params, 726int bnx2x_ets_disabled(struct link_params *params,
744 struct link_vars *vars) 727 struct link_vars *vars)
@@ -867,7 +850,7 @@ static int bnx2x_ets_e3b0_set_cos_bw(struct bnx2x *bp,
867/****************************************************************************** 850/******************************************************************************
868* Description: 851* Description:
869* Calculate the total BW.A value of 0 isn't legal. 852* Calculate the total BW.A value of 0 isn't legal.
870*. 853*
871******************************************************************************/ 854******************************************************************************/
872static int bnx2x_ets_e3b0_get_total_bw( 855static int bnx2x_ets_e3b0_get_total_bw(
873 const struct link_params *params, 856 const struct link_params *params,
@@ -879,7 +862,6 @@ static int bnx2x_ets_e3b0_get_total_bw(
879 u8 is_bw_cos_exist = 0; 862 u8 is_bw_cos_exist = 0;
880 863
881 *total_bw = 0 ; 864 *total_bw = 0 ;
882
883 /* Calculate total BW requested */ 865 /* Calculate total BW requested */
884 for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) { 866 for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) {
885 if (ets_params->cos[cos_idx].state == bnx2x_cos_state_bw) { 867 if (ets_params->cos[cos_idx].state == bnx2x_cos_state_bw) {
@@ -887,10 +869,9 @@ static int bnx2x_ets_e3b0_get_total_bw(
887 if (!ets_params->cos[cos_idx].params.bw_params.bw) { 869 if (!ets_params->cos[cos_idx].params.bw_params.bw) {
888 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config BW" 870 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config BW"
889 "was set to 0\n"); 871 "was set to 0\n");
890 /* 872 /* This is to prevent a state when ramrods
891 * This is to prevent a state when ramrods
892 * can't be sent 873 * can't be sent
893 */ 874 */
894 ets_params->cos[cos_idx].params.bw_params.bw 875 ets_params->cos[cos_idx].params.bw_params.bw
895 = 1; 876 = 1;
896 } 877 }
@@ -908,8 +889,7 @@ static int bnx2x_ets_e3b0_get_total_bw(
908 } 889 }
909 DP(NETIF_MSG_LINK, 890 DP(NETIF_MSG_LINK,
910 "bnx2x_ets_E3B0_config total BW should be 100\n"); 891 "bnx2x_ets_E3B0_config total BW should be 100\n");
911 /* 892 /* We can handle a case whre the BW isn't 100 this can happen
912 * We can handle a case whre the BW isn't 100 this can happen
913 * if the TC are joined. 893 * if the TC are joined.
914 */ 894 */
915 } 895 }
@@ -919,7 +899,7 @@ static int bnx2x_ets_e3b0_get_total_bw(
919/****************************************************************************** 899/******************************************************************************
920* Description: 900* Description:
921* Invalidate all the sp_pri_to_cos. 901* Invalidate all the sp_pri_to_cos.
922*. 902*
923******************************************************************************/ 903******************************************************************************/
924static void bnx2x_ets_e3b0_sp_pri_to_cos_init(u8 *sp_pri_to_cos) 904static void bnx2x_ets_e3b0_sp_pri_to_cos_init(u8 *sp_pri_to_cos)
925{ 905{
@@ -931,7 +911,7 @@ static void bnx2x_ets_e3b0_sp_pri_to_cos_init(u8 *sp_pri_to_cos)
931* Description: 911* Description:
932* Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers 912* Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
933* according to sp_pri_to_cos. 913* according to sp_pri_to_cos.
934*. 914*
935******************************************************************************/ 915******************************************************************************/
936static int bnx2x_ets_e3b0_sp_pri_to_cos_set(const struct link_params *params, 916static int bnx2x_ets_e3b0_sp_pri_to_cos_set(const struct link_params *params,
937 u8 *sp_pri_to_cos, const u8 pri, 917 u8 *sp_pri_to_cos, const u8 pri,
@@ -964,7 +944,7 @@ static int bnx2x_ets_e3b0_sp_pri_to_cos_set(const struct link_params *params,
964* Description: 944* Description:
965* Returns the correct value according to COS and priority in 945* Returns the correct value according to COS and priority in
966* the sp_pri_cli register. 946* the sp_pri_cli register.
967*. 947*
968******************************************************************************/ 948******************************************************************************/
969static u64 bnx2x_e3b0_sp_get_pri_cli_reg(const u8 cos, const u8 cos_offset, 949static u64 bnx2x_e3b0_sp_get_pri_cli_reg(const u8 cos, const u8 cos_offset,
970 const u8 pri_set, 950 const u8 pri_set,
@@ -981,7 +961,7 @@ static u64 bnx2x_e3b0_sp_get_pri_cli_reg(const u8 cos, const u8 cos_offset,
981* Description: 961* Description:
982* Returns the correct value according to COS and priority in the 962* Returns the correct value according to COS and priority in the
983* sp_pri_cli register for NIG. 963* sp_pri_cli register for NIG.
984*. 964*
985******************************************************************************/ 965******************************************************************************/
986static u64 bnx2x_e3b0_sp_get_pri_cli_reg_nig(const u8 cos, const u8 pri_set) 966static u64 bnx2x_e3b0_sp_get_pri_cli_reg_nig(const u8 cos, const u8 pri_set)
987{ 967{
@@ -997,7 +977,7 @@ static u64 bnx2x_e3b0_sp_get_pri_cli_reg_nig(const u8 cos, const u8 pri_set)
997* Description: 977* Description:
998* Returns the correct value according to COS and priority in the 978* Returns the correct value according to COS and priority in the
999* sp_pri_cli register for PBF. 979* sp_pri_cli register for PBF.
1000*. 980*
1001******************************************************************************/ 981******************************************************************************/
1002static u64 bnx2x_e3b0_sp_get_pri_cli_reg_pbf(const u8 cos, const u8 pri_set) 982static u64 bnx2x_e3b0_sp_get_pri_cli_reg_pbf(const u8 cos, const u8 pri_set)
1003{ 983{
@@ -1013,7 +993,7 @@ static u64 bnx2x_e3b0_sp_get_pri_cli_reg_pbf(const u8 cos, const u8 pri_set)
1013* Description: 993* Description:
1014* Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers 994* Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
1015* according to sp_pri_to_cos.(which COS has higher priority) 995* according to sp_pri_to_cos.(which COS has higher priority)
1016*. 996*
1017******************************************************************************/ 997******************************************************************************/
1018static int bnx2x_ets_e3b0_sp_set_pri_cli_reg(const struct link_params *params, 998static int bnx2x_ets_e3b0_sp_set_pri_cli_reg(const struct link_params *params,
1019 u8 *sp_pri_to_cos) 999 u8 *sp_pri_to_cos)
@@ -1149,8 +1129,7 @@ int bnx2x_ets_e3b0_config(const struct link_params *params,
1149 return -EINVAL; 1129 return -EINVAL;
1150 } 1130 }
1151 1131
1152 /* 1132 /* Upper bound is set according to current link speed (min_w_val
1153 * Upper bound is set according to current link speed (min_w_val
1154 * should be the same for upper bound and COS credit val). 1133 * should be the same for upper bound and COS credit val).
1155 */ 1134 */
1156 bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig); 1135 bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig);
@@ -1160,8 +1139,7 @@ int bnx2x_ets_e3b0_config(const struct link_params *params,
1160 for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) { 1139 for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) {
1161 if (bnx2x_cos_state_bw == ets_params->cos[cos_entry].state) { 1140 if (bnx2x_cos_state_bw == ets_params->cos[cos_entry].state) {
1162 cos_bw_bitmap |= (1 << cos_entry); 1141 cos_bw_bitmap |= (1 << cos_entry);
1163 /* 1142 /* The function also sets the BW in HW(not the mappin
1164 * The function also sets the BW in HW(not the mappin
1165 * yet) 1143 * yet)
1166 */ 1144 */
1167 bnx2x_status = bnx2x_ets_e3b0_set_cos_bw( 1145 bnx2x_status = bnx2x_ets_e3b0_set_cos_bw(
@@ -1217,14 +1195,12 @@ static void bnx2x_ets_bw_limit_common(const struct link_params *params)
1217 /* ETS disabled configuration */ 1195 /* ETS disabled configuration */
1218 struct bnx2x *bp = params->bp; 1196 struct bnx2x *bp = params->bp;
1219 DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n"); 1197 DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1220 /* 1198 /* Defines which entries (clients) are subjected to WFQ arbitration
1221 * defines which entries (clients) are subjected to WFQ arbitration
1222 * COS0 0x8 1199 * COS0 0x8
1223 * COS1 0x10 1200 * COS1 0x10
1224 */ 1201 */
1225 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18); 1202 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);
1226 /* 1203 /* Mapping between the ARB_CREDIT_WEIGHT registers and actual
1227 * mapping between the ARB_CREDIT_WEIGHT registers and actual
1228 * client numbers (WEIGHT_0 does not actually have to represent 1204 * client numbers (WEIGHT_0 does not actually have to represent
1229 * client 0) 1205 * client 0)
1230 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0 1206 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
@@ -1242,8 +1218,7 @@ static void bnx2x_ets_bw_limit_common(const struct link_params *params)
1242 1218
1243 /* Defines the number of consecutive slots for the strict priority */ 1219 /* Defines the number of consecutive slots for the strict priority */
1244 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0); 1220 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
1245 /* 1221 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
1246 * Bitmap of 5bits length. Each bit specifies whether the entry behaves
1247 * as strict. Bits 0,1,2 - debug and management entries, 3 - COS0 1222 * as strict. Bits 0,1,2 - debug and management entries, 3 - COS0
1248 * entry, 4 - COS1 entry. 1223 * entry, 4 - COS1 entry.
1249 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT 1224 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
@@ -1298,8 +1273,7 @@ int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos)
1298 u32 val = 0; 1273 u32 val = 0;
1299 1274
1300 DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n"); 1275 DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n");
1301 /* 1276 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
1302 * Bitmap of 5bits length. Each bit specifies whether the entry behaves
1303 * as strict. Bits 0,1,2 - debug and management entries, 1277 * as strict. Bits 0,1,2 - debug and management entries,
1304 * 3 - COS0 entry, 4 - COS1 entry. 1278 * 3 - COS0 entry, 4 - COS1 entry.
1305 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT 1279 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
@@ -1307,8 +1281,7 @@ int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos)
1307 * MCP and debug are strict 1281 * MCP and debug are strict
1308 */ 1282 */
1309 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F); 1283 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F);
1310 /* 1284 /* For strict priority entries defines the number of consecutive slots
1311 * For strict priority entries defines the number of consecutive slots
1312 * for the highest priority. 1285 * for the highest priority.
1313 */ 1286 */
1314 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); 1287 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
@@ -1320,8 +1293,7 @@ int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos)
1320 /* Defines the number of consecutive slots for the strict priority */ 1293 /* Defines the number of consecutive slots for the strict priority */
1321 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos); 1294 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos);
1322 1295
1323 /* 1296 /* Mapping between entry priority to client number (0,1,2 -debug and
1324 * mapping between entry priority to client number (0,1,2 -debug and
1325 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST) 1297 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
1326 * 3bits client num. 1298 * 3bits client num.
1327 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0 1299 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
@@ -1356,15 +1328,12 @@ static void bnx2x_update_pfc_xmac(struct link_params *params,
1356 if (!(params->feature_config_flags & 1328 if (!(params->feature_config_flags &
1357 FEATURE_CONFIG_PFC_ENABLED)) { 1329 FEATURE_CONFIG_PFC_ENABLED)) {
1358 1330
1359 /* 1331 /* RX flow control - Process pause frame in receive direction
1360 * RX flow control - Process pause frame in receive direction
1361 */ 1332 */
1362 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX) 1333 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1363 pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN; 1334 pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN;
1364 1335
1365 /* 1336 /* TX flow control - Send pause packet when buffer is full */
1366 * TX flow control - Send pause packet when buffer is full
1367 */
1368 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) 1337 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1369 pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN; 1338 pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN;
1370 } else {/* PFC support */ 1339 } else {/* PFC support */
@@ -1450,8 +1419,7 @@ void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars,
1450static void bnx2x_set_mdio_clk(struct bnx2x *bp, u32 chip_id, u8 port) 1419static void bnx2x_set_mdio_clk(struct bnx2x *bp, u32 chip_id, u8 port)
1451{ 1420{
1452 u32 mode, emac_base; 1421 u32 mode, emac_base;
1453 /** 1422 /* Set clause 45 mode, slow down the MDIO clock to 2.5MHz
1454 * Set clause 45 mode, slow down the MDIO clock to 2.5MHz
1455 * (a value of 49==0x31) and make sure that the AUTO poll is off 1423 * (a value of 49==0x31) and make sure that the AUTO poll is off
1456 */ 1424 */
1457 1425
@@ -1571,15 +1539,6 @@ static void bnx2x_umac_enable(struct link_params *params,
1571 1539
1572 DP(NETIF_MSG_LINK, "enabling UMAC\n"); 1540 DP(NETIF_MSG_LINK, "enabling UMAC\n");
1573 1541
1574 /**
1575 * This register determines on which events the MAC will assert
1576 * error on the i/f to the NIG along w/ EOP.
1577 */
1578
1579 /**
1580 * BD REG_WR(bp, NIG_REG_P0_MAC_RSV_ERR_MASK +
1581 * params->port*0x14, 0xfffff.
1582 */
1583 /* This register opens the gate for the UMAC despite its name */ 1542 /* This register opens the gate for the UMAC despite its name */
1584 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1); 1543 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
1585 1544
@@ -1642,8 +1601,7 @@ static void bnx2x_umac_enable(struct link_params *params,
1642 val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA; 1601 val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA;
1643 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); 1602 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1644 1603
1645 /* 1604 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
1646 * Maximum Frame Length (RW). Defines a 14-Bit maximum frame
1647 * length used by the MAC receive logic to check frames. 1605 * length used by the MAC receive logic to check frames.
1648 */ 1606 */
1649 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710); 1607 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
@@ -1659,8 +1617,7 @@ static void bnx2x_xmac_init(struct link_params *params, u32 max_speed)
1659 struct bnx2x *bp = params->bp; 1617 struct bnx2x *bp = params->bp;
1660 u32 is_port4mode = bnx2x_is_4_port_mode(bp); 1618 u32 is_port4mode = bnx2x_is_4_port_mode(bp);
1661 1619
1662 /* 1620 /* In 4-port mode, need to set the mode only once, so if XMAC is
1663 * In 4-port mode, need to set the mode only once, so if XMAC is
1664 * already out of reset, it means the mode has already been set, 1621 * already out of reset, it means the mode has already been set,
1665 * and it must not* reset the XMAC again, since it controls both 1622 * and it must not* reset the XMAC again, since it controls both
1666 * ports of the path 1623 * ports of the path
@@ -1684,13 +1641,13 @@ static void bnx2x_xmac_init(struct link_params *params, u32 max_speed)
1684 if (is_port4mode) { 1641 if (is_port4mode) {
1685 DP(NETIF_MSG_LINK, "Init XMAC to 2 ports x 10G per path\n"); 1642 DP(NETIF_MSG_LINK, "Init XMAC to 2 ports x 10G per path\n");
1686 1643
1687 /* Set the number of ports on the system side to up to 2 */ 1644 /* Set the number of ports on the system side to up to 2 */
1688 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 1); 1645 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 1);
1689 1646
1690 /* Set the number of ports on the Warp Core to 10G */ 1647 /* Set the number of ports on the Warp Core to 10G */
1691 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3); 1648 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1692 } else { 1649 } else {
1693 /* Set the number of ports on the system side to 1 */ 1650 /* Set the number of ports on the system side to 1 */
1694 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 0); 1651 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 0);
1695 if (max_speed == SPEED_10000) { 1652 if (max_speed == SPEED_10000) {
1696 DP(NETIF_MSG_LINK, 1653 DP(NETIF_MSG_LINK,
@@ -1722,8 +1679,7 @@ static void bnx2x_xmac_disable(struct link_params *params)
1722 1679
1723 if (REG_RD(bp, MISC_REG_RESET_REG_2) & 1680 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
1724 MISC_REGISTERS_RESET_REG_2_XMAC) { 1681 MISC_REGISTERS_RESET_REG_2_XMAC) {
1725 /* 1682 /* Send an indication to change the state in the NIG back to XON
1726 * Send an indication to change the state in the NIG back to XON
1727 * Clearing this bit enables the next set of this bit to get 1683 * Clearing this bit enables the next set of this bit to get
1728 * rising edge 1684 * rising edge
1729 */ 1685 */
@@ -1748,13 +1704,11 @@ static int bnx2x_xmac_enable(struct link_params *params,
1748 1704
1749 bnx2x_xmac_init(params, vars->line_speed); 1705 bnx2x_xmac_init(params, vars->line_speed);
1750 1706
1751 /* 1707 /* This register determines on which events the MAC will assert
1752 * This register determines on which events the MAC will assert
1753 * error on the i/f to the NIG along w/ EOP. 1708 * error on the i/f to the NIG along w/ EOP.
1754 */ 1709 */
1755 1710
1756 /* 1711 /* This register tells the NIG whether to send traffic to UMAC
1757 * This register tells the NIG whether to send traffic to UMAC
1758 * or XMAC 1712 * or XMAC
1759 */ 1713 */
1760 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0); 1714 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0);
@@ -1856,8 +1810,7 @@ static int bnx2x_emac_enable(struct link_params *params,
1856 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE); 1810 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
1857 val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS; 1811 val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
1858 1812
1859 /* 1813 /* Setting this bit causes MAC control frames (except for pause
1860 * Setting this bit causes MAC control frames (except for pause
1861 * frames) to be passed on for processing. This setting has no 1814 * frames) to be passed on for processing. This setting has no
1862 * affect on the operation of the pause frames. This bit effects 1815 * affect on the operation of the pause frames. This bit effects
1863 * all packets regardless of RX Parser packet sorting logic. 1816 * all packets regardless of RX Parser packet sorting logic.
@@ -1956,8 +1909,7 @@ static void bnx2x_update_pfc_bmac2(struct link_params *params,
1956 struct link_vars *vars, 1909 struct link_vars *vars,
1957 u8 is_lb) 1910 u8 is_lb)
1958{ 1911{
1959 /* 1912 /* Set rx control: Strip CRC and enable BigMAC to relay
1960 * Set rx control: Strip CRC and enable BigMAC to relay
1961 * control packets to the system as well 1913 * control packets to the system as well
1962 */ 1914 */
1963 u32 wb_data[2]; 1915 u32 wb_data[2];
@@ -2009,8 +1961,7 @@ static void bnx2x_update_pfc_bmac2(struct link_params *params,
2009 1961
2010 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2); 1962 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
2011 1963
2012 /* 1964 /* Set Time (based unit is 512 bit time) between automatic
2013 * Set Time (based unit is 512 bit time) between automatic
2014 * re-sending of PP packets amd enable automatic re-send of 1965 * re-sending of PP packets amd enable automatic re-send of
2015 * Per-Priroity Packet as long as pp_gen is asserted and 1966 * Per-Priroity Packet as long as pp_gen is asserted and
2016 * pp_disable is low. 1967 * pp_disable is low.
@@ -2079,7 +2030,7 @@ static int bnx2x_pfc_brb_get_config_params(
2079 config_val->default_class1.full_xon = 0; 2030 config_val->default_class1.full_xon = 0;
2080 2031
2081 if (CHIP_IS_E2(bp)) { 2032 if (CHIP_IS_E2(bp)) {
2082 /* class0 defaults */ 2033 /* Class0 defaults */
2083 config_val->default_class0.pause_xoff = 2034 config_val->default_class0.pause_xoff =
2084 DEFAULT0_E2_BRB_MAC_PAUSE_XOFF_THR; 2035 DEFAULT0_E2_BRB_MAC_PAUSE_XOFF_THR;
2085 config_val->default_class0.pause_xon = 2036 config_val->default_class0.pause_xon =
@@ -2088,7 +2039,7 @@ static int bnx2x_pfc_brb_get_config_params(
2088 DEFAULT0_E2_BRB_MAC_FULL_XOFF_THR; 2039 DEFAULT0_E2_BRB_MAC_FULL_XOFF_THR;
2089 config_val->default_class0.full_xon = 2040 config_val->default_class0.full_xon =
2090 DEFAULT0_E2_BRB_MAC_FULL_XON_THR; 2041 DEFAULT0_E2_BRB_MAC_FULL_XON_THR;
2091 /* pause able*/ 2042 /* Pause able*/
2092 config_val->pauseable_th.pause_xoff = 2043 config_val->pauseable_th.pause_xoff =
2093 PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE; 2044 PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2094 config_val->pauseable_th.pause_xon = 2045 config_val->pauseable_th.pause_xon =
@@ -2107,7 +2058,7 @@ static int bnx2x_pfc_brb_get_config_params(
2107 config_val->non_pauseable_th.full_xon = 2058 config_val->non_pauseable_th.full_xon =
2108 PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE; 2059 PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2109 } else if (CHIP_IS_E3A0(bp)) { 2060 } else if (CHIP_IS_E3A0(bp)) {
2110 /* class0 defaults */ 2061 /* Class0 defaults */
2111 config_val->default_class0.pause_xoff = 2062 config_val->default_class0.pause_xoff =
2112 DEFAULT0_E3A0_BRB_MAC_PAUSE_XOFF_THR; 2063 DEFAULT0_E3A0_BRB_MAC_PAUSE_XOFF_THR;
2113 config_val->default_class0.pause_xon = 2064 config_val->default_class0.pause_xon =
@@ -2116,7 +2067,7 @@ static int bnx2x_pfc_brb_get_config_params(
2116 DEFAULT0_E3A0_BRB_MAC_FULL_XOFF_THR; 2067 DEFAULT0_E3A0_BRB_MAC_FULL_XOFF_THR;
2117 config_val->default_class0.full_xon = 2068 config_val->default_class0.full_xon =
2118 DEFAULT0_E3A0_BRB_MAC_FULL_XON_THR; 2069 DEFAULT0_E3A0_BRB_MAC_FULL_XON_THR;
2119 /* pause able */ 2070 /* Pause able */
2120 config_val->pauseable_th.pause_xoff = 2071 config_val->pauseable_th.pause_xoff =
2121 PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE; 2072 PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE;
2122 config_val->pauseable_th.pause_xon = 2073 config_val->pauseable_th.pause_xon =
@@ -2135,7 +2086,7 @@ static int bnx2x_pfc_brb_get_config_params(
2135 config_val->non_pauseable_th.full_xon = 2086 config_val->non_pauseable_th.full_xon =
2136 PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE; 2087 PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE;
2137 } else if (CHIP_IS_E3B0(bp)) { 2088 } else if (CHIP_IS_E3B0(bp)) {
2138 /* class0 defaults */ 2089 /* Class0 defaults */
2139 config_val->default_class0.pause_xoff = 2090 config_val->default_class0.pause_xoff =
2140 DEFAULT0_E3B0_BRB_MAC_PAUSE_XOFF_THR; 2091 DEFAULT0_E3B0_BRB_MAC_PAUSE_XOFF_THR;
2141 config_val->default_class0.pause_xon = 2092 config_val->default_class0.pause_xon =
@@ -2298,27 +2249,23 @@ static int bnx2x_update_pfc_brb(struct link_params *params,
2298 reg_th_config = &config_val.non_pauseable_th; 2249 reg_th_config = &config_val.non_pauseable_th;
2299 } else 2250 } else
2300 reg_th_config = &config_val.default_class0; 2251 reg_th_config = &config_val.default_class0;
2301 /* 2252 /* The number of free blocks below which the pause signal to class 0
2302 * The number of free blocks below which the pause signal to class 0
2303 * of MAC #n is asserted. n=0,1 2253 * of MAC #n is asserted. n=0,1
2304 */ 2254 */
2305 REG_WR(bp, (port) ? BRB1_REG_PAUSE_0_XOFF_THRESHOLD_1 : 2255 REG_WR(bp, (port) ? BRB1_REG_PAUSE_0_XOFF_THRESHOLD_1 :
2306 BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 , 2256 BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 ,
2307 reg_th_config->pause_xoff); 2257 reg_th_config->pause_xoff);
2308 /* 2258 /* The number of free blocks above which the pause signal to class 0
2309 * The number of free blocks above which the pause signal to class 0
2310 * of MAC #n is de-asserted. n=0,1 2259 * of MAC #n is de-asserted. n=0,1
2311 */ 2260 */
2312 REG_WR(bp, (port) ? BRB1_REG_PAUSE_0_XON_THRESHOLD_1 : 2261 REG_WR(bp, (port) ? BRB1_REG_PAUSE_0_XON_THRESHOLD_1 :
2313 BRB1_REG_PAUSE_0_XON_THRESHOLD_0 , reg_th_config->pause_xon); 2262 BRB1_REG_PAUSE_0_XON_THRESHOLD_0 , reg_th_config->pause_xon);
2314 /* 2263 /* The number of free blocks below which the full signal to class 0
2315 * The number of free blocks below which the full signal to class 0
2316 * of MAC #n is asserted. n=0,1 2264 * of MAC #n is asserted. n=0,1
2317 */ 2265 */
2318 REG_WR(bp, (port) ? BRB1_REG_FULL_0_XOFF_THRESHOLD_1 : 2266 REG_WR(bp, (port) ? BRB1_REG_FULL_0_XOFF_THRESHOLD_1 :
2319 BRB1_REG_FULL_0_XOFF_THRESHOLD_0 , reg_th_config->full_xoff); 2267 BRB1_REG_FULL_0_XOFF_THRESHOLD_0 , reg_th_config->full_xoff);
2320 /* 2268 /* The number of free blocks above which the full signal to class 0
2321 * The number of free blocks above which the full signal to class 0
2322 * of MAC #n is de-asserted. n=0,1 2269 * of MAC #n is de-asserted. n=0,1
2323 */ 2270 */
2324 REG_WR(bp, (port) ? BRB1_REG_FULL_0_XON_THRESHOLD_1 : 2271 REG_WR(bp, (port) ? BRB1_REG_FULL_0_XON_THRESHOLD_1 :
@@ -2332,30 +2279,26 @@ static int bnx2x_update_pfc_brb(struct link_params *params,
2332 reg_th_config = &config_val.non_pauseable_th; 2279 reg_th_config = &config_val.non_pauseable_th;
2333 } else 2280 } else
2334 reg_th_config = &config_val.default_class1; 2281 reg_th_config = &config_val.default_class1;
2335 /* 2282 /* The number of free blocks below which the pause signal to
2336 * The number of free blocks below which the pause signal to
2337 * class 1 of MAC #n is asserted. n=0,1 2283 * class 1 of MAC #n is asserted. n=0,1
2338 */ 2284 */
2339 REG_WR(bp, (port) ? BRB1_REG_PAUSE_1_XOFF_THRESHOLD_1 : 2285 REG_WR(bp, (port) ? BRB1_REG_PAUSE_1_XOFF_THRESHOLD_1 :
2340 BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0, 2286 BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0,
2341 reg_th_config->pause_xoff); 2287 reg_th_config->pause_xoff);
2342 2288
2343 /* 2289 /* The number of free blocks above which the pause signal to
2344 * The number of free blocks above which the pause signal to
2345 * class 1 of MAC #n is de-asserted. n=0,1 2290 * class 1 of MAC #n is de-asserted. n=0,1
2346 */ 2291 */
2347 REG_WR(bp, (port) ? BRB1_REG_PAUSE_1_XON_THRESHOLD_1 : 2292 REG_WR(bp, (port) ? BRB1_REG_PAUSE_1_XON_THRESHOLD_1 :
2348 BRB1_REG_PAUSE_1_XON_THRESHOLD_0, 2293 BRB1_REG_PAUSE_1_XON_THRESHOLD_0,
2349 reg_th_config->pause_xon); 2294 reg_th_config->pause_xon);
2350 /* 2295 /* The number of free blocks below which the full signal to
2351 * The number of free blocks below which the full signal to
2352 * class 1 of MAC #n is asserted. n=0,1 2296 * class 1 of MAC #n is asserted. n=0,1
2353 */ 2297 */
2354 REG_WR(bp, (port) ? BRB1_REG_FULL_1_XOFF_THRESHOLD_1 : 2298 REG_WR(bp, (port) ? BRB1_REG_FULL_1_XOFF_THRESHOLD_1 :
2355 BRB1_REG_FULL_1_XOFF_THRESHOLD_0, 2299 BRB1_REG_FULL_1_XOFF_THRESHOLD_0,
2356 reg_th_config->full_xoff); 2300 reg_th_config->full_xoff);
2357 /* 2301 /* The number of free blocks above which the full signal to
2358 * The number of free blocks above which the full signal to
2359 * class 1 of MAC #n is de-asserted. n=0,1 2302 * class 1 of MAC #n is de-asserted. n=0,1
2360 */ 2303 */
2361 REG_WR(bp, (port) ? BRB1_REG_FULL_1_XON_THRESHOLD_1 : 2304 REG_WR(bp, (port) ? BRB1_REG_FULL_1_XON_THRESHOLD_1 :
@@ -2372,49 +2315,41 @@ static int bnx2x_update_pfc_brb(struct link_params *params,
2372 REG_WR(bp, BRB1_REG_PER_CLASS_GUARANTY_MODE, 2315 REG_WR(bp, BRB1_REG_PER_CLASS_GUARANTY_MODE,
2373 e3b0_val.per_class_guaranty_mode); 2316 e3b0_val.per_class_guaranty_mode);
2374 2317
2375 /* 2318 /* The hysteresis on the guarantied buffer space for the Lb
2376 * The hysteresis on the guarantied buffer space for the Lb
2377 * port before signaling XON. 2319 * port before signaling XON.
2378 */ 2320 */
2379 REG_WR(bp, BRB1_REG_LB_GUARANTIED_HYST, 2321 REG_WR(bp, BRB1_REG_LB_GUARANTIED_HYST,
2380 e3b0_val.lb_guarantied_hyst); 2322 e3b0_val.lb_guarantied_hyst);
2381 2323
2382 /* 2324 /* The number of free blocks below which the full signal to the
2383 * The number of free blocks below which the full signal to the
2384 * LB port is asserted. 2325 * LB port is asserted.
2385 */ 2326 */
2386 REG_WR(bp, BRB1_REG_FULL_LB_XOFF_THRESHOLD, 2327 REG_WR(bp, BRB1_REG_FULL_LB_XOFF_THRESHOLD,
2387 e3b0_val.full_lb_xoff_th); 2328 e3b0_val.full_lb_xoff_th);
2388 /* 2329 /* The number of free blocks above which the full signal to the
2389 * The number of free blocks above which the full signal to the
2390 * LB port is de-asserted. 2330 * LB port is de-asserted.
2391 */ 2331 */
2392 REG_WR(bp, BRB1_REG_FULL_LB_XON_THRESHOLD, 2332 REG_WR(bp, BRB1_REG_FULL_LB_XON_THRESHOLD,
2393 e3b0_val.full_lb_xon_threshold); 2333 e3b0_val.full_lb_xon_threshold);
2394 /* 2334 /* The number of blocks guarantied for the MAC #n port. n=0,1
2395 * The number of blocks guarantied for the MAC #n port. n=0,1
2396 */ 2335 */
2397 2336
2398 /* The number of blocks guarantied for the LB port.*/ 2337 /* The number of blocks guarantied for the LB port. */
2399 REG_WR(bp, BRB1_REG_LB_GUARANTIED, 2338 REG_WR(bp, BRB1_REG_LB_GUARANTIED,
2400 e3b0_val.lb_guarantied); 2339 e3b0_val.lb_guarantied);
2401 2340
2402 /* 2341 /* The number of blocks guarantied for the MAC #n port. */
2403 * The number of blocks guarantied for the MAC #n port.
2404 */
2405 REG_WR(bp, BRB1_REG_MAC_GUARANTIED_0, 2342 REG_WR(bp, BRB1_REG_MAC_GUARANTIED_0,
2406 2 * e3b0_val.mac_0_class_t_guarantied); 2343 2 * e3b0_val.mac_0_class_t_guarantied);
2407 REG_WR(bp, BRB1_REG_MAC_GUARANTIED_1, 2344 REG_WR(bp, BRB1_REG_MAC_GUARANTIED_1,
2408 2 * e3b0_val.mac_1_class_t_guarantied); 2345 2 * e3b0_val.mac_1_class_t_guarantied);
2409 /* 2346 /* The number of blocks guarantied for class #t in MAC0. t=0,1
2410 * The number of blocks guarantied for class #t in MAC0. t=0,1
2411 */ 2347 */
2412 REG_WR(bp, BRB1_REG_MAC_0_CLASS_0_GUARANTIED, 2348 REG_WR(bp, BRB1_REG_MAC_0_CLASS_0_GUARANTIED,
2413 e3b0_val.mac_0_class_t_guarantied); 2349 e3b0_val.mac_0_class_t_guarantied);
2414 REG_WR(bp, BRB1_REG_MAC_0_CLASS_1_GUARANTIED, 2350 REG_WR(bp, BRB1_REG_MAC_0_CLASS_1_GUARANTIED,
2415 e3b0_val.mac_0_class_t_guarantied); 2351 e3b0_val.mac_0_class_t_guarantied);
2416 /* 2352 /* The hysteresis on the guarantied buffer space for class in
2417 * The hysteresis on the guarantied buffer space for class in
2418 * MAC0. t=0,1 2353 * MAC0. t=0,1
2419 */ 2354 */
2420 REG_WR(bp, BRB1_REG_MAC_0_CLASS_0_GUARANTIED_HYST, 2355 REG_WR(bp, BRB1_REG_MAC_0_CLASS_0_GUARANTIED_HYST,
@@ -2422,15 +2357,13 @@ static int bnx2x_update_pfc_brb(struct link_params *params,
2422 REG_WR(bp, BRB1_REG_MAC_0_CLASS_1_GUARANTIED_HYST, 2357 REG_WR(bp, BRB1_REG_MAC_0_CLASS_1_GUARANTIED_HYST,
2423 e3b0_val.mac_0_class_t_guarantied_hyst); 2358 e3b0_val.mac_0_class_t_guarantied_hyst);
2424 2359
2425 /* 2360 /* The number of blocks guarantied for class #t in MAC1.t=0,1
2426 * The number of blocks guarantied for class #t in MAC1.t=0,1
2427 */ 2361 */
2428 REG_WR(bp, BRB1_REG_MAC_1_CLASS_0_GUARANTIED, 2362 REG_WR(bp, BRB1_REG_MAC_1_CLASS_0_GUARANTIED,
2429 e3b0_val.mac_1_class_t_guarantied); 2363 e3b0_val.mac_1_class_t_guarantied);
2430 REG_WR(bp, BRB1_REG_MAC_1_CLASS_1_GUARANTIED, 2364 REG_WR(bp, BRB1_REG_MAC_1_CLASS_1_GUARANTIED,
2431 e3b0_val.mac_1_class_t_guarantied); 2365 e3b0_val.mac_1_class_t_guarantied);
2432 /* 2366 /* The hysteresis on the guarantied buffer space for class #t
2433 * The hysteresis on the guarantied buffer space for class #t
2434 * in MAC1. t=0,1 2367 * in MAC1. t=0,1
2435 */ 2368 */
2436 REG_WR(bp, BRB1_REG_MAC_1_CLASS_0_GUARANTIED_HYST, 2369 REG_WR(bp, BRB1_REG_MAC_1_CLASS_0_GUARANTIED_HYST,
@@ -2513,15 +2446,13 @@ static void bnx2x_update_pfc_nig(struct link_params *params,
2513 FEATURE_CONFIG_PFC_ENABLED; 2446 FEATURE_CONFIG_PFC_ENABLED;
2514 DP(NETIF_MSG_LINK, "updating pfc nig parameters\n"); 2447 DP(NETIF_MSG_LINK, "updating pfc nig parameters\n");
2515 2448
2516 /* 2449 /* When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
2517 * When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
2518 * MAC control frames (that are not pause packets) 2450 * MAC control frames (that are not pause packets)
2519 * will be forwarded to the XCM. 2451 * will be forwarded to the XCM.
2520 */ 2452 */
2521 xcm_mask = REG_RD(bp, port ? NIG_REG_LLH1_XCM_MASK : 2453 xcm_mask = REG_RD(bp, port ? NIG_REG_LLH1_XCM_MASK :
2522 NIG_REG_LLH0_XCM_MASK); 2454 NIG_REG_LLH0_XCM_MASK);
2523 /* 2455 /* NIG params will override non PFC params, since it's possible to
2524 * nig params will override non PFC params, since it's possible to
2525 * do transition from PFC to SAFC 2456 * do transition from PFC to SAFC
2526 */ 2457 */
2527 if (set_pfc) { 2458 if (set_pfc) {
@@ -2541,7 +2472,7 @@ static void bnx2x_update_pfc_nig(struct link_params *params,
2541 llfc_out_en = nig_params->llfc_out_en; 2472 llfc_out_en = nig_params->llfc_out_en;
2542 llfc_enable = nig_params->llfc_enable; 2473 llfc_enable = nig_params->llfc_enable;
2543 pause_enable = nig_params->pause_enable; 2474 pause_enable = nig_params->pause_enable;
2544 } else /*defaul non PFC mode - PAUSE */ 2475 } else /* Default non PFC mode - PAUSE */
2545 pause_enable = 1; 2476 pause_enable = 1;
2546 2477
2547 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN : 2478 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
@@ -2601,8 +2532,7 @@ int bnx2x_update_pfc(struct link_params *params,
2601 struct link_vars *vars, 2532 struct link_vars *vars,
2602 struct bnx2x_nig_brb_pfc_port_params *pfc_params) 2533 struct bnx2x_nig_brb_pfc_port_params *pfc_params)
2603{ 2534{
2604 /* 2535 /* The PFC and pause are orthogonal to one another, meaning when
2605 * The PFC and pause are orthogonal to one another, meaning when
2606 * PFC is enabled, the pause are disabled, and when PFC is 2536 * PFC is enabled, the pause are disabled, and when PFC is
2607 * disabled, pause are set according to the pause result. 2537 * disabled, pause are set according to the pause result.
2608 */ 2538 */
@@ -3141,7 +3071,6 @@ static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
3141 EMAC_MDIO_STATUS_10MB); 3071 EMAC_MDIO_STATUS_10MB);
3142 3072
3143 /* address */ 3073 /* address */
3144
3145 tmp = ((phy->addr << 21) | (devad << 16) | reg | 3074 tmp = ((phy->addr << 21) | (devad << 16) | reg |
3146 EMAC_MDIO_COMM_COMMAND_ADDRESS | 3075 EMAC_MDIO_COMM_COMMAND_ADDRESS |
3147 EMAC_MDIO_COMM_START_BUSY); 3076 EMAC_MDIO_COMM_START_BUSY);
@@ -3330,8 +3259,7 @@ int bnx2x_phy_read(struct link_params *params, u8 phy_addr,
3330 u8 devad, u16 reg, u16 *ret_val) 3259 u8 devad, u16 reg, u16 *ret_val)
3331{ 3260{
3332 u8 phy_index; 3261 u8 phy_index;
3333 /* 3262 /* Probe for the phy according to the given phy_addr, and execute
3334 * Probe for the phy according to the given phy_addr, and execute
3335 * the read request on it 3263 * the read request on it
3336 */ 3264 */
3337 for (phy_index = 0; phy_index < params->num_phys; phy_index++) { 3265 for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
@@ -3348,8 +3276,7 @@ int bnx2x_phy_write(struct link_params *params, u8 phy_addr,
3348 u8 devad, u16 reg, u16 val) 3276 u8 devad, u16 reg, u16 val)
3349{ 3277{
3350 u8 phy_index; 3278 u8 phy_index;
3351 /* 3279 /* Probe for the phy according to the given phy_addr, and execute
3352 * Probe for the phy according to the given phy_addr, and execute
3353 * the write request on it 3280 * the write request on it
3354 */ 3281 */
3355 for (phy_index = 0; phy_index < params->num_phys; phy_index++) { 3282 for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
@@ -3375,7 +3302,7 @@ static u8 bnx2x_get_warpcore_lane(struct bnx2x_phy *phy,
3375 if (bnx2x_is_4_port_mode(bp)) { 3302 if (bnx2x_is_4_port_mode(bp)) {
3376 u32 port_swap, port_swap_ovr; 3303 u32 port_swap, port_swap_ovr;
3377 3304
3378 /*figure out path swap value */ 3305 /* Figure out path swap value */
3379 path_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR); 3306 path_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR);
3380 if (path_swap_ovr & 0x1) 3307 if (path_swap_ovr & 0x1)
3381 path_swap = (path_swap_ovr & 0x2); 3308 path_swap = (path_swap_ovr & 0x2);
@@ -3385,7 +3312,7 @@ static u8 bnx2x_get_warpcore_lane(struct bnx2x_phy *phy,
3385 if (path_swap) 3312 if (path_swap)
3386 path = path ^ 1; 3313 path = path ^ 1;
3387 3314
3388 /*figure out port swap value */ 3315 /* Figure out port swap value */
3389 port_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR); 3316 port_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR);
3390 if (port_swap_ovr & 0x1) 3317 if (port_swap_ovr & 0x1)
3391 port_swap = (port_swap_ovr & 0x2); 3318 port_swap = (port_swap_ovr & 0x2);
@@ -3398,7 +3325,7 @@ static u8 bnx2x_get_warpcore_lane(struct bnx2x_phy *phy,
3398 lane = (port<<1) + path; 3325 lane = (port<<1) + path;
3399 } else { /* two port mode - no port swap */ 3326 } else { /* two port mode - no port swap */
3400 3327
3401 /*figure out path swap value */ 3328 /* Figure out path swap value */
3402 path_swap_ovr = 3329 path_swap_ovr =
3403 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP_OVWR); 3330 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);
3404 if (path_swap_ovr & 0x1) { 3331 if (path_swap_ovr & 0x1) {
@@ -3430,8 +3357,7 @@ static void bnx2x_set_aer_mmd(struct link_params *params,
3430 3357
3431 if (USES_WARPCORE(bp)) { 3358 if (USES_WARPCORE(bp)) {
3432 aer_val = bnx2x_get_warpcore_lane(phy, params); 3359 aer_val = bnx2x_get_warpcore_lane(phy, params);
3433 /* 3360 /* In Dual-lane mode, two lanes are joined together,
3434 * In Dual-lane mode, two lanes are joined together,
3435 * so in order to configure them, the AER broadcast method is 3361 * so in order to configure them, the AER broadcast method is
3436 * used here. 3362 * used here.
3437 * 0x200 is the broadcast address for lanes 0,1 3363 * 0x200 is the broadcast address for lanes 0,1
@@ -3511,8 +3437,7 @@ static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy,
3511{ 3437{
3512 struct bnx2x *bp = params->bp; 3438 struct bnx2x *bp = params->bp;
3513 *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX; 3439 *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
3514 /** 3440 /* Resolve pause mode and advertisement Please refer to Table
3515 * resolve pause mode and advertisement Please refer to Table
3516 * 28B-3 of the 802.3ab-1999 spec 3441 * 28B-3 of the 802.3ab-1999 spec
3517 */ 3442 */
3518 3443
@@ -3635,6 +3560,7 @@ static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result)
3635 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE; 3560 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
3636 if (pause_result & (1<<1)) 3561 if (pause_result & (1<<1))
3637 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE; 3562 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
3563
3638} 3564}
3639 3565
3640static void bnx2x_ext_phy_update_adv_fc(struct bnx2x_phy *phy, 3566static void bnx2x_ext_phy_update_adv_fc(struct bnx2x_phy *phy,
@@ -3664,6 +3590,7 @@ static void bnx2x_ext_phy_update_adv_fc(struct bnx2x_phy *phy,
3664 bnx2x_pause_resolve(vars, pause_result); 3590 bnx2x_pause_resolve(vars, pause_result);
3665 3591
3666} 3592}
3593
3667static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy, 3594static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy,
3668 struct link_params *params, 3595 struct link_params *params,
3669 struct link_vars *vars) 3596 struct link_vars *vars)
@@ -3769,9 +3696,7 @@ static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy,
3769 3696
3770 /* Advertise pause */ 3697 /* Advertise pause */
3771 bnx2x_ext_phy_set_pause(params, phy, vars); 3698 bnx2x_ext_phy_set_pause(params, phy, vars);
3772 3699 /* Set KR Autoneg Work-Around flag for Warpcore version older than D108
3773 /*
3774 * Set KR Autoneg Work-Around flag for Warpcore version older than D108
3775 */ 3700 */
3776 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3701 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3777 MDIO_WC_REG_UC_INFO_B1_VERSION, &val16); 3702 MDIO_WC_REG_UC_INFO_B1_VERSION, &val16);
@@ -3779,7 +3704,6 @@ static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy,
3779 DP(NETIF_MSG_LINK, "Enable AN KR work-around\n"); 3704 DP(NETIF_MSG_LINK, "Enable AN KR work-around\n");
3780 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY; 3705 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
3781 } 3706 }
3782
3783 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3707 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3784 MDIO_WC_REG_DIGITAL5_MISC7, &val16); 3708 MDIO_WC_REG_DIGITAL5_MISC7, &val16);
3785 3709
@@ -3853,7 +3777,7 @@ static void bnx2x_warpcore_set_10G_KR(struct bnx2x_phy *phy,
3853 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 3777 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3854 MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB); 3778 MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB);
3855 3779
3856 /*Enable encoded forced speed */ 3780 /* Enable encoded forced speed */
3857 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3781 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3858 MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30); 3782 MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30);
3859 3783
@@ -4215,8 +4139,7 @@ static int bnx2x_get_mod_abs_int_cfg(struct bnx2x *bp,
4215 PORT_HW_CFG_E3_MOD_ABS_MASK) >> 4139 PORT_HW_CFG_E3_MOD_ABS_MASK) >>
4216 PORT_HW_CFG_E3_MOD_ABS_SHIFT; 4140 PORT_HW_CFG_E3_MOD_ABS_SHIFT;
4217 4141
4218 /* 4142 /* Should not happen. This function called upon interrupt
4219 * Should not happen. This function called upon interrupt
4220 * triggered by GPIO ( since EPIO can only generate interrupts 4143 * triggered by GPIO ( since EPIO can only generate interrupts
4221 * to MCP). 4144 * to MCP).
4222 * So if this function was called and none of the GPIOs was set, 4145 * So if this function was called and none of the GPIOs was set,
@@ -4316,7 +4239,7 @@ static void bnx2x_warpcore_config_runtime(struct bnx2x_phy *phy,
4316 "link up, rx_tx_asic_rst 0x%x\n", 4239 "link up, rx_tx_asic_rst 0x%x\n",
4317 vars->rx_tx_asic_rst); 4240 vars->rx_tx_asic_rst);
4318 } else { 4241 } else {
4319 /*reset the lane to see if link comes up.*/ 4242 /* Reset the lane to see if link comes up.*/
4320 bnx2x_warpcore_reset_lane(bp, phy, 1); 4243 bnx2x_warpcore_reset_lane(bp, phy, 1);
4321 bnx2x_warpcore_reset_lane(bp, phy, 0); 4244 bnx2x_warpcore_reset_lane(bp, phy, 0);
4322 4245
@@ -4337,7 +4260,6 @@ static void bnx2x_warpcore_config_runtime(struct bnx2x_phy *phy,
4337 } /*params->rx_tx_asic_rst*/ 4260 } /*params->rx_tx_asic_rst*/
4338 4261
4339} 4262}
4340
4341static void bnx2x_warpcore_config_init(struct bnx2x_phy *phy, 4263static void bnx2x_warpcore_config_init(struct bnx2x_phy *phy,
4342 struct link_params *params, 4264 struct link_params *params,
4343 struct link_vars *vars) 4265 struct link_vars *vars)
@@ -4495,7 +4417,7 @@ static void bnx2x_warpcore_link_reset(struct bnx2x_phy *phy,
4495 /* Update those 1-copy registers */ 4417 /* Update those 1-copy registers */
4496 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, 4418 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4497 MDIO_AER_BLOCK_AER_REG, 0); 4419 MDIO_AER_BLOCK_AER_REG, 0);
4498 /* Enable 1G MDIO (1-copy) */ 4420 /* Enable 1G MDIO (1-copy) */
4499 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 4421 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4500 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, 4422 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4501 &val16); 4423 &val16);
@@ -4574,43 +4496,43 @@ void bnx2x_sync_link(struct link_params *params,
4574 vars->duplex = DUPLEX_FULL; 4496 vars->duplex = DUPLEX_FULL;
4575 switch (vars->link_status & 4497 switch (vars->link_status &
4576 LINK_STATUS_SPEED_AND_DUPLEX_MASK) { 4498 LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
4577 case LINK_10THD: 4499 case LINK_10THD:
4578 vars->duplex = DUPLEX_HALF; 4500 vars->duplex = DUPLEX_HALF;
4579 /* fall thru */ 4501 /* Fall thru */
4580 case LINK_10TFD: 4502 case LINK_10TFD:
4581 vars->line_speed = SPEED_10; 4503 vars->line_speed = SPEED_10;
4582 break; 4504 break;
4583 4505
4584 case LINK_100TXHD: 4506 case LINK_100TXHD:
4585 vars->duplex = DUPLEX_HALF; 4507 vars->duplex = DUPLEX_HALF;
4586 /* fall thru */ 4508 /* Fall thru */
4587 case LINK_100T4: 4509 case LINK_100T4:
4588 case LINK_100TXFD: 4510 case LINK_100TXFD:
4589 vars->line_speed = SPEED_100; 4511 vars->line_speed = SPEED_100;
4590 break; 4512 break;
4591 4513
4592 case LINK_1000THD: 4514 case LINK_1000THD:
4593 vars->duplex = DUPLEX_HALF; 4515 vars->duplex = DUPLEX_HALF;
4594 /* fall thru */ 4516 /* Fall thru */
4595 case LINK_1000TFD: 4517 case LINK_1000TFD:
4596 vars->line_speed = SPEED_1000; 4518 vars->line_speed = SPEED_1000;
4597 break; 4519 break;
4598 4520
4599 case LINK_2500THD: 4521 case LINK_2500THD:
4600 vars->duplex = DUPLEX_HALF; 4522 vars->duplex = DUPLEX_HALF;
4601 /* fall thru */ 4523 /* Fall thru */
4602 case LINK_2500TFD: 4524 case LINK_2500TFD:
4603 vars->line_speed = SPEED_2500; 4525 vars->line_speed = SPEED_2500;
4604 break; 4526 break;
4605 4527
4606 case LINK_10GTFD: 4528 case LINK_10GTFD:
4607 vars->line_speed = SPEED_10000; 4529 vars->line_speed = SPEED_10000;
4608 break; 4530 break;
4609 case LINK_20GTFD: 4531 case LINK_20GTFD:
4610 vars->line_speed = SPEED_20000; 4532 vars->line_speed = SPEED_20000;
4611 break; 4533 break;
4612 default: 4534 default:
4613 break; 4535 break;
4614 } 4536 }
4615 vars->flow_ctrl = 0; 4537 vars->flow_ctrl = 0;
4616 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED) 4538 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
@@ -4785,9 +4707,8 @@ static void bnx2x_set_swap_lanes(struct link_params *params,
4785 struct bnx2x_phy *phy) 4707 struct bnx2x_phy *phy)
4786{ 4708{
4787 struct bnx2x *bp = params->bp; 4709 struct bnx2x *bp = params->bp;
4788 /* 4710 /* Each two bits represents a lane number:
4789 * Each two bits represents a lane number: 4711 * No swap is 0123 => 0x1b no need to enable the swap
4790 * No swap is 0123 => 0x1b no need to enable the swap
4791 */ 4712 */
4792 u16 rx_lane_swap, tx_lane_swap; 4713 u16 rx_lane_swap, tx_lane_swap;
4793 4714
@@ -5001,8 +4922,7 @@ static void bnx2x_program_serdes(struct bnx2x_phy *phy,
5001 MDIO_REG_BANK_COMBO_IEEE0, 4922 MDIO_REG_BANK_COMBO_IEEE0,
5002 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val); 4923 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
5003 4924
5004 /* 4925 /* Program speed
5005 * program speed
5006 * - needed only if the speed is greater than 1G (2.5G or 10G) 4926 * - needed only if the speed is greater than 1G (2.5G or 10G)
5007 */ 4927 */
5008 CL22_RD_OVER_CL45(bp, phy, 4928 CL22_RD_OVER_CL45(bp, phy,
@@ -5037,8 +4957,6 @@ static void bnx2x_set_brcm_cl37_advertisement(struct bnx2x_phy *phy,
5037 struct bnx2x *bp = params->bp; 4957 struct bnx2x *bp = params->bp;
5038 u16 val = 0; 4958 u16 val = 0;
5039 4959
5040 /* configure the 48 bits for BAM AN */
5041
5042 /* set extended capabilities */ 4960 /* set extended capabilities */
5043 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) 4961 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
5044 val |= MDIO_OVER_1G_UP1_2_5G; 4962 val |= MDIO_OVER_1G_UP1_2_5G;
@@ -5184,11 +5102,8 @@ static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy,
5184 } 5102 }
5185} 5103}
5186 5104
5187 5105/* Link management
5188/*
5189 * link management
5190 */ 5106 */
5191
5192static int bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy, 5107static int bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy,
5193 struct link_params *params) 5108 struct link_params *params)
5194{ 5109{
@@ -5333,8 +5248,7 @@ static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy,
5333 "ustat_val(0x8371) = 0x%x\n", ustat_val); 5248 "ustat_val(0x8371) = 0x%x\n", ustat_val);
5334 return; 5249 return;
5335 } 5250 }
5336 /* 5251 /* Step 3: Check CL37 Message Pages received to indicate LP
5337 * Step 3: Check CL37 Message Pages received to indicate LP
5338 * supports only CL37 5252 * supports only CL37
5339 */ 5253 */
5340 CL22_RD_OVER_CL45(bp, phy, 5254 CL22_RD_OVER_CL45(bp, phy,
@@ -5351,8 +5265,7 @@ static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy,
5351 cl37_fsm_received); 5265 cl37_fsm_received);
5352 return; 5266 return;
5353 } 5267 }
5354 /* 5268 /* The combined cl37/cl73 fsm state information indicating that
5355 * The combined cl37/cl73 fsm state information indicating that
5356 * we are connected to a device which does not support cl73, but 5269 * we are connected to a device which does not support cl73, but
5357 * does support cl37 BAM. In this case we disable cl73 and 5270 * does support cl37 BAM. In this case we disable cl73 and
5358 * restart cl37 auto-neg 5271 * restart cl37 auto-neg
@@ -5923,8 +5836,7 @@ static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port,
5923{ 5836{
5924 u32 latch_status = 0; 5837 u32 latch_status = 0;
5925 5838
5926 /* 5839 /* Disable the MI INT ( external phy int ) by writing 1 to the
5927 * Disable the MI INT ( external phy int ) by writing 1 to the
5928 * status register. Link down indication is high-active-signal, 5840 * status register. Link down indication is high-active-signal,
5929 * so in this case we need to write the status to clear the XOR 5841 * so in this case we need to write the status to clear the XOR
5930 */ 5842 */
@@ -5959,8 +5871,7 @@ static void bnx2x_link_int_ack(struct link_params *params,
5959 struct bnx2x *bp = params->bp; 5871 struct bnx2x *bp = params->bp;
5960 u8 port = params->port; 5872 u8 port = params->port;
5961 u32 mask; 5873 u32 mask;
5962 /* 5874 /* First reset all status we assume only one line will be
5963 * First reset all status we assume only one line will be
5964 * change at a time 5875 * change at a time
5965 */ 5876 */
5966 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, 5877 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
@@ -5974,8 +5885,7 @@ static void bnx2x_link_int_ack(struct link_params *params,
5974 if (is_10g_plus) 5885 if (is_10g_plus)
5975 mask = NIG_STATUS_XGXS0_LINK10G; 5886 mask = NIG_STATUS_XGXS0_LINK10G;
5976 else if (params->switch_cfg == SWITCH_CFG_10G) { 5887 else if (params->switch_cfg == SWITCH_CFG_10G) {
5977 /* 5888 /* Disable the link interrupt by writing 1 to
5978 * Disable the link interrupt by writing 1 to
5979 * the relevant lane in the status register 5889 * the relevant lane in the status register
5980 */ 5890 */
5981 u32 ser_lane = 5891 u32 ser_lane =
@@ -6175,8 +6085,7 @@ int bnx2x_set_led(struct link_params *params,
6175 break; 6085 break;
6176 6086
6177 case LED_MODE_OPER: 6087 case LED_MODE_OPER:
6178 /* 6088 /* For all other phys, OPER mode is same as ON, so in case
6179 * For all other phys, OPER mode is same as ON, so in case
6180 * link is down, do nothing 6089 * link is down, do nothing
6181 */ 6090 */
6182 if (!vars->link_up) 6091 if (!vars->link_up)
@@ -6187,9 +6096,7 @@ int bnx2x_set_led(struct link_params *params,
6187 (params->phy[EXT_PHY1].type == 6096 (params->phy[EXT_PHY1].type ==
6188 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) && 6097 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) &&
6189 CHIP_IS_E2(bp) && params->num_phys == 2) { 6098 CHIP_IS_E2(bp) && params->num_phys == 2) {
6190 /* 6099 /* This is a work-around for E2+8727 Configurations */
6191 * This is a work-around for E2+8727 Configurations
6192 */
6193 if (mode == LED_MODE_ON || 6100 if (mode == LED_MODE_ON ||
6194 speed == SPEED_10000){ 6101 speed == SPEED_10000){
6195 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); 6102 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
@@ -6198,8 +6105,7 @@ int bnx2x_set_led(struct link_params *params,
6198 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); 6105 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6199 EMAC_WR(bp, EMAC_REG_EMAC_LED, 6106 EMAC_WR(bp, EMAC_REG_EMAC_LED,
6200 (tmp | EMAC_LED_OVERRIDE)); 6107 (tmp | EMAC_LED_OVERRIDE));
6201 /* 6108 /* Return here without enabling traffic
6202 * return here without enabling traffic
6203 * LED blink and setting rate in ON mode. 6109 * LED blink and setting rate in ON mode.
6204 * In oper mode, enabling LED blink 6110 * In oper mode, enabling LED blink
6205 * and setting rate is needed. 6111 * and setting rate is needed.
@@ -6208,8 +6114,7 @@ int bnx2x_set_led(struct link_params *params,
6208 return rc; 6114 return rc;
6209 } 6115 }
6210 } else if (SINGLE_MEDIA_DIRECT(params)) { 6116 } else if (SINGLE_MEDIA_DIRECT(params)) {
6211 /* 6117 /* This is a work-around for HW issue found when link
6212 * This is a work-around for HW issue found when link
6213 * is up in CL73 6118 * is up in CL73
6214 */ 6119 */
6215 if ((!CHIP_IS_E3(bp)) || 6120 if ((!CHIP_IS_E3(bp)) ||
@@ -6257,10 +6162,7 @@ int bnx2x_set_led(struct link_params *params,
6257 (speed == SPEED_1000) || 6162 (speed == SPEED_1000) ||
6258 (speed == SPEED_100) || 6163 (speed == SPEED_100) ||
6259 (speed == SPEED_10))) { 6164 (speed == SPEED_10))) {
6260 /* 6165 /* For speeds less than 10G LED scheme is different */
6261 * On Everest 1 Ax chip versions for speeds less than
6262 * 10G LED scheme is different
6263 */
6264 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 6166 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
6265 + port*4, 1); 6167 + port*4, 1);
6266 REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 + 6168 REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
@@ -6280,8 +6182,7 @@ int bnx2x_set_led(struct link_params *params,
6280 6182
6281} 6183}
6282 6184
6283/* 6185/* This function comes to reflect the actual link state read DIRECTLY from the
6284 * This function comes to reflect the actual link state read DIRECTLY from the
6285 * HW 6186 * HW
6286 */ 6187 */
6287int bnx2x_test_link(struct link_params *params, struct link_vars *vars, 6188int bnx2x_test_link(struct link_params *params, struct link_vars *vars,
@@ -6369,16 +6270,14 @@ static int bnx2x_link_initialize(struct link_params *params,
6369 int rc = 0; 6270 int rc = 0;
6370 u8 phy_index, non_ext_phy; 6271 u8 phy_index, non_ext_phy;
6371 struct bnx2x *bp = params->bp; 6272 struct bnx2x *bp = params->bp;
6372 /* 6273 /* In case of external phy existence, the line speed would be the
6373 * In case of external phy existence, the line speed would be the
6374 * line speed linked up by the external phy. In case it is direct 6274 * line speed linked up by the external phy. In case it is direct
6375 * only, then the line_speed during initialization will be 6275 * only, then the line_speed during initialization will be
6376 * equal to the req_line_speed 6276 * equal to the req_line_speed
6377 */ 6277 */
6378 vars->line_speed = params->phy[INT_PHY].req_line_speed; 6278 vars->line_speed = params->phy[INT_PHY].req_line_speed;
6379 6279
6380 /* 6280 /* Initialize the internal phy in case this is a direct board
6381 * Initialize the internal phy in case this is a direct board
6382 * (no external phys), or this board has external phy which requires 6281 * (no external phys), or this board has external phy which requires
6383 * to first. 6282 * to first.
6384 */ 6283 */
@@ -6410,8 +6309,7 @@ static int bnx2x_link_initialize(struct link_params *params,
6410 } else { 6309 } else {
6411 for (phy_index = EXT_PHY1; phy_index < params->num_phys; 6310 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6412 phy_index++) { 6311 phy_index++) {
6413 /* 6312 /* No need to initialize second phy in case of first
6414 * No need to initialize second phy in case of first
6415 * phy only selection. In case of second phy, we do 6313 * phy only selection. In case of second phy, we do
6416 * need to initialize the first phy, since they are 6314 * need to initialize the first phy, since they are
6417 * connected. 6315 * connected.
@@ -6598,8 +6496,7 @@ static int bnx2x_update_link_up(struct link_params *params,
6598 msleep(20); 6496 msleep(20);
6599 return rc; 6497 return rc;
6600} 6498}
6601/* 6499/* The bnx2x_link_update function should be called upon link
6602 * The bnx2x_link_update function should be called upon link
6603 * interrupt. 6500 * interrupt.
6604 * Link is considered up as follows: 6501 * Link is considered up as follows:
6605 * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs 6502 * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
@@ -6656,8 +6553,7 @@ int bnx2x_link_update(struct link_params *params, struct link_vars *vars)
6656 if (!CHIP_IS_E3(bp)) 6553 if (!CHIP_IS_E3(bp))
6657 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); 6554 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6658 6555
6659 /* 6556 /* Step 1:
6660 * Step 1:
6661 * Check external link change only for external phys, and apply 6557 * Check external link change only for external phys, and apply
6662 * priority selection between them in case the link on both phys 6558 * priority selection between them in case the link on both phys
6663 * is up. Note that instead of the common vars, a temporary 6559 * is up. Note that instead of the common vars, a temporary
@@ -6688,23 +6584,20 @@ int bnx2x_link_update(struct link_params *params, struct link_vars *vars)
6688 switch (bnx2x_phy_selection(params)) { 6584 switch (bnx2x_phy_selection(params)) {
6689 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT: 6585 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6690 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: 6586 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6691 /* 6587 /* In this option, the first PHY makes sure to pass the
6692 * In this option, the first PHY makes sure to pass the
6693 * traffic through itself only. 6588 * traffic through itself only.
6694 * Its not clear how to reset the link on the second phy 6589 * Its not clear how to reset the link on the second phy
6695 */ 6590 */
6696 active_external_phy = EXT_PHY1; 6591 active_external_phy = EXT_PHY1;
6697 break; 6592 break;
6698 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: 6593 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6699 /* 6594 /* In this option, the first PHY makes sure to pass the
6700 * In this option, the first PHY makes sure to pass the
6701 * traffic through the second PHY. 6595 * traffic through the second PHY.
6702 */ 6596 */
6703 active_external_phy = EXT_PHY2; 6597 active_external_phy = EXT_PHY2;
6704 break; 6598 break;
6705 default: 6599 default:
6706 /* 6600 /* Link indication on both PHYs with the following cases
6707 * Link indication on both PHYs with the following cases
6708 * is invalid: 6601 * is invalid:
6709 * - FIRST_PHY means that second phy wasn't initialized, 6602 * - FIRST_PHY means that second phy wasn't initialized,
6710 * hence its link is expected to be down 6603 * hence its link is expected to be down
@@ -6721,8 +6614,7 @@ int bnx2x_link_update(struct link_params *params, struct link_vars *vars)
6721 } 6614 }
6722 } 6615 }
6723 prev_line_speed = vars->line_speed; 6616 prev_line_speed = vars->line_speed;
6724 /* 6617 /* Step 2:
6725 * Step 2:
6726 * Read the status of the internal phy. In case of 6618 * Read the status of the internal phy. In case of
6727 * DIRECT_SINGLE_MEDIA board, this link is the external link, 6619 * DIRECT_SINGLE_MEDIA board, this link is the external link,
6728 * otherwise this is the link between the 577xx and the first 6620 * otherwise this is the link between the 577xx and the first
@@ -6732,8 +6624,7 @@ int bnx2x_link_update(struct link_params *params, struct link_vars *vars)
6732 params->phy[INT_PHY].read_status( 6624 params->phy[INT_PHY].read_status(
6733 &params->phy[INT_PHY], 6625 &params->phy[INT_PHY],
6734 params, vars); 6626 params, vars);
6735 /* 6627 /* The INT_PHY flow control reside in the vars. This include the
6736 * The INT_PHY flow control reside in the vars. This include the
6737 * case where the speed or flow control are not set to AUTO. 6628 * case where the speed or flow control are not set to AUTO.
6738 * Otherwise, the active external phy flow control result is set 6629 * Otherwise, the active external phy flow control result is set
6739 * to the vars. The ext_phy_line_speed is needed to check if the 6630 * to the vars. The ext_phy_line_speed is needed to check if the
@@ -6742,14 +6633,12 @@ int bnx2x_link_update(struct link_params *params, struct link_vars *vars)
6742 */ 6633 */
6743 if (active_external_phy > INT_PHY) { 6634 if (active_external_phy > INT_PHY) {
6744 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl; 6635 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;
6745 /* 6636 /* Link speed is taken from the XGXS. AN and FC result from
6746 * Link speed is taken from the XGXS. AN and FC result from
6747 * the external phy. 6637 * the external phy.
6748 */ 6638 */
6749 vars->link_status |= phy_vars[active_external_phy].link_status; 6639 vars->link_status |= phy_vars[active_external_phy].link_status;
6750 6640
6751 /* 6641 /* if active_external_phy is first PHY and link is up - disable
6752 * if active_external_phy is first PHY and link is up - disable
6753 * disable TX on second external PHY 6642 * disable TX on second external PHY
6754 */ 6643 */
6755 if (active_external_phy == EXT_PHY1) { 6644 if (active_external_phy == EXT_PHY1) {
@@ -6786,8 +6675,7 @@ int bnx2x_link_update(struct link_params *params, struct link_vars *vars)
6786 DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x," 6675 DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
6787 " ext_phy_line_speed = %d\n", vars->flow_ctrl, 6676 " ext_phy_line_speed = %d\n", vars->flow_ctrl,
6788 vars->link_status, ext_phy_line_speed); 6677 vars->link_status, ext_phy_line_speed);
6789 /* 6678 /* Upon link speed change set the NIG into drain mode. Comes to
6790 * Upon link speed change set the NIG into drain mode. Comes to
6791 * deals with possible FIFO glitch due to clk change when speed 6679 * deals with possible FIFO glitch due to clk change when speed
6792 * is decreased without link down indicator 6680 * is decreased without link down indicator
6793 */ 6681 */
@@ -6812,8 +6700,7 @@ int bnx2x_link_update(struct link_params *params, struct link_vars *vars)
6812 6700
6813 bnx2x_link_int_ack(params, vars, link_10g_plus); 6701 bnx2x_link_int_ack(params, vars, link_10g_plus);
6814 6702
6815 /* 6703 /* In case external phy link is up, and internal link is down
6816 * In case external phy link is up, and internal link is down
6817 * (not initialized yet probably after link initialization, it 6704 * (not initialized yet probably after link initialization, it
6818 * needs to be initialized. 6705 * needs to be initialized.
6819 * Note that after link down-up as result of cable plug, the xgxs 6706 * Note that after link down-up as result of cable plug, the xgxs
@@ -6841,8 +6728,7 @@ int bnx2x_link_update(struct link_params *params, struct link_vars *vars)
6841 vars); 6728 vars);
6842 } 6729 }
6843 } 6730 }
6844 /* 6731 /* Link is up only if both local phy and external phy (in case of
6845 * Link is up only if both local phy and external phy (in case of
6846 * non-direct board) are up and no fault detected on active PHY. 6732 * non-direct board) are up and no fault detected on active PHY.
6847 */ 6733 */
6848 vars->link_up = (vars->phy_link_up && 6734 vars->link_up = (vars->phy_link_up &&
@@ -7068,8 +6954,7 @@ static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy)
7068 } 6954 }
7069 /* XAUI workaround in 8073 A0: */ 6955 /* XAUI workaround in 8073 A0: */
7070 6956
7071 /* 6957 /* After loading the boot ROM and restarting Autoneg, poll
7072 * After loading the boot ROM and restarting Autoneg, poll
7073 * Dev1, Reg $C820: 6958 * Dev1, Reg $C820:
7074 */ 6959 */
7075 6960
@@ -7078,8 +6963,7 @@ static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy)
7078 MDIO_PMA_DEVAD, 6963 MDIO_PMA_DEVAD,
7079 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, 6964 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7080 &val); 6965 &val);
7081 /* 6966 /* If bit [14] = 0 or bit [13] = 0, continue on with
7082 * If bit [14] = 0 or bit [13] = 0, continue on with
7083 * system initialization (XAUI work-around not required, as 6967 * system initialization (XAUI work-around not required, as
7084 * these bits indicate 2.5G or 1G link up). 6968 * these bits indicate 2.5G or 1G link up).
7085 */ 6969 */
@@ -7088,8 +6972,7 @@ static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy)
7088 return 0; 6972 return 0;
7089 } else if (!(val & (1<<15))) { 6973 } else if (!(val & (1<<15))) {
7090 DP(NETIF_MSG_LINK, "bit 15 went off\n"); 6974 DP(NETIF_MSG_LINK, "bit 15 went off\n");
7091 /* 6975 /* If bit 15 is 0, then poll Dev1, Reg $C841 until it's
7092 * If bit 15 is 0, then poll Dev1, Reg $C841 until it's
7093 * MSB (bit15) goes to 1 (indicating that the XAUI 6976 * MSB (bit15) goes to 1 (indicating that the XAUI
7094 * workaround has completed), then continue on with 6977 * workaround has completed), then continue on with
7095 * system initialization. 6978 * system initialization.
@@ -7239,8 +7122,7 @@ static int bnx2x_8073_config_init(struct bnx2x_phy *phy,
7239 val = (1<<7); 7122 val = (1<<7);
7240 } else if (phy->req_line_speed == SPEED_2500) { 7123 } else if (phy->req_line_speed == SPEED_2500) {
7241 val = (1<<5); 7124 val = (1<<5);
7242 /* 7125 /* Note that 2.5G works only when used with 1G
7243 * Note that 2.5G works only when used with 1G
7244 * advertisement 7126 * advertisement
7245 */ 7127 */
7246 } else 7128 } else
@@ -7291,8 +7173,7 @@ static int bnx2x_8073_config_init(struct bnx2x_phy *phy,
7291 /* Add support for CL37 (passive mode) III */ 7173 /* Add support for CL37 (passive mode) III */
7292 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); 7174 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
7293 7175
7294 /* 7176 /* The SNR will improve about 2db by changing BW and FEE main
7295 * The SNR will improve about 2db by changing BW and FEE main
7296 * tap. Rest commands are executed after link is up 7177 * tap. Rest commands are executed after link is up
7297 * Change FFE main cursor to 5 in EDC register 7178 * Change FFE main cursor to 5 in EDC register
7298 */ 7179 */
@@ -7379,8 +7260,7 @@ static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy,
7379 7260
7380 link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1))); 7261 link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1)));
7381 if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) { 7262 if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) {
7382 /* 7263 /* The SNR will improve about 2dbby changing the BW and FEE main
7383 * The SNR will improve about 2dbby changing the BW and FEE main
7384 * tap. The 1st write to change FFE main tap is set before 7264 * tap. The 1st write to change FFE main tap is set before
7385 * restart AN. Change PLL Bandwidth in EDC register 7265 * restart AN. Change PLL Bandwidth in EDC register
7386 */ 7266 */
@@ -7427,8 +7307,7 @@ static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy,
7427 bnx2x_cl45_read(bp, phy, 7307 bnx2x_cl45_read(bp, phy,
7428 MDIO_XS_DEVAD, 7308 MDIO_XS_DEVAD,
7429 MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1); 7309 MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1);
7430 /* 7310 /* Set bit 3 to invert Rx in 1G mode and clear this bit
7431 * Set bit 3 to invert Rx in 1G mode and clear this bit
7432 * when it`s in 10G mode. 7311 * when it`s in 10G mode.
7433 */ 7312 */
7434 if (vars->line_speed == SPEED_1000) { 7313 if (vars->line_speed == SPEED_1000) {
@@ -7550,8 +7429,7 @@ static void bnx2x_set_disable_pmd_transmit(struct link_params *params,
7550 u8 pmd_dis) 7429 u8 pmd_dis)
7551{ 7430{
7552 struct bnx2x *bp = params->bp; 7431 struct bnx2x *bp = params->bp;
7553 /* 7432 /* Disable transmitter only for bootcodes which can enable it afterwards
7554 * Disable transmitter only for bootcodes which can enable it afterwards
7555 * (for D3 link) 7433 * (for D3 link)
7556 */ 7434 */
7557 if (pmd_dis) { 7435 if (pmd_dis) {
@@ -7728,9 +7606,6 @@ static int bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7728 u32 data_array[4]; 7606 u32 data_array[4];
7729 u16 addr32; 7607 u16 addr32;
7730 struct bnx2x *bp = params->bp; 7608 struct bnx2x *bp = params->bp;
7731 /*DP(NETIF_MSG_LINK, "bnx2x_direct_read_sfp_module_eeprom:"
7732 " addr %d, cnt %d\n",
7733 addr, byte_cnt);*/
7734 if (byte_cnt > 16) { 7609 if (byte_cnt > 16) {
7735 DP(NETIF_MSG_LINK, 7610 DP(NETIF_MSG_LINK,
7736 "Reading from eeprom is limited to 16 bytes\n"); 7611 "Reading from eeprom is limited to 16 bytes\n");
@@ -7795,8 +7670,7 @@ static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7795 MDIO_PMA_DEVAD, 7670 MDIO_PMA_DEVAD,
7796 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, 7671 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7797 0x8002); 7672 0x8002);
7798 /* 7673 /* Wait appropriate time for two-wire command to finish before
7799 * Wait appropriate time for two-wire command to finish before
7800 * polling the status register 7674 * polling the status register
7801 */ 7675 */
7802 msleep(1); 7676 msleep(1);
@@ -7889,8 +7763,7 @@ static int bnx2x_get_edc_mode(struct bnx2x_phy *phy,
7889 { 7763 {
7890 u8 copper_module_type; 7764 u8 copper_module_type;
7891 phy->media_type = ETH_PHY_DA_TWINAX; 7765 phy->media_type = ETH_PHY_DA_TWINAX;
7892 /* 7766 /* Check if its active cable (includes SFP+ module)
7893 * Check if its active cable (includes SFP+ module)
7894 * of passive cable 7767 * of passive cable
7895 */ 7768 */
7896 if (bnx2x_read_sfp_module_eeprom(phy, 7769 if (bnx2x_read_sfp_module_eeprom(phy,
@@ -7967,8 +7840,7 @@ static int bnx2x_get_edc_mode(struct bnx2x_phy *phy,
7967 DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode); 7840 DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode);
7968 return 0; 7841 return 0;
7969} 7842}
7970/* 7843/* This function read the relevant field from the module (SFP+), and verify it
7971 * This function read the relevant field from the module (SFP+), and verify it
7972 * is compliant with this board 7844 * is compliant with this board
7973 */ 7845 */
7974static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy, 7846static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy,
@@ -8048,8 +7920,7 @@ static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy,
8048 u8 val; 7920 u8 val;
8049 struct bnx2x *bp = params->bp; 7921 struct bnx2x *bp = params->bp;
8050 u16 timeout; 7922 u16 timeout;
8051 /* 7923 /* Initialization time after hot-plug may take up to 300ms for
8052 * Initialization time after hot-plug may take up to 300ms for
8053 * some phys type ( e.g. JDSU ) 7924 * some phys type ( e.g. JDSU )
8054 */ 7925 */
8055 7926
@@ -8071,8 +7942,7 @@ static void bnx2x_8727_power_module(struct bnx2x *bp,
8071 u8 is_power_up) { 7942 u8 is_power_up) {
8072 /* Make sure GPIOs are not using for LED mode */ 7943 /* Make sure GPIOs are not using for LED mode */
8073 u16 val; 7944 u16 val;
8074 /* 7945 /* In the GPIO register, bit 4 is use to determine if the GPIOs are
8075 * In the GPIO register, bit 4 is use to determine if the GPIOs are
8076 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for 7946 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
8077 * output 7947 * output
8078 * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0 7948 * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0
@@ -8088,8 +7958,7 @@ static void bnx2x_8727_power_module(struct bnx2x *bp,
8088 if (is_power_up) 7958 if (is_power_up)
8089 val = (1<<4); 7959 val = (1<<4);
8090 else 7960 else
8091 /* 7961 /* Set GPIO control to OUTPUT, and set the power bit
8092 * Set GPIO control to OUTPUT, and set the power bit
8093 * to according to the is_power_up 7962 * to according to the is_power_up
8094 */ 7963 */
8095 val = (1<<1); 7964 val = (1<<1);
@@ -8123,8 +7992,7 @@ static int bnx2x_8726_set_limiting_mode(struct bnx2x *bp,
8123 7992
8124 DP(NETIF_MSG_LINK, "Setting LRM MODE\n"); 7993 DP(NETIF_MSG_LINK, "Setting LRM MODE\n");
8125 7994
8126 /* 7995 /* Changing to LRM mode takes quite few seconds. So do it only
8127 * Changing to LRM mode takes quite few seconds. So do it only
8128 * if current mode is limiting (default is LRM) 7996 * if current mode is limiting (default is LRM)
8129 */ 7997 */
8130 if (cur_limiting_mode != EDC_MODE_LIMITING) 7998 if (cur_limiting_mode != EDC_MODE_LIMITING)
@@ -8259,8 +8127,7 @@ static void bnx2x_set_sfp_module_fault_led(struct link_params *params,
8259 struct bnx2x *bp = params->bp; 8127 struct bnx2x *bp = params->bp;
8260 DP(NETIF_MSG_LINK, "Setting SFP+ module fault LED to %d\n", gpio_mode); 8128 DP(NETIF_MSG_LINK, "Setting SFP+ module fault LED to %d\n", gpio_mode);
8261 if (CHIP_IS_E3(bp)) { 8129 if (CHIP_IS_E3(bp)) {
8262 /* 8130 /* Low ==> if SFP+ module is supported otherwise
8263 * Low ==> if SFP+ module is supported otherwise
8264 * High ==> if SFP+ module is not on the approved vendor list 8131 * High ==> if SFP+ module is not on the approved vendor list
8265 */ 8132 */
8266 bnx2x_set_e3_module_fault_led(params, gpio_mode); 8133 bnx2x_set_e3_module_fault_led(params, gpio_mode);
@@ -8285,8 +8152,7 @@ static void bnx2x_warpcore_power_module(struct link_params *params,
8285 return; 8152 return;
8286 DP(NETIF_MSG_LINK, "Setting SFP+ module power to %d using pin cfg %d\n", 8153 DP(NETIF_MSG_LINK, "Setting SFP+ module power to %d using pin cfg %d\n",
8287 power, pin_cfg); 8154 power, pin_cfg);
8288 /* 8155 /* Low ==> corresponding SFP+ module is powered
8289 * Low ==> corresponding SFP+ module is powered
8290 * high ==> the SFP+ module is powered down 8156 * high ==> the SFP+ module is powered down
8291 */ 8157 */
8292 bnx2x_set_cfg_pin(bp, pin_cfg, power ^ 1); 8158 bnx2x_set_cfg_pin(bp, pin_cfg, power ^ 1);
@@ -8420,14 +8286,12 @@ int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
8420 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW); 8286 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW);
8421 } 8287 }
8422 8288
8423 /* 8289 /* Check and set limiting mode / LRM mode on 8726. On 8727 it
8424 * Check and set limiting mode / LRM mode on 8726. On 8727 it
8425 * is done automatically 8290 * is done automatically
8426 */ 8291 */
8427 bnx2x_set_limiting_mode(params, phy, edc_mode); 8292 bnx2x_set_limiting_mode(params, phy, edc_mode);
8428 8293
8429 /* 8294 /* Enable transmit for this module if the module is approved, or
8430 * Enable transmit for this module if the module is approved, or
8431 * if unapproved modules should also enable the Tx laser 8295 * if unapproved modules should also enable the Tx laser
8432 */ 8296 */
8433 if (rc == 0 || 8297 if (rc == 0 ||
@@ -8482,8 +8346,7 @@ void bnx2x_handle_module_detect_int(struct link_params *params)
8482 bnx2x_set_gpio_int(bp, gpio_num, 8346 bnx2x_set_gpio_int(bp, gpio_num,
8483 MISC_REGISTERS_GPIO_INT_OUTPUT_SET, 8347 MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
8484 gpio_port); 8348 gpio_port);
8485 /* 8349 /* Module was plugged out.
8486 * Module was plugged out.
8487 * Disable transmit for this module 8350 * Disable transmit for this module
8488 */ 8351 */
8489 phy->media_type = ETH_PHY_NOT_PRESENT; 8352 phy->media_type = ETH_PHY_NOT_PRESENT;
@@ -8553,8 +8416,7 @@ static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy,
8553 8416
8554 DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps" 8417 DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
8555 " link_status 0x%x\n", rx_sd, pcs_status, val2); 8418 " link_status 0x%x\n", rx_sd, pcs_status, val2);
8556 /* 8419 /* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
8557 * link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
8558 * are set, or if the autoneg bit 1 is set 8420 * are set, or if the autoneg bit 1 is set
8559 */ 8421 */
8560 link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1))); 8422 link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
@@ -8668,8 +8530,7 @@ static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy,
8668 } 8530 }
8669 bnx2x_save_bcm_spirom_ver(bp, phy, params->port); 8531 bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
8670 8532
8671 /* 8533 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
8672 * If TX Laser is controlled by GPIO_0, do not let PHY go into low
8673 * power mode, if TX Laser is disabled 8534 * power mode, if TX Laser is disabled
8674 */ 8535 */
8675 8536
@@ -8779,8 +8640,7 @@ static int bnx2x_8726_config_init(struct bnx2x_phy *phy,
8779 8640
8780 bnx2x_8726_external_rom_boot(phy, params); 8641 bnx2x_8726_external_rom_boot(phy, params);
8781 8642
8782 /* 8643 /* Need to call module detected on initialization since the module
8783 * Need to call module detected on initialization since the module
8784 * detection triggered by actual module insertion might occur before 8644 * detection triggered by actual module insertion might occur before
8785 * driver is loaded, and when driver is loaded, it reset all 8645 * driver is loaded, and when driver is loaded, it reset all
8786 * registers, including the transmitter 8646 * registers, including the transmitter
@@ -8817,8 +8677,7 @@ static int bnx2x_8726_config_init(struct bnx2x_phy *phy,
8817 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); 8677 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8818 bnx2x_cl45_write(bp, phy, 8678 bnx2x_cl45_write(bp, phy,
8819 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); 8679 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8820 /* 8680 /* Enable RX-ALARM control to receive interrupt for 1G speed
8821 * Enable RX-ALARM control to receive interrupt for 1G speed
8822 * change 8681 * change
8823 */ 8682 */
8824 bnx2x_cl45_write(bp, phy, 8683 bnx2x_cl45_write(bp, phy,
@@ -8919,8 +8778,7 @@ static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy,
8919 struct link_params *params) { 8778 struct link_params *params) {
8920 u32 swap_val, swap_override; 8779 u32 swap_val, swap_override;
8921 u8 port; 8780 u8 port;
8922 /* 8781 /* The PHY reset is controlled by GPIO 1. Fake the port number
8923 * The PHY reset is controlled by GPIO 1. Fake the port number
8924 * to cancel the swap done in set_gpio() 8782 * to cancel the swap done in set_gpio()
8925 */ 8783 */
8926 struct bnx2x *bp = params->bp; 8784 struct bnx2x *bp = params->bp;
@@ -8958,14 +8816,12 @@ static int bnx2x_8727_config_init(struct bnx2x_phy *phy,
8958 bnx2x_cl45_write(bp, phy, 8816 bnx2x_cl45_write(bp, phy,
8959 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, lasi_ctrl_val); 8817 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, lasi_ctrl_val);
8960 8818
8961 /* 8819 /* Initially configure MOD_ABS to interrupt when module is
8962 * Initially configure MOD_ABS to interrupt when module is
8963 * presence( bit 8) 8820 * presence( bit 8)
8964 */ 8821 */
8965 bnx2x_cl45_read(bp, phy, 8822 bnx2x_cl45_read(bp, phy,
8966 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs); 8823 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
8967 /* 8824 /* Set EDC off by setting OPTXLOS signal input to low (bit 9).
8968 * Set EDC off by setting OPTXLOS signal input to low (bit 9).
8969 * When the EDC is off it locks onto a reference clock and avoids 8825 * When the EDC is off it locks onto a reference clock and avoids
8970 * becoming 'lost' 8826 * becoming 'lost'
8971 */ 8827 */
@@ -8986,8 +8842,7 @@ static int bnx2x_8727_config_init(struct bnx2x_phy *phy,
8986 if (phy->flags & FLAGS_NOC) 8842 if (phy->flags & FLAGS_NOC)
8987 val |= (3<<5); 8843 val |= (3<<5);
8988 8844
8989 /* 8845 /* Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
8990 * Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
8991 * status which reflect SFP+ module over-current 8846 * status which reflect SFP+ module over-current
8992 */ 8847 */
8993 if (!(phy->flags & FLAGS_NOC)) 8848 if (!(phy->flags & FLAGS_NOC))
@@ -9013,8 +8868,7 @@ static int bnx2x_8727_config_init(struct bnx2x_phy *phy,
9013 bnx2x_cl45_read(bp, phy, 8868 bnx2x_cl45_read(bp, phy,
9014 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1); 8869 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
9015 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1); 8870 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1);
9016 /* 8871 /* Power down the XAUI until link is up in case of dual-media
9017 * Power down the XAUI until link is up in case of dual-media
9018 * and 1G 8872 * and 1G
9019 */ 8873 */
9020 if (DUAL_MEDIA(params)) { 8874 if (DUAL_MEDIA(params)) {
@@ -9039,8 +8893,7 @@ static int bnx2x_8727_config_init(struct bnx2x_phy *phy,
9039 bnx2x_cl45_write(bp, phy, 8893 bnx2x_cl45_write(bp, phy,
9040 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300); 8894 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
9041 } else { 8895 } else {
9042 /* 8896 /* Since the 8727 has only single reset pin, need to set the 10G
9043 * Since the 8727 has only single reset pin, need to set the 10G
9044 * registers although it is default 8897 * registers although it is default
9045 */ 8898 */
9046 bnx2x_cl45_write(bp, phy, 8899 bnx2x_cl45_write(bp, phy,
@@ -9055,8 +8908,7 @@ static int bnx2x_8727_config_init(struct bnx2x_phy *phy,
9055 0x0008); 8908 0x0008);
9056 } 8909 }
9057 8910
9058 /* 8911 /* Set 2-wire transfer rate of SFP+ module EEPROM
9059 * Set 2-wire transfer rate of SFP+ module EEPROM
9060 * to 100Khz since some DACs(direct attached cables) do 8912 * to 100Khz since some DACs(direct attached cables) do
9061 * not work at 400Khz. 8913 * not work at 400Khz.
9062 */ 8914 */
@@ -9079,8 +8931,7 @@ static int bnx2x_8727_config_init(struct bnx2x_phy *phy,
9079 phy->tx_preemphasis[1]); 8931 phy->tx_preemphasis[1]);
9080 } 8932 }
9081 8933
9082 /* 8934 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
9083 * If TX Laser is controlled by GPIO_0, do not let PHY go into low
9084 * power mode, if TX Laser is disabled 8935 * power mode, if TX Laser is disabled
9085 */ 8936 */
9086 tx_en_mode = REG_RD(bp, params->shmem_base + 8937 tx_en_mode = REG_RD(bp, params->shmem_base +
@@ -9120,8 +8971,7 @@ static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
9120 DP(NETIF_MSG_LINK, 8971 DP(NETIF_MSG_LINK,
9121 "MOD_ABS indication show module is absent\n"); 8972 "MOD_ABS indication show module is absent\n");
9122 phy->media_type = ETH_PHY_NOT_PRESENT; 8973 phy->media_type = ETH_PHY_NOT_PRESENT;
9123 /* 8974 /* 1. Set mod_abs to detect next module
9124 * 1. Set mod_abs to detect next module
9125 * presence event 8975 * presence event
9126 * 2. Set EDC off by setting OPTXLOS signal input to low 8976 * 2. Set EDC off by setting OPTXLOS signal input to low
9127 * (bit 9). 8977 * (bit 9).
@@ -9135,8 +8985,7 @@ static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
9135 MDIO_PMA_DEVAD, 8985 MDIO_PMA_DEVAD,
9136 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); 8986 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9137 8987
9138 /* 8988 /* Clear RX alarm since it stays up as long as
9139 * Clear RX alarm since it stays up as long as
9140 * the mod_abs wasn't changed 8989 * the mod_abs wasn't changed
9141 */ 8990 */
9142 bnx2x_cl45_read(bp, phy, 8991 bnx2x_cl45_read(bp, phy,
@@ -9147,8 +8996,7 @@ static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
9147 /* Module is present */ 8996 /* Module is present */
9148 DP(NETIF_MSG_LINK, 8997 DP(NETIF_MSG_LINK,
9149 "MOD_ABS indication show module is present\n"); 8998 "MOD_ABS indication show module is present\n");
9150 /* 8999 /* First disable transmitter, and if the module is ok, the
9151 * First disable transmitter, and if the module is ok, the
9152 * module_detection will enable it 9000 * module_detection will enable it
9153 * 1. Set mod_abs to detect next module absent event ( bit 8) 9001 * 1. Set mod_abs to detect next module absent event ( bit 8)
9154 * 2. Restore the default polarity of the OPRXLOS signal and 9002 * 2. Restore the default polarity of the OPRXLOS signal and
@@ -9162,8 +9010,7 @@ static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
9162 MDIO_PMA_DEVAD, 9010 MDIO_PMA_DEVAD,
9163 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); 9011 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9164 9012
9165 /* 9013 /* Clear RX alarm since it stays up as long as the mod_abs
9166 * Clear RX alarm since it stays up as long as the mod_abs
9167 * wasn't changed. This is need to be done before calling the 9014 * wasn't changed. This is need to be done before calling the
9168 * module detection, otherwise it will clear* the link update 9015 * module detection, otherwise it will clear* the link update
9169 * alarm 9016 * alarm
@@ -9224,8 +9071,7 @@ static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy,
9224 bnx2x_cl45_read(bp, phy, 9071 bnx2x_cl45_read(bp, phy,
9225 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1); 9072 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
9226 9073
9227 /* 9074 /* If a module is present and there is need to check
9228 * If a module is present and there is need to check
9229 * for over current 9075 * for over current
9230 */ 9076 */
9231 if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) { 9077 if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) {
@@ -9291,8 +9137,7 @@ static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy,
9291 MDIO_PMA_DEVAD, 9137 MDIO_PMA_DEVAD,
9292 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status); 9138 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);
9293 9139
9294 /* 9140 /* Bits 0..2 --> speed detected,
9295 * Bits 0..2 --> speed detected,
9296 * Bits 13..15--> link is down 9141 * Bits 13..15--> link is down
9297 */ 9142 */
9298 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) { 9143 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
@@ -9335,8 +9180,7 @@ static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy,
9335 bnx2x_cl45_read(bp, phy, 9180 bnx2x_cl45_read(bp, phy,
9336 MDIO_PMA_DEVAD, 9181 MDIO_PMA_DEVAD,
9337 MDIO_PMA_REG_8727_PCS_GP, &val1); 9182 MDIO_PMA_REG_8727_PCS_GP, &val1);
9338 /* 9183 /* In case of dual-media board and 1G, power up the XAUI side,
9339 * In case of dual-media board and 1G, power up the XAUI side,
9340 * otherwise power it down. For 10G it is done automatically 9184 * otherwise power it down. For 10G it is done automatically
9341 */ 9185 */
9342 if (link_up) 9186 if (link_up)
@@ -9503,8 +9347,7 @@ static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
9503 /* Save spirom version */ 9347 /* Save spirom version */
9504 bnx2x_save_848xx_spirom_version(phy, bp, params->port); 9348 bnx2x_save_848xx_spirom_version(phy, bp, params->port);
9505 } 9349 }
9506 /* 9350 /* This phy uses the NIG latch mechanism since link indication
9507 * This phy uses the NIG latch mechanism since link indication
9508 * arrives through its LED4 and not via its LASI signal, so we 9351 * arrives through its LED4 and not via its LASI signal, so we
9509 * get steady signal instead of clear on read 9352 * get steady signal instead of clear on read
9510 */ 9353 */
@@ -9609,8 +9452,7 @@ static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
9609 if (phy->req_duplex == DUPLEX_FULL) 9452 if (phy->req_duplex == DUPLEX_FULL)
9610 autoneg_val |= (1<<8); 9453 autoneg_val |= (1<<8);
9611 9454
9612 /* 9455 /* Always write this if this is not 84833.
9613 * Always write this if this is not 84833.
9614 * For 84833, write it only when it's a forced speed. 9456 * For 84833, write it only when it's a forced speed.
9615 */ 9457 */
9616 if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || 9458 if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
@@ -9849,8 +9691,7 @@ static int bnx2x_848x3_config_init(struct bnx2x_phy *phy,
9849 /* Wait for GPHY to come out of reset */ 9691 /* Wait for GPHY to come out of reset */
9850 msleep(50); 9692 msleep(50);
9851 if (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) { 9693 if (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) {
9852 /* 9694 /* BCM84823 requires that XGXS links up first @ 10G for normal
9853 * BCM84823 requires that XGXS links up first @ 10G for normal
9854 * behavior. 9695 * behavior.
9855 */ 9696 */
9856 u16 temp; 9697 u16 temp;
@@ -10326,8 +10167,7 @@ static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,
10326 break; 10167 break;
10327 } 10168 }
10328 10169
10329 /* 10170 /* This is a workaround for E3+84833 until autoneg
10330 * This is a workaround for E3+84833 until autoneg
10331 * restart is fixed in f/w 10171 * restart is fixed in f/w
10332 */ 10172 */
10333 if (CHIP_IS_E3(bp)) { 10173 if (CHIP_IS_E3(bp)) {
@@ -10351,8 +10191,7 @@ static int bnx2x_54618se_config_init(struct bnx2x_phy *phy,
10351 DP(NETIF_MSG_LINK, "54618SE cfg init\n"); 10191 DP(NETIF_MSG_LINK, "54618SE cfg init\n");
10352 usleep_range(1000, 1000); 10192 usleep_range(1000, 1000);
10353 10193
10354 /* 10194 /* This works with E3 only, no need to check the chip
10355 * This works with E3 only, no need to check the chip
10356 * before determining the port. 10195 * before determining the port.
10357 */ 10196 */
10358 port = params->port; 10197 port = params->port;
@@ -10374,7 +10213,7 @@ static int bnx2x_54618se_config_init(struct bnx2x_phy *phy,
10374 MDIO_PMA_REG_CTRL, 0x8000); 10213 MDIO_PMA_REG_CTRL, 0x8000);
10375 bnx2x_wait_reset_complete(bp, phy, params); 10214 bnx2x_wait_reset_complete(bp, phy, params);
10376 10215
10377 /*wait for GPHY to reset */ 10216 /* Wait for GPHY to reset */
10378 msleep(50); 10217 msleep(50);
10379 10218
10380 /* Configure LED4: set to INTR (0x6). */ 10219 /* Configure LED4: set to INTR (0x6). */
@@ -10580,13 +10419,11 @@ static void bnx2x_54618se_link_reset(struct bnx2x_phy *phy,
10580 u32 cfg_pin; 10419 u32 cfg_pin;
10581 u8 port; 10420 u8 port;
10582 10421
10583 /* 10422 /* In case of no EPIO routed to reset the GPHY, put it
10584 * In case of no EPIO routed to reset the GPHY, put it
10585 * in low power mode. 10423 * in low power mode.
10586 */ 10424 */
10587 bnx2x_cl22_write(bp, phy, MDIO_PMA_REG_CTRL, 0x800); 10425 bnx2x_cl22_write(bp, phy, MDIO_PMA_REG_CTRL, 0x800);
10588 /* 10426 /* This works with E3 only, no need to check the chip
10589 * This works with E3 only, no need to check the chip
10590 * before determining the port. 10427 * before determining the port.
10591 */ 10428 */
10592 port = params->port; 10429 port = params->port;
@@ -10695,7 +10532,7 @@ static u8 bnx2x_54618se_read_status(struct bnx2x_phy *phy,
10695 bnx2x_ext_phy_resolve_fc(phy, params, vars); 10532 bnx2x_ext_phy_resolve_fc(phy, params, vars);
10696 10533
10697 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { 10534 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
10698 /* report LP advertised speeds */ 10535 /* Report LP advertised speeds */
10699 bnx2x_cl22_read(bp, phy, 0x5, &val); 10536 bnx2x_cl22_read(bp, phy, 0x5, &val);
10700 10537
10701 if (val & (1<<5)) 10538 if (val & (1<<5))
@@ -10760,8 +10597,7 @@ static void bnx2x_54618se_config_loopback(struct bnx2x_phy *phy,
10760 /* This register opens the gate for the UMAC despite its name */ 10597 /* This register opens the gate for the UMAC despite its name */
10761 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1); 10598 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
10762 10599
10763 /* 10600 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
10764 * Maximum Frame Length (RW). Defines a 14-Bit maximum frame
10765 * length used by the MAC receive logic to check frames. 10601 * length used by the MAC receive logic to check frames.
10766 */ 10602 */
10767 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710); 10603 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
@@ -11040,17 +10876,17 @@ static struct bnx2x_phy phy_warpcore = {
11040 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 10876 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11041 .mdio_ctrl = 0, 10877 .mdio_ctrl = 0,
11042 .supported = (SUPPORTED_10baseT_Half | 10878 .supported = (SUPPORTED_10baseT_Half |
11043 SUPPORTED_10baseT_Full | 10879 SUPPORTED_10baseT_Full |
11044 SUPPORTED_100baseT_Half | 10880 SUPPORTED_100baseT_Half |
11045 SUPPORTED_100baseT_Full | 10881 SUPPORTED_100baseT_Full |
11046 SUPPORTED_1000baseT_Full | 10882 SUPPORTED_1000baseT_Full |
11047 SUPPORTED_10000baseT_Full | 10883 SUPPORTED_10000baseT_Full |
11048 SUPPORTED_20000baseKR2_Full | 10884 SUPPORTED_20000baseKR2_Full |
11049 SUPPORTED_20000baseMLD2_Full | 10885 SUPPORTED_20000baseMLD2_Full |
11050 SUPPORTED_FIBRE | 10886 SUPPORTED_FIBRE |
11051 SUPPORTED_Autoneg | 10887 SUPPORTED_Autoneg |
11052 SUPPORTED_Pause | 10888 SUPPORTED_Pause |
11053 SUPPORTED_Asym_Pause), 10889 SUPPORTED_Asym_Pause),
11054 .media_type = ETH_PHY_UNSPECIFIED, 10890 .media_type = ETH_PHY_UNSPECIFIED,
11055 .ver_addr = 0, 10891 .ver_addr = 0,
11056 .req_flow_ctrl = 0, 10892 .req_flow_ctrl = 0,
@@ -11404,9 +11240,8 @@ static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base,
11404 /* Get the 4 lanes xgxs config rx and tx */ 11240 /* Get the 4 lanes xgxs config rx and tx */
11405 u32 rx = 0, tx = 0, i; 11241 u32 rx = 0, tx = 0, i;
11406 for (i = 0; i < 2; i++) { 11242 for (i = 0; i < 2; i++) {
11407 /* 11243 /* INT_PHY and EXT_PHY1 share the same value location in
11408 * INT_PHY and EXT_PHY1 share the same value location in the 11244 * the shmem. When num_phys is greater than 1, than this value
11409 * shmem. When num_phys is greater than 1, than this value
11410 * applies only to EXT_PHY1 11245 * applies only to EXT_PHY1
11411 */ 11246 */
11412 if (phy_index == INT_PHY || phy_index == EXT_PHY1) { 11247 if (phy_index == INT_PHY || phy_index == EXT_PHY1) {
@@ -11484,8 +11319,7 @@ static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port,
11484 offsetof(struct shmem_region, dev_info. 11319 offsetof(struct shmem_region, dev_info.
11485 port_hw_config[port].default_cfg)) & 11320 port_hw_config[port].default_cfg)) &
11486 PORT_HW_CFG_NET_SERDES_IF_MASK); 11321 PORT_HW_CFG_NET_SERDES_IF_MASK);
11487 /* 11322 /* Set the appropriate supported and flags indications per
11488 * Set the appropriate supported and flags indications per
11489 * interface type of the chip 11323 * interface type of the chip
11490 */ 11324 */
11491 switch (serdes_net_if) { 11325 switch (serdes_net_if) {
@@ -11543,8 +11377,7 @@ static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port,
11543 break; 11377 break;
11544 } 11378 }
11545 11379
11546 /* 11380 /* Enable MDC/MDIO work-around for E3 A0 since free running MDC
11547 * Enable MDC/MDIO work-around for E3 A0 since free running MDC
11548 * was not set as expected. For B0, ECO will be enabled so there 11381 * was not set as expected. For B0, ECO will be enabled so there
11549 * won't be an issue there 11382 * won't be an issue there
11550 */ 11383 */
@@ -11657,8 +11490,7 @@ static int bnx2x_populate_ext_phy(struct bnx2x *bp,
11657 phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config); 11490 phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config);
11658 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index); 11491 bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index);
11659 11492
11660 /* 11493 /* The shmem address of the phy version is located on different
11661 * The shmem address of the phy version is located on different
11662 * structures. In case this structure is too old, do not set 11494 * structures. In case this structure is too old, do not set
11663 * the address 11495 * the address
11664 */ 11496 */
@@ -11692,8 +11524,7 @@ static int bnx2x_populate_ext_phy(struct bnx2x *bp,
11692 11524
11693 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) && 11525 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
11694 (phy->ver_addr)) { 11526 (phy->ver_addr)) {
11695 /* 11527 /* Remove 100Mb link supported for BCM84833 when phy fw
11696 * Remove 100Mb link supported for BCM84833 when phy fw
11697 * version lower than or equal to 1.39 11528 * version lower than or equal to 1.39
11698 */ 11529 */
11699 u32 raw_ver = REG_RD(bp, phy->ver_addr); 11530 u32 raw_ver = REG_RD(bp, phy->ver_addr);
@@ -11703,8 +11534,7 @@ static int bnx2x_populate_ext_phy(struct bnx2x *bp,
11703 SUPPORTED_100baseT_Full); 11534 SUPPORTED_100baseT_Full);
11704 } 11535 }
11705 11536
11706 /* 11537 /* In case mdc/mdio_access of the external phy is different than the
11707 * In case mdc/mdio_access of the external phy is different than the
11708 * mdc/mdio access of the XGXS, a HW lock must be taken in each access 11538 * mdc/mdio access of the XGXS, a HW lock must be taken in each access
11709 * to prevent one port interfere with another port's CL45 operations. 11539 * to prevent one port interfere with another port's CL45 operations.
11710 */ 11540 */
@@ -11883,8 +11713,7 @@ int bnx2x_phy_probe(struct link_params *params)
11883 dev_info.port_hw_config[params->port].media_type); 11713 dev_info.port_hw_config[params->port].media_type);
11884 media_types = REG_RD(bp, sync_offset); 11714 media_types = REG_RD(bp, sync_offset);
11885 11715
11886 /* 11716 /* Update media type for non-PMF sync only for the first time
11887 * Update media type for non-PMF sync only for the first time
11888 * In case the media type changes afterwards, it will be updated 11717 * In case the media type changes afterwards, it will be updated
11889 * using the update_status function 11718 * using the update_status function
11890 */ 11719 */
@@ -11958,8 +11787,7 @@ void bnx2x_init_xmac_loopback(struct link_params *params,
11958 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE; 11787 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
11959 vars->mac_type = MAC_TYPE_XMAC; 11788 vars->mac_type = MAC_TYPE_XMAC;
11960 vars->phy_flags = PHY_XGXS_FLAG; 11789 vars->phy_flags = PHY_XGXS_FLAG;
11961 /* 11790 /* Set WC to loopback mode since link is required to provide clock
11962 * Set WC to loopback mode since link is required to provide clock
11963 * to the XMAC in 20G mode 11791 * to the XMAC in 20G mode
11964 */ 11792 */
11965 bnx2x_set_aer_mmd(params, &params->phy[0]); 11793 bnx2x_set_aer_mmd(params, &params->phy[0]);
@@ -12242,7 +12070,8 @@ static int bnx2x_8073_common_init_phy(struct bnx2x *bp,
12242 NIG_MASK_MI_INT)); 12070 NIG_MASK_MI_INT));
12243 12071
12244 /* Need to take the phy out of low power mode in order 12072 /* Need to take the phy out of low power mode in order
12245 to write to access its registers */ 12073 * to write to access its registers
12074 */
12246 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2, 12075 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
12247 MISC_REGISTERS_GPIO_OUTPUT_HIGH, 12076 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
12248 port); 12077 port);
@@ -12290,8 +12119,7 @@ static int bnx2x_8073_common_init_phy(struct bnx2x *bp,
12290 (val | 1<<10)); 12119 (val | 1<<10));
12291 } 12120 }
12292 12121
12293 /* 12122 /* Toggle Transmitter: Power down and then up with 600ms delay
12294 * Toggle Transmitter: Power down and then up with 600ms delay
12295 * between 12123 * between
12296 */ 12124 */
12297 msleep(600); 12125 msleep(600);
@@ -12434,8 +12262,7 @@ static int bnx2x_8727_common_init_phy(struct bnx2x *bp,
12434 reset_gpio = MISC_REGISTERS_GPIO_1; 12262 reset_gpio = MISC_REGISTERS_GPIO_1;
12435 port = 1; 12263 port = 1;
12436 12264
12437 /* 12265 /* Retrieve the reset gpio/port which control the reset.
12438 * Retrieve the reset gpio/port which control the reset.
12439 * Default is GPIO1, PORT1 12266 * Default is GPIO1, PORT1
12440 */ 12267 */
12441 bnx2x_get_ext_phy_reset_gpio(bp, shmem_base_path[0], 12268 bnx2x_get_ext_phy_reset_gpio(bp, shmem_base_path[0],
@@ -12610,8 +12437,7 @@ static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[],
12610 break; 12437 break;
12611 12438
12612 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: 12439 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
12613 /* 12440 /* GPIO1 affects both ports, so there's need to pull
12614 * GPIO1 affects both ports, so there's need to pull
12615 * it for single port alone 12441 * it for single port alone
12616 */ 12442 */
12617 rc = bnx2x_8726_common_init_phy(bp, shmem_base_path, 12443 rc = bnx2x_8726_common_init_phy(bp, shmem_base_path,
@@ -12619,8 +12445,7 @@ static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[],
12619 phy_index, chip_id); 12445 phy_index, chip_id);
12620 break; 12446 break;
12621 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833: 12447 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
12622 /* 12448 /* GPIO3's are linked, and so both need to be toggled
12623 * GPIO3's are linked, and so both need to be toggled
12624 * to obtain required 2us pulse. 12449 * to obtain required 2us pulse.
12625 */ 12450 */
12626 rc = bnx2x_84833_common_init_phy(bp, shmem_base_path, 12451 rc = bnx2x_84833_common_init_phy(bp, shmem_base_path,
@@ -12734,8 +12559,7 @@ static void bnx2x_analyze_link_error(struct link_params *params,
12734 DP(NETIF_MSG_LINK, "Link changed:%x %x->%x\n", vars->link_up, 12559 DP(NETIF_MSG_LINK, "Link changed:%x %x->%x\n", vars->link_up,
12735 half_open_conn, lss_status); 12560 half_open_conn, lss_status);
12736 12561
12737 /* 12562 /* a. Update shmem->link_status accordingly
12738 * a. Update shmem->link_status accordingly
12739 * b. Update link_vars->link_up 12563 * b. Update link_vars->link_up
12740 */ 12564 */
12741 if (lss_status) { 12565 if (lss_status) {
@@ -12746,8 +12570,7 @@ static void bnx2x_analyze_link_error(struct link_params *params,
12746 12570
12747 /* activate nig drain */ 12571 /* activate nig drain */
12748 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1); 12572 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);
12749 /* 12573 /* Set LED mode to off since the PHY doesn't know about these
12750 * Set LED mode to off since the PHY doesn't know about these
12751 * errors 12574 * errors
12752 */ 12575 */
12753 led_mode = LED_MODE_OFF; 12576 led_mode = LED_MODE_OFF;
@@ -12799,8 +12622,7 @@ int bnx2x_check_half_open_conn(struct link_params *params,
12799 (REG_RD(bp, MISC_REG_RESET_REG_2) & 12622 (REG_RD(bp, MISC_REG_RESET_REG_2) &
12800 (MISC_REGISTERS_RESET_REG_2_XMAC))) { 12623 (MISC_REGISTERS_RESET_REG_2_XMAC))) {
12801 /* Check E3 XMAC */ 12624 /* Check E3 XMAC */
12802 /* 12625 /* Note that link speed cannot be queried here, since it may be
12803 * Note that link speed cannot be queried here, since it may be
12804 * zero while link is down. In case UMAC is active, LSS will 12626 * zero while link is down. In case UMAC is active, LSS will
12805 * simply not be set 12627 * simply not be set
12806 */ 12628 */
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-04 23:40:19 -0500