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authorLee Jones <lee.jones@linaro.org>2013-08-19 07:23:05 -0400
committerLinus Walleij <linus.walleij@linaro.org>2013-09-26 05:04:16 -0400
commit58092dc4dfde55d5824211e5aa1be47212a57f1f (patch)
tree5854e297e171b911a7178ddcc682c7f5565d13fa /drivers/mfd
parent67f13daadccebf95c04f73db7b78cead844540bd (diff)
mfd: dbx500: Remove any mention of the BML8580CLK
The platform which it pertains to is no longer supported and is actually causing some confusion in the new common clock implementation. A recent patch removed its use in the clock driver, let's take out the definitions too. Acked-by: Samuel Ortiz <sameo@linux.intel.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/mfd')
-rw-r--r--drivers/mfd/db8500-prcmu.c1
-rw-r--r--drivers/mfd/dbx500-prcmu-regs.h1
2 files changed, 0 insertions, 2 deletions
diff --git a/drivers/mfd/db8500-prcmu.c b/drivers/mfd/db8500-prcmu.c
index 53f371dcbb6e..b9ce60c301de 100644
--- a/drivers/mfd/db8500-prcmu.c
+++ b/drivers/mfd/db8500-prcmu.c
@@ -480,7 +480,6 @@ static struct clk_mgt clk_mgt[PRCMU_NUM_REG_CLOCKS] = {
480 CLK_MGT_ENTRY(PER6CLK, PLL_DIV, true), 480 CLK_MGT_ENTRY(PER6CLK, PLL_DIV, true),
481 CLK_MGT_ENTRY(PER7CLK, PLL_DIV, true), 481 CLK_MGT_ENTRY(PER7CLK, PLL_DIV, true),
482 CLK_MGT_ENTRY(LCDCLK, PLL_FIX, true), 482 CLK_MGT_ENTRY(LCDCLK, PLL_FIX, true),
483 CLK_MGT_ENTRY(BML8580CLK, PLL_DIV, true),
484 CLK_MGT_ENTRY(BMLCLK, PLL_DIV, true), 483 CLK_MGT_ENTRY(BMLCLK, PLL_DIV, true),
485 CLK_MGT_ENTRY(HSITXCLK, PLL_DIV, true), 484 CLK_MGT_ENTRY(HSITXCLK, PLL_DIV, true),
486 CLK_MGT_ENTRY(HSIRXCLK, PLL_DIV, true), 485 CLK_MGT_ENTRY(HSIRXCLK, PLL_DIV, true),
diff --git a/drivers/mfd/dbx500-prcmu-regs.h b/drivers/mfd/dbx500-prcmu-regs.h
index 4f6f0fa5d3b7..7cc32a8ff01c 100644
--- a/drivers/mfd/dbx500-prcmu-regs.h
+++ b/drivers/mfd/dbx500-prcmu-regs.h
@@ -32,7 +32,6 @@
32#define PRCM_PER7CLK_MGT (0x040) 32#define PRCM_PER7CLK_MGT (0x040)
33#define PRCM_LCDCLK_MGT (0x044) 33#define PRCM_LCDCLK_MGT (0x044)
34#define PRCM_BMLCLK_MGT (0x04C) 34#define PRCM_BMLCLK_MGT (0x04C)
35#define PRCM_BML8580CLK_MGT (0x108)
36#define PRCM_HSITXCLK_MGT (0x050) 35#define PRCM_HSITXCLK_MGT (0x050)
37#define PRCM_HSIRXCLK_MGT (0x054) 36#define PRCM_HSIRXCLK_MGT (0x054)
38#define PRCM_HDMICLK_MGT (0x058) 37#define PRCM_HDMICLK_MGT (0x058)