diff options
author | Mauro Carvalho Chehab <m.chehab@samsung.com> | 2014-07-04 13:15:34 -0400 |
---|---|---|
committer | Mauro Carvalho Chehab <m.chehab@samsung.com> | 2014-07-07 08:56:37 -0400 |
commit | 40d1a7c3ded03347336fbd33234af89aaf5ffdca (patch) | |
tree | bf799c3fc489adf9cd32fef4ba639109e42b5d7c /drivers/media/usb/dvb-usb/dib0700_devices.c | |
parent | 6d38454a59a01ce24f93c990a08cac0c0d4df2c8 (diff) |
[media] dib0700: better document struct init
Instead of using anonymous initialization for dib0896 structs,
identify each field by name. That helps to understand what's
being initialized.
No functional changes.
Acked-By: Patrick Boettcher <pboettcher@kernellabs.com>
Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>
Diffstat (limited to 'drivers/media/usb/dvb-usb/dib0700_devices.c')
-rw-r--r-- | drivers/media/usb/dvb-usb/dib0700_devices.c | 148 |
1 files changed, 81 insertions, 67 deletions
diff --git a/drivers/media/usb/dvb-usb/dib0700_devices.c b/drivers/media/usb/dvb-usb/dib0700_devices.c index d067bb77534f..501947eaacfe 100644 --- a/drivers/media/usb/dvb-usb/dib0700_devices.c +++ b/drivers/media/usb/dvb-usb/dib0700_devices.c | |||
@@ -1412,99 +1412,113 @@ static int stk807xpvr_frontend_attach1(struct dvb_usb_adapter *adap) | |||
1412 | /* STK8096GP */ | 1412 | /* STK8096GP */ |
1413 | static struct dibx000_agc_config dib8090_agc_config[2] = { | 1413 | static struct dibx000_agc_config dib8090_agc_config[2] = { |
1414 | { | 1414 | { |
1415 | BAND_UHF | BAND_VHF | BAND_LBAND | BAND_SBAND, | 1415 | .band_caps = BAND_UHF | BAND_VHF | BAND_LBAND | BAND_SBAND, |
1416 | /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=1, | 1416 | /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=1, |
1417 | * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0, P_agc_inh_dc_rv_est=0, | 1417 | * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0, P_agc_inh_dc_rv_est=0, |
1418 | * P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=5, P_agc_write=0 */ | 1418 | * P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=5, P_agc_write=0 */ |
1419 | (0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) | (0 << 8) | 1419 | .setup = (0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) | (0 << 8) |
1420 | | (3 << 5) | (0 << 4) | (5 << 1) | (0 << 0), | 1420 | | (3 << 5) | (0 << 4) | (5 << 1) | (0 << 0), |
1421 | 1421 | ||
1422 | 787, | 1422 | .inv_gain = 787, |
1423 | 10, | 1423 | .time_stabiliz = 10, |
1424 | 1424 | ||
1425 | 0, | 1425 | .alpha_level = 0, |
1426 | 118, | 1426 | .thlock = 118, |
1427 | 1427 | ||
1428 | 0, | 1428 | .wbd_inv = 0, |
1429 | 3530, | 1429 | .wbd_ref = 3530, |
1430 | 1, | 1430 | .wbd_sel = 1, |
1431 | 5, | 1431 | .wbd_alpha = 5, |
1432 | 1432 | ||
1433 | 65535, | 1433 | .agc1_max = 65535, |
1434 | 0, | 1434 | .agc1_min = 0, |
1435 | 1435 | ||
1436 | 65535, | 1436 | .agc2_max = 65535, |
1437 | 0, | 1437 | .agc2_min = 0, |
1438 | |||
1439 | 0, | ||
1440 | 32, | ||
1441 | 114, | ||
1442 | 143, | ||
1443 | 144, | ||
1444 | 114, | ||
1445 | 227, | ||
1446 | 116, | ||
1447 | 117, | ||
1448 | |||
1449 | 28, | ||
1450 | 26, | ||
1451 | 31, | ||
1452 | 51, | ||
1453 | 1438 | ||
1454 | 0, | 1439 | .agc1_pt1 = 0, |
1440 | .agc1_pt2 = 32, | ||
1441 | .agc1_pt3 = 114, | ||
1442 | .agc1_slope1 = 143, | ||
1443 | .agc1_slope2 = 144, | ||
1444 | .agc2_pt1 = 114, | ||
1445 | .agc2_pt2 = 227, | ||
1446 | .agc2_slope1 = 116, | ||
1447 | .agc2_slope2 = 117, | ||
1448 | |||
1449 | .alpha_mant = 28, | ||
1450 | .alpha_exp = 26, | ||
1451 | .beta_mant = 31, | ||
1452 | .beta_exp = 51, | ||
1453 | |||
1454 | .perform_agc_softsplit = 0, | ||
1455 | }, | 1455 | }, |
1456 | { | 1456 | { |
1457 | BAND_CBAND, | 1457 | .band_caps = BAND_CBAND, |
1458 | /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=1, | 1458 | /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=1, |
1459 | * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0, P_agc_inh_dc_rv_est=0, | 1459 | * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0, P_agc_inh_dc_rv_est=0, |
1460 | * P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=5, P_agc_write=0 */ | 1460 | * P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=5, P_agc_write=0 */ |
1461 | (0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) | (0 << 8) | 1461 | .setup = (0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) | (0 << 8) |
1462 | | (3 << 5) | (0 << 4) | (5 << 1) | (0 << 0), | 1462 | | (3 << 5) | (0 << 4) | (5 << 1) | (0 << 0), |
1463 | 1463 | ||
1464 | 787, | 1464 | .inv_gain = 787, |
1465 | 10, | 1465 | .time_stabiliz = 10, |
1466 | 1466 | ||
1467 | 0, | 1467 | .alpha_level = 0, |
1468 | 118, | 1468 | .thlock = 118, |
1469 | 1469 | ||
1470 | 0, | 1470 | .wbd_inv = 0, |
1471 | 3530, | 1471 | .wbd_ref = 3530, |
1472 | 1, | 1472 | .wbd_sel = 1, |
1473 | 5, | 1473 | .wbd_alpha = 5, |
1474 | |||
1475 | 0, | ||
1476 | 0, | ||
1477 | |||
1478 | 65535, | ||
1479 | 0, | ||
1480 | 1474 | ||
1481 | 0, | 1475 | .agc1_max = 0, |
1482 | 32, | 1476 | .agc1_min = 0, |
1483 | 114, | ||
1484 | 143, | ||
1485 | 144, | ||
1486 | 114, | ||
1487 | 227, | ||
1488 | 116, | ||
1489 | 117, | ||
1490 | 1477 | ||
1491 | 28, | 1478 | .agc2_max = 65535, |
1492 | 26, | 1479 | .agc2_min = 0, |
1493 | 31, | ||
1494 | 51, | ||
1495 | 1480 | ||
1496 | 0, | 1481 | .agc1_pt1 = 0, |
1482 | .agc1_pt2 = 32, | ||
1483 | .agc1_pt3 = 114, | ||
1484 | .agc1_slope1 = 143, | ||
1485 | .agc1_slope2 = 144, | ||
1486 | .agc2_pt1 = 114, | ||
1487 | .agc2_pt2 = 227, | ||
1488 | .agc2_slope1 = 116, | ||
1489 | .agc2_slope2 = 117, | ||
1490 | |||
1491 | .alpha_mant = 28, | ||
1492 | .alpha_exp = 26, | ||
1493 | .beta_mant = 31, | ||
1494 | .beta_exp = 51, | ||
1495 | |||
1496 | .perform_agc_softsplit = 0, | ||
1497 | } | 1497 | } |
1498 | }; | 1498 | }; |
1499 | 1499 | ||
1500 | static struct dibx000_bandwidth_config dib8090_pll_config_12mhz = { | 1500 | static struct dibx000_bandwidth_config dib8090_pll_config_12mhz = { |
1501 | 54000, 13500, | 1501 | .internal = 54000, |
1502 | 1, 18, 3, 1, 0, | 1502 | .sampling = 13500, |
1503 | 0, 0, 1, 1, 2, | 1503 | |
1504 | (3 << 14) | (1 << 12) | (599 << 0), | 1504 | .pll_prediv = 1, |
1505 | (0 << 25) | 0, | 1505 | .pll_ratio = 18, |
1506 | 20199727, | 1506 | .pll_range = 3, |
1507 | 12000000, | 1507 | .pll_reset = 1, |
1508 | .pll_bypass = 0, | ||
1509 | |||
1510 | .enable_refdiv = 0, | ||
1511 | .bypclk_div = 0, | ||
1512 | .IO_CLK_en_core = 1, | ||
1513 | .ADClkSrc = 1, | ||
1514 | .modulo = 2, | ||
1515 | |||
1516 | .sad_cfg = (3 << 14) | (1 << 12) | (599 << 0), | ||
1517 | |||
1518 | .ifreq = (0 << 25) | 0, | ||
1519 | .timf = 20199727, | ||
1520 | |||
1521 | .xtal_hz = 12000000, | ||
1508 | }; | 1522 | }; |
1509 | 1523 | ||
1510 | static int dib8090_get_adc_power(struct dvb_frontend *fe) | 1524 | static int dib8090_get_adc_power(struct dvb_frontend *fe) |