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authorRussell King <rmk+kernel@arm.linux.org.uk>2015-07-27 08:29:46 -0400
committerThierry Reding <treding@nvidia.com>2015-08-13 10:06:41 -0400
commitd62c7a886c2bc9f9258164814245dc0678b9a52e (patch)
tree02d61bd03b2fc7ed228dc76cb1306ed10427f050 /drivers/iommu
parentb8fe03827b192a23d04e99c40d72e6b938fa6576 (diff)
iommu/tegra-smmu: smmu_flush_ptc() wants device addresses
Pass smmu_flush_ptc() the device address rather than struct page pointer. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/iommu')
-rw-r--r--drivers/iommu/tegra-smmu.c11
1 files changed, 5 insertions, 6 deletions
diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c
index 5c775b70ef8c..f420d8718535 100644
--- a/drivers/iommu/tegra-smmu.c
+++ b/drivers/iommu/tegra-smmu.c
@@ -170,10 +170,9 @@ static void smmu_flush_ptc_all(struct tegra_smmu *smmu)
170 smmu_writel(smmu, SMMU_PTC_FLUSH_TYPE_ALL, SMMU_PTC_FLUSH); 170 smmu_writel(smmu, SMMU_PTC_FLUSH_TYPE_ALL, SMMU_PTC_FLUSH);
171} 171}
172 172
173static inline void smmu_flush_ptc(struct tegra_smmu *smmu, struct page *page, 173static inline void smmu_flush_ptc(struct tegra_smmu *smmu, phys_addr_t phys,
174 unsigned long offset) 174 unsigned long offset)
175{ 175{
176 phys_addr_t phys = page_to_phys(page);
177 u32 value; 176 u32 value;
178 177
179 offset &= ~(smmu->mc->soc->atom_size - 1); 178 offset &= ~(smmu->mc->soc->atom_size - 1);
@@ -413,7 +412,7 @@ static int tegra_smmu_as_prepare(struct tegra_smmu *smmu,
413 return err; 412 return err;
414 413
415 smmu_flush_dcache(as->pd, 0, SMMU_SIZE_PD); 414 smmu_flush_dcache(as->pd, 0, SMMU_SIZE_PD);
416 smmu_flush_ptc(smmu, as->pd, 0); 415 smmu_flush_ptc(smmu, page_to_phys(as->pd), 0);
417 smmu_flush_tlb_asid(smmu, as->id); 416 smmu_flush_tlb_asid(smmu, as->id);
418 417
419 smmu_writel(smmu, as->id & 0x7f, SMMU_PTB_ASID); 418 smmu_writel(smmu, as->id & 0x7f, SMMU_PTB_ASID);
@@ -546,7 +545,7 @@ static u32 *as_get_pte(struct tegra_smmu_as *as, dma_addr_t iova,
546 pd[pde] = SMMU_MK_PDE(page, SMMU_PDE_ATTR | SMMU_PDE_NEXT); 545 pd[pde] = SMMU_MK_PDE(page, SMMU_PDE_ATTR | SMMU_PDE_NEXT);
547 546
548 smmu_flush_dcache(as->pd, pde << 2, 4); 547 smmu_flush_dcache(as->pd, pde << 2, 4);
549 smmu_flush_ptc(smmu, as->pd, pde << 2); 548 smmu_flush_ptc(smmu, page_to_phys(as->pd), pde << 2);
550 smmu_flush_tlb_section(smmu, as->id, iova); 549 smmu_flush_tlb_section(smmu, as->id, iova);
551 smmu_flush(smmu); 550 smmu_flush(smmu);
552 } else { 551 } else {
@@ -583,7 +582,7 @@ static void tegra_smmu_pte_put_use(struct tegra_smmu_as *as, unsigned long iova)
583 582
584 /* Flush the page directory entry */ 583 /* Flush the page directory entry */
585 smmu_flush_dcache(as->pd, offset, sizeof(*pd)); 584 smmu_flush_dcache(as->pd, offset, sizeof(*pd));
586 smmu_flush_ptc(smmu, as->pd, offset); 585 smmu_flush_ptc(smmu, page_to_phys(as->pd), offset);
587 smmu_flush_tlb_section(smmu, as->id, iova); 586 smmu_flush_tlb_section(smmu, as->id, iova);
588 smmu_flush(smmu); 587 smmu_flush(smmu);
589 588
@@ -603,7 +602,7 @@ static void tegra_smmu_set_pte(struct tegra_smmu_as *as, unsigned long iova,
603 *pte = val; 602 *pte = val;
604 603
605 smmu_flush_dcache(pte_page, offset, 4); 604 smmu_flush_dcache(pte_page, offset, 4);
606 smmu_flush_ptc(smmu, pte_page, offset); 605 smmu_flush_ptc(smmu, page_to_phys(pte_page), offset);
607 smmu_flush_tlb_group(smmu, as->id, iova); 606 smmu_flush_tlb_group(smmu, as->id, iova);
608 smmu_flush(smmu); 607 smmu_flush(smmu);
609} 608}