diff options
author | Andrew F. Davis <afd@ti.com> | 2016-05-01 16:36:59 -0400 |
---|---|---|
committer | Jonathan Cameron <jic23@kernel.org> | 2016-05-04 06:10:38 -0400 |
commit | b36e8257641a043764c62240316610c81e36376c (patch) | |
tree | 6739afa1b341288ca45c8484b8c8d9eb7fb9554c /drivers/iio | |
parent | 24b9dea764bdf0de8434fb4567e7f62038ba869e (diff) |
iio: health/afe440x: Use regmap fields
These drivers can use regmap fields to access fields in registers, this
allows us to remove some macros/defines and simplify code, do this here.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
Diffstat (limited to 'drivers/iio')
-rw-r--r-- | drivers/iio/health/afe4403.c | 118 | ||||
-rw-r--r-- | drivers/iio/health/afe4404.c | 156 | ||||
-rw-r--r-- | drivers/iio/health/afe440x.h | 25 |
3 files changed, 144 insertions, 155 deletions
diff --git a/drivers/iio/health/afe4403.c b/drivers/iio/health/afe4403.c index 4a580646f10e..19501550c6ff 100644 --- a/drivers/iio/health/afe4403.c +++ b/drivers/iio/health/afe4403.c | |||
@@ -39,32 +39,6 @@ | |||
39 | #define AFE4403_TIAGAIN 0x20 | 39 | #define AFE4403_TIAGAIN 0x20 |
40 | #define AFE4403_TIA_AMB_GAIN 0x21 | 40 | #define AFE4403_TIA_AMB_GAIN 0x21 |
41 | 41 | ||
42 | /* AFE4403 GAIN register fields */ | ||
43 | #define AFE4403_TIAGAIN_RES_MASK GENMASK(2, 0) | ||
44 | #define AFE4403_TIAGAIN_RES_SHIFT 0 | ||
45 | #define AFE4403_TIAGAIN_CAP_MASK GENMASK(7, 3) | ||
46 | #define AFE4403_TIAGAIN_CAP_SHIFT 3 | ||
47 | |||
48 | /* AFE4403 LEDCNTRL register fields */ | ||
49 | #define AFE440X_LEDCNTRL_LED1_MASK GENMASK(15, 8) | ||
50 | #define AFE440X_LEDCNTRL_LED1_SHIFT 8 | ||
51 | #define AFE440X_LEDCNTRL_LED2_MASK GENMASK(7, 0) | ||
52 | #define AFE440X_LEDCNTRL_LED2_SHIFT 0 | ||
53 | #define AFE440X_LEDCNTRL_LED_RANGE_MASK GENMASK(17, 16) | ||
54 | #define AFE440X_LEDCNTRL_LED_RANGE_SHIFT 16 | ||
55 | |||
56 | /* AFE4403 CONTROL2 register fields */ | ||
57 | #define AFE440X_CONTROL2_PWR_DWN_TX BIT(2) | ||
58 | #define AFE440X_CONTROL2_EN_SLOW_DIAG BIT(8) | ||
59 | #define AFE440X_CONTROL2_DIAG_OUT_TRI BIT(10) | ||
60 | #define AFE440X_CONTROL2_TX_BRDG_MOD BIT(11) | ||
61 | #define AFE440X_CONTROL2_TX_REF_MASK GENMASK(18, 17) | ||
62 | #define AFE440X_CONTROL2_TX_REF_SHIFT 17 | ||
63 | |||
64 | /* AFE4404 NULL fields */ | ||
65 | #define NULL_MASK 0 | ||
66 | #define NULL_SHIFT 0 | ||
67 | |||
68 | /* AFE4403 LEDCNTRL values */ | 42 | /* AFE4403 LEDCNTRL values */ |
69 | #define AFE440X_LEDCNTRL_RANGE_TX_HALF 0x1 | 43 | #define AFE440X_LEDCNTRL_RANGE_TX_HALF 0x1 |
70 | #define AFE440X_LEDCNTRL_RANGE_TX_FULL 0x2 | 44 | #define AFE440X_LEDCNTRL_RANGE_TX_FULL 0x2 |
@@ -102,11 +76,35 @@ | |||
102 | #define AFE4403_TIAGAIN_RES_1_M 0x6 | 76 | #define AFE4403_TIAGAIN_RES_1_M 0x6 |
103 | #define AFE4403_TIAGAIN_RES_NONE 0x7 | 77 | #define AFE4403_TIAGAIN_RES_NONE 0x7 |
104 | 78 | ||
79 | enum afe4403_fields { | ||
80 | /* Gains */ | ||
81 | F_RF_LED1, F_CF_LED1, | ||
82 | F_RF_LED, F_CF_LED, | ||
83 | |||
84 | /* LED Current */ | ||
85 | F_ILED1, F_ILED2, | ||
86 | |||
87 | /* sentinel */ | ||
88 | F_MAX_FIELDS | ||
89 | }; | ||
90 | |||
91 | static const struct reg_field afe4403_reg_fields[] = { | ||
92 | /* Gains */ | ||
93 | [F_RF_LED1] = REG_FIELD(AFE4403_TIAGAIN, 0, 2), | ||
94 | [F_CF_LED1] = REG_FIELD(AFE4403_TIAGAIN, 3, 7), | ||
95 | [F_RF_LED] = REG_FIELD(AFE4403_TIA_AMB_GAIN, 0, 2), | ||
96 | [F_CF_LED] = REG_FIELD(AFE4403_TIA_AMB_GAIN, 3, 7), | ||
97 | /* LED Current */ | ||
98 | [F_ILED1] = REG_FIELD(AFE440X_LEDCNTRL, 0, 7), | ||
99 | [F_ILED2] = REG_FIELD(AFE440X_LEDCNTRL, 8, 15), | ||
100 | }; | ||
101 | |||
105 | /** | 102 | /** |
106 | * struct afe4403_data - AFE4403 device instance data | 103 | * struct afe4403_data - AFE4403 device instance data |
107 | * @dev: Device structure | 104 | * @dev: Device structure |
108 | * @spi: SPI device handle | 105 | * @spi: SPI device handle |
109 | * @regmap: Register map of the device | 106 | * @regmap: Register map of the device |
107 | * @fields: Register fields of the device | ||
110 | * @regulator: Pointer to the regulator for the IC | 108 | * @regulator: Pointer to the regulator for the IC |
111 | * @trig: IIO trigger for this device | 109 | * @trig: IIO trigger for this device |
112 | * @irq: ADC_RDY line interrupt number | 110 | * @irq: ADC_RDY line interrupt number |
@@ -115,6 +113,7 @@ struct afe4403_data { | |||
115 | struct device *dev; | 113 | struct device *dev; |
116 | struct spi_device *spi; | 114 | struct spi_device *spi; |
117 | struct regmap *regmap; | 115 | struct regmap *regmap; |
116 | struct regmap_field *fields[F_MAX_FIELDS]; | ||
118 | struct regulator *regulator; | 117 | struct regulator *regulator; |
119 | struct iio_trigger *trig; | 118 | struct iio_trigger *trig; |
120 | int irq; | 119 | int irq; |
@@ -131,15 +130,18 @@ enum afe4403_chan_id { | |||
131 | ILED2, | 130 | ILED2, |
132 | }; | 131 | }; |
133 | 132 | ||
134 | static const struct afe440x_reg_info afe4403_reg_info[] = { | 133 | static const unsigned int afe4403_channel_values[] = { |
135 | [LED2] = AFE440X_REG_INFO(AFE440X_LED2VAL, 0, NULL), | 134 | [LED2] = AFE440X_LED2VAL, |
136 | [ALED2] = AFE440X_REG_INFO(AFE440X_ALED2VAL, 0, NULL), | 135 | [ALED2] = AFE440X_ALED2VAL, |
137 | [LED1] = AFE440X_REG_INFO(AFE440X_LED1VAL, 0, NULL), | 136 | [LED1] = AFE440X_LED1VAL, |
138 | [ALED1] = AFE440X_REG_INFO(AFE440X_ALED1VAL, 0, NULL), | 137 | [ALED1] = AFE440X_ALED1VAL, |
139 | [LED2_ALED2] = AFE440X_REG_INFO(AFE440X_LED2_ALED2VAL, 0, NULL), | 138 | [LED2_ALED2] = AFE440X_LED2_ALED2VAL, |
140 | [LED1_ALED1] = AFE440X_REG_INFO(AFE440X_LED1_ALED1VAL, 0, NULL), | 139 | [LED1_ALED1] = AFE440X_LED1_ALED1VAL, |
141 | [ILED1] = AFE440X_REG_INFO(AFE440X_LEDCNTRL, 0, AFE440X_LEDCNTRL_LED1), | 140 | }; |
142 | [ILED2] = AFE440X_REG_INFO(AFE440X_LEDCNTRL, 0, AFE440X_LEDCNTRL_LED2), | 141 | |
142 | static const unsigned int afe4403_channel_leds[] = { | ||
143 | [ILED1] = F_ILED1, | ||
144 | [ILED2] = F_ILED2, | ||
143 | }; | 145 | }; |
144 | 146 | ||
145 | static const struct iio_chan_spec afe4403_channels[] = { | 147 | static const struct iio_chan_spec afe4403_channels[] = { |
@@ -184,13 +186,10 @@ static ssize_t afe440x_show_register(struct device *dev, | |||
184 | int vals[2]; | 186 | int vals[2]; |
185 | int ret; | 187 | int ret; |
186 | 188 | ||
187 | ret = regmap_read(afe->regmap, afe440x_attr->reg, ®_val); | 189 | ret = regmap_field_read(afe->fields[afe440x_attr->field], ®_val); |
188 | if (ret) | 190 | if (ret) |
189 | return ret; | 191 | return ret; |
190 | 192 | ||
191 | reg_val &= afe440x_attr->mask; | ||
192 | reg_val >>= afe440x_attr->shift; | ||
193 | |||
194 | if (reg_val >= afe440x_attr->table_size) | 193 | if (reg_val >= afe440x_attr->table_size) |
195 | return -EINVAL; | 194 | return -EINVAL; |
196 | 195 | ||
@@ -220,20 +219,18 @@ static ssize_t afe440x_store_register(struct device *dev, | |||
220 | if (val == afe440x_attr->table_size) | 219 | if (val == afe440x_attr->table_size) |
221 | return -EINVAL; | 220 | return -EINVAL; |
222 | 221 | ||
223 | ret = regmap_update_bits(afe->regmap, afe440x_attr->reg, | 222 | ret = regmap_field_write(afe->fields[afe440x_attr->field], val); |
224 | afe440x_attr->mask, | ||
225 | (val << afe440x_attr->shift)); | ||
226 | if (ret) | 223 | if (ret) |
227 | return ret; | 224 | return ret; |
228 | 225 | ||
229 | return count; | 226 | return count; |
230 | } | 227 | } |
231 | 228 | ||
232 | static AFE440X_ATTR(tia_resistance1, AFE4403_TIAGAIN, AFE4403_TIAGAIN_RES, afe4403_res_table); | 229 | static AFE440X_ATTR(tia_resistance1, F_RF_LED1, afe4403_res_table); |
233 | static AFE440X_ATTR(tia_capacitance1, AFE4403_TIAGAIN, AFE4403_TIAGAIN_CAP, afe4403_cap_table); | 230 | static AFE440X_ATTR(tia_capacitance1, F_CF_LED1, afe4403_cap_table); |
234 | 231 | ||
235 | static AFE440X_ATTR(tia_resistance2, AFE4403_TIA_AMB_GAIN, AFE4403_TIAGAIN_RES, afe4403_res_table); | 232 | static AFE440X_ATTR(tia_resistance2, F_RF_LED, afe4403_res_table); |
236 | static AFE440X_ATTR(tia_capacitance2, AFE4403_TIA_AMB_GAIN, AFE4403_TIAGAIN_RES, afe4403_cap_table); | 233 | static AFE440X_ATTR(tia_capacitance2, F_CF_LED, afe4403_cap_table); |
237 | 234 | ||
238 | static struct attribute *afe440x_attributes[] = { | 235 | static struct attribute *afe440x_attributes[] = { |
239 | &afe440x_attr_tia_resistance1.dev_attr.attr, | 236 | &afe440x_attr_tia_resistance1.dev_attr.attr, |
@@ -282,14 +279,15 @@ static int afe4403_read_raw(struct iio_dev *indio_dev, | |||
282 | int *val, int *val2, long mask) | 279 | int *val, int *val2, long mask) |
283 | { | 280 | { |
284 | struct afe4403_data *afe = iio_priv(indio_dev); | 281 | struct afe4403_data *afe = iio_priv(indio_dev); |
285 | const struct afe440x_reg_info reg_info = afe4403_reg_info[chan->address]; | 282 | unsigned int reg = afe4403_channel_values[chan->address]; |
283 | unsigned int field = afe4403_channel_leds[chan->address]; | ||
286 | int ret; | 284 | int ret; |
287 | 285 | ||
288 | switch (chan->type) { | 286 | switch (chan->type) { |
289 | case IIO_INTENSITY: | 287 | case IIO_INTENSITY: |
290 | switch (mask) { | 288 | switch (mask) { |
291 | case IIO_CHAN_INFO_RAW: | 289 | case IIO_CHAN_INFO_RAW: |
292 | ret = afe4403_read(afe, reg_info.reg, val); | 290 | ret = afe4403_read(afe, reg, val); |
293 | if (ret) | 291 | if (ret) |
294 | return ret; | 292 | return ret; |
295 | return IIO_VAL_INT; | 293 | return IIO_VAL_INT; |
@@ -298,11 +296,9 @@ static int afe4403_read_raw(struct iio_dev *indio_dev, | |||
298 | case IIO_CURRENT: | 296 | case IIO_CURRENT: |
299 | switch (mask) { | 297 | switch (mask) { |
300 | case IIO_CHAN_INFO_RAW: | 298 | case IIO_CHAN_INFO_RAW: |
301 | ret = regmap_read(afe->regmap, reg_info.reg, val); | 299 | ret = regmap_field_read(afe->fields[field], val); |
302 | if (ret) | 300 | if (ret) |
303 | return ret; | 301 | return ret; |
304 | *val &= reg_info.mask; | ||
305 | *val >>= reg_info.shift; | ||
306 | return IIO_VAL_INT; | 302 | return IIO_VAL_INT; |
307 | case IIO_CHAN_INFO_SCALE: | 303 | case IIO_CHAN_INFO_SCALE: |
308 | *val = 0; | 304 | *val = 0; |
@@ -322,16 +318,13 @@ static int afe4403_write_raw(struct iio_dev *indio_dev, | |||
322 | int val, int val2, long mask) | 318 | int val, int val2, long mask) |
323 | { | 319 | { |
324 | struct afe4403_data *afe = iio_priv(indio_dev); | 320 | struct afe4403_data *afe = iio_priv(indio_dev); |
325 | const struct afe440x_reg_info reg_info = afe4403_reg_info[chan->address]; | 321 | unsigned int field = afe4403_channel_leds[chan->address]; |
326 | 322 | ||
327 | switch (chan->type) { | 323 | switch (chan->type) { |
328 | case IIO_CURRENT: | 324 | case IIO_CURRENT: |
329 | switch (mask) { | 325 | switch (mask) { |
330 | case IIO_CHAN_INFO_RAW: | 326 | case IIO_CHAN_INFO_RAW: |
331 | return regmap_update_bits(afe->regmap, | 327 | return regmap_field_write(afe->fields[field], val); |
332 | reg_info.reg, | ||
333 | reg_info.mask, | ||
334 | (val << reg_info.shift)); | ||
335 | } | 328 | } |
336 | break; | 329 | break; |
337 | default: | 330 | default: |
@@ -366,7 +359,7 @@ static irqreturn_t afe4403_trigger_handler(int irq, void *private) | |||
366 | for_each_set_bit(bit, indio_dev->active_scan_mask, | 359 | for_each_set_bit(bit, indio_dev->active_scan_mask, |
367 | indio_dev->masklength) { | 360 | indio_dev->masklength) { |
368 | ret = spi_write_then_read(afe->spi, | 361 | ret = spi_write_then_read(afe->spi, |
369 | &afe4403_reg_info[bit].reg, 1, | 362 | &afe4403_channel_values[bit], 1, |
370 | rx, 3); | 363 | rx, 3); |
371 | if (ret) | 364 | if (ret) |
372 | goto err; | 365 | goto err; |
@@ -503,7 +496,7 @@ static int afe4403_probe(struct spi_device *spi) | |||
503 | { | 496 | { |
504 | struct iio_dev *indio_dev; | 497 | struct iio_dev *indio_dev; |
505 | struct afe4403_data *afe; | 498 | struct afe4403_data *afe; |
506 | int ret; | 499 | int i, ret; |
507 | 500 | ||
508 | indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*afe)); | 501 | indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*afe)); |
509 | if (!indio_dev) | 502 | if (!indio_dev) |
@@ -522,6 +515,15 @@ static int afe4403_probe(struct spi_device *spi) | |||
522 | return PTR_ERR(afe->regmap); | 515 | return PTR_ERR(afe->regmap); |
523 | } | 516 | } |
524 | 517 | ||
518 | for (i = 0; i < F_MAX_FIELDS; i++) { | ||
519 | afe->fields[i] = devm_regmap_field_alloc(afe->dev, afe->regmap, | ||
520 | afe4403_reg_fields[i]); | ||
521 | if (IS_ERR(afe->fields[i])) { | ||
522 | dev_err(afe->dev, "Unable to allocate regmap fields\n"); | ||
523 | return PTR_ERR(afe->fields[i]); | ||
524 | } | ||
525 | } | ||
526 | |||
525 | afe->regulator = devm_regulator_get(afe->dev, "tx_sup"); | 527 | afe->regulator = devm_regulator_get(afe->dev, "tx_sup"); |
526 | if (IS_ERR(afe->regulator)) { | 528 | if (IS_ERR(afe->regulator)) { |
527 | dev_err(afe->dev, "Unable to get regulator\n"); | 529 | dev_err(afe->dev, "Unable to get regulator\n"); |
diff --git a/drivers/iio/health/afe4404.c b/drivers/iio/health/afe4404.c index 7806a452edf8..0d1af4a4a903 100644 --- a/drivers/iio/health/afe4404.c +++ b/drivers/iio/health/afe4404.c | |||
@@ -48,43 +48,9 @@ | |||
48 | #define AFE4404_AVG_LED2_ALED2VAL 0x3f | 48 | #define AFE4404_AVG_LED2_ALED2VAL 0x3f |
49 | #define AFE4404_AVG_LED1_ALED1VAL 0x40 | 49 | #define AFE4404_AVG_LED1_ALED1VAL 0x40 |
50 | 50 | ||
51 | /* AFE4404 GAIN register fields */ | ||
52 | #define AFE4404_TIA_GAIN_RES_MASK GENMASK(2, 0) | ||
53 | #define AFE4404_TIA_GAIN_RES_SHIFT 0 | ||
54 | #define AFE4404_TIA_GAIN_CAP_MASK GENMASK(5, 3) | ||
55 | #define AFE4404_TIA_GAIN_CAP_SHIFT 3 | ||
56 | |||
57 | /* AFE4404 LEDCNTRL register fields */ | ||
58 | #define AFE4404_LEDCNTRL_ILED1_MASK GENMASK(5, 0) | ||
59 | #define AFE4404_LEDCNTRL_ILED1_SHIFT 0 | ||
60 | #define AFE4404_LEDCNTRL_ILED2_MASK GENMASK(11, 6) | ||
61 | #define AFE4404_LEDCNTRL_ILED2_SHIFT 6 | ||
62 | #define AFE4404_LEDCNTRL_ILED3_MASK GENMASK(17, 12) | ||
63 | #define AFE4404_LEDCNTRL_ILED3_SHIFT 12 | ||
64 | |||
65 | /* AFE4404 CONTROL2 register fields */ | ||
66 | #define AFE440X_CONTROL2_ILED_2X_MASK BIT(17) | ||
67 | #define AFE440X_CONTROL2_ILED_2X_SHIFT 17 | ||
68 | |||
69 | /* AFE4404 CONTROL3 register fields */ | 51 | /* AFE4404 CONTROL3 register fields */ |
70 | #define AFE440X_CONTROL3_OSC_ENABLE BIT(9) | 52 | #define AFE440X_CONTROL3_OSC_ENABLE BIT(9) |
71 | 53 | ||
72 | /* AFE4404 OFFDAC register current fields */ | ||
73 | #define AFE4404_OFFDAC_CURR_LED1_MASK GENMASK(9, 5) | ||
74 | #define AFE4404_OFFDAC_CURR_LED1_SHIFT 5 | ||
75 | #define AFE4404_OFFDAC_CURR_LED2_MASK GENMASK(19, 15) | ||
76 | #define AFE4404_OFFDAC_CURR_LED2_SHIFT 15 | ||
77 | #define AFE4404_OFFDAC_CURR_LED3_MASK GENMASK(4, 0) | ||
78 | #define AFE4404_OFFDAC_CURR_LED3_SHIFT 0 | ||
79 | #define AFE4404_OFFDAC_CURR_ALED1_MASK GENMASK(14, 10) | ||
80 | #define AFE4404_OFFDAC_CURR_ALED1_SHIFT 10 | ||
81 | #define AFE4404_OFFDAC_CURR_ALED2_MASK GENMASK(4, 0) | ||
82 | #define AFE4404_OFFDAC_CURR_ALED2_SHIFT 0 | ||
83 | |||
84 | /* AFE4404 NULL fields */ | ||
85 | #define NULL_MASK 0 | ||
86 | #define NULL_SHIFT 0 | ||
87 | |||
88 | /* AFE4404 TIA_GAIN_CAP values */ | 54 | /* AFE4404 TIA_GAIN_CAP values */ |
89 | #define AFE4404_TIA_GAIN_CAP_5_P 0x0 | 55 | #define AFE4404_TIA_GAIN_CAP_5_P 0x0 |
90 | #define AFE4404_TIA_GAIN_CAP_2_5_P 0x1 | 56 | #define AFE4404_TIA_GAIN_CAP_2_5_P 0x1 |
@@ -105,10 +71,43 @@ | |||
105 | #define AFE4404_TIA_GAIN_RES_1_M 0x6 | 71 | #define AFE4404_TIA_GAIN_RES_1_M 0x6 |
106 | #define AFE4404_TIA_GAIN_RES_2_M 0x7 | 72 | #define AFE4404_TIA_GAIN_RES_2_M 0x7 |
107 | 73 | ||
74 | enum afe4404_fields { | ||
75 | /* Gains */ | ||
76 | F_TIA_GAIN_SEP, F_TIA_CF_SEP, | ||
77 | F_TIA_GAIN, TIA_CF, | ||
78 | |||
79 | /* LED Current */ | ||
80 | F_ILED1, F_ILED2, F_ILED3, | ||
81 | |||
82 | /* Offset DAC */ | ||
83 | F_OFFDAC_AMB2, F_OFFDAC_LED1, F_OFFDAC_AMB1, F_OFFDAC_LED2, | ||
84 | |||
85 | /* sentinel */ | ||
86 | F_MAX_FIELDS | ||
87 | }; | ||
88 | |||
89 | static const struct reg_field afe4404_reg_fields[] = { | ||
90 | /* Gains */ | ||
91 | [F_TIA_GAIN_SEP] = REG_FIELD(AFE4404_TIA_GAIN_SEP, 0, 2), | ||
92 | [F_TIA_CF_SEP] = REG_FIELD(AFE4404_TIA_GAIN_SEP, 3, 5), | ||
93 | [F_TIA_GAIN] = REG_FIELD(AFE4404_TIA_GAIN, 0, 2), | ||
94 | [TIA_CF] = REG_FIELD(AFE4404_TIA_GAIN, 3, 5), | ||
95 | /* LED Current */ | ||
96 | [F_ILED1] = REG_FIELD(AFE440X_LEDCNTRL, 0, 5), | ||
97 | [F_ILED2] = REG_FIELD(AFE440X_LEDCNTRL, 6, 11), | ||
98 | [F_ILED3] = REG_FIELD(AFE440X_LEDCNTRL, 12, 17), | ||
99 | /* Offset DAC */ | ||
100 | [F_OFFDAC_AMB2] = REG_FIELD(AFE4404_OFFDAC, 0, 4), | ||
101 | [F_OFFDAC_LED1] = REG_FIELD(AFE4404_OFFDAC, 5, 9), | ||
102 | [F_OFFDAC_AMB1] = REG_FIELD(AFE4404_OFFDAC, 10, 14), | ||
103 | [F_OFFDAC_LED2] = REG_FIELD(AFE4404_OFFDAC, 15, 19), | ||
104 | }; | ||
105 | |||
108 | /** | 106 | /** |
109 | * struct afe4404_data - AFE4404 device instance data | 107 | * struct afe4404_data - AFE4404 device instance data |
110 | * @dev: Device structure | 108 | * @dev: Device structure |
111 | * @regmap: Register map of the device | 109 | * @regmap: Register map of the device |
110 | * @fields: Register fields of the device | ||
112 | * @regulator: Pointer to the regulator for the IC | 111 | * @regulator: Pointer to the regulator for the IC |
113 | * @trig: IIO trigger for this device | 112 | * @trig: IIO trigger for this device |
114 | * @irq: ADC_RDY line interrupt number | 113 | * @irq: ADC_RDY line interrupt number |
@@ -116,6 +115,7 @@ | |||
116 | struct afe4404_data { | 115 | struct afe4404_data { |
117 | struct device *dev; | 116 | struct device *dev; |
118 | struct regmap *regmap; | 117 | struct regmap *regmap; |
118 | struct regmap_field *fields[F_MAX_FIELDS]; | ||
119 | struct regulator *regulator; | 119 | struct regulator *regulator; |
120 | struct iio_trigger *trig; | 120 | struct iio_trigger *trig; |
121 | int irq; | 121 | int irq; |
@@ -133,16 +133,26 @@ enum afe4404_chan_id { | |||
133 | ILED3, | 133 | ILED3, |
134 | }; | 134 | }; |
135 | 135 | ||
136 | static const struct afe440x_reg_info afe4404_reg_info[] = { | 136 | static const unsigned int afe4404_channel_values[] = { |
137 | [LED2] = AFE440X_REG_INFO(AFE440X_LED2VAL, AFE4404_OFFDAC, AFE4404_OFFDAC_CURR_LED2), | 137 | [LED2] = AFE440X_LED2VAL, |
138 | [ALED2] = AFE440X_REG_INFO(AFE440X_ALED2VAL, AFE4404_OFFDAC, AFE4404_OFFDAC_CURR_ALED2), | 138 | [ALED2] = AFE440X_ALED2VAL, |
139 | [LED1] = AFE440X_REG_INFO(AFE440X_LED1VAL, AFE4404_OFFDAC, AFE4404_OFFDAC_CURR_LED1), | 139 | [LED1] = AFE440X_LED1VAL, |
140 | [ALED1] = AFE440X_REG_INFO(AFE440X_ALED1VAL, AFE4404_OFFDAC, AFE4404_OFFDAC_CURR_ALED1), | 140 | [ALED1] = AFE440X_ALED1VAL, |
141 | [LED2_ALED2] = AFE440X_REG_INFO(AFE440X_LED2_ALED2VAL, 0, NULL), | 141 | [LED2_ALED2] = AFE440X_LED2_ALED2VAL, |
142 | [LED1_ALED1] = AFE440X_REG_INFO(AFE440X_LED1_ALED1VAL, 0, NULL), | 142 | [LED1_ALED1] = AFE440X_LED1_ALED1VAL, |
143 | [ILED1] = AFE440X_REG_INFO(AFE440X_LEDCNTRL, 0, AFE4404_LEDCNTRL_ILED1), | 143 | }; |
144 | [ILED2] = AFE440X_REG_INFO(AFE440X_LEDCNTRL, 0, AFE4404_LEDCNTRL_ILED2), | 144 | |
145 | [ILED3] = AFE440X_REG_INFO(AFE440X_LEDCNTRL, 0, AFE4404_LEDCNTRL_ILED3), | 145 | static const unsigned int afe4404_channel_leds[] = { |
146 | [ILED1] = F_ILED1, | ||
147 | [ILED2] = F_ILED2, | ||
148 | [ILED3] = F_ILED3, | ||
149 | }; | ||
150 | |||
151 | static const unsigned int afe4404_channel_offdacs[] = { | ||
152 | [LED2] = F_OFFDAC_LED2, | ||
153 | [ALED2] = F_OFFDAC_AMB2, | ||
154 | [LED1] = F_OFFDAC_LED1, | ||
155 | [ALED1] = F_OFFDAC_AMB1, | ||
146 | }; | 156 | }; |
147 | 157 | ||
148 | static const struct iio_chan_spec afe4404_channels[] = { | 158 | static const struct iio_chan_spec afe4404_channels[] = { |
@@ -194,13 +204,10 @@ static ssize_t afe440x_show_register(struct device *dev, | |||
194 | int vals[2]; | 204 | int vals[2]; |
195 | int ret; | 205 | int ret; |
196 | 206 | ||
197 | ret = regmap_read(afe->regmap, afe440x_attr->reg, ®_val); | 207 | ret = regmap_field_read(afe->fields[afe440x_attr->field], ®_val); |
198 | if (ret) | 208 | if (ret) |
199 | return ret; | 209 | return ret; |
200 | 210 | ||
201 | reg_val &= afe440x_attr->mask; | ||
202 | reg_val >>= afe440x_attr->shift; | ||
203 | |||
204 | if (reg_val >= afe440x_attr->table_size) | 211 | if (reg_val >= afe440x_attr->table_size) |
205 | return -EINVAL; | 212 | return -EINVAL; |
206 | 213 | ||
@@ -230,20 +237,18 @@ static ssize_t afe440x_store_register(struct device *dev, | |||
230 | if (val == afe440x_attr->table_size) | 237 | if (val == afe440x_attr->table_size) |
231 | return -EINVAL; | 238 | return -EINVAL; |
232 | 239 | ||
233 | ret = regmap_update_bits(afe->regmap, afe440x_attr->reg, | 240 | ret = regmap_field_write(afe->fields[afe440x_attr->field], val); |
234 | afe440x_attr->mask, | ||
235 | (val << afe440x_attr->shift)); | ||
236 | if (ret) | 241 | if (ret) |
237 | return ret; | 242 | return ret; |
238 | 243 | ||
239 | return count; | 244 | return count; |
240 | } | 245 | } |
241 | 246 | ||
242 | static AFE440X_ATTR(tia_resistance1, AFE4404_TIA_GAIN, AFE4404_TIA_GAIN_RES, afe4404_res_table); | 247 | static AFE440X_ATTR(tia_resistance1, F_TIA_GAIN, afe4404_res_table); |
243 | static AFE440X_ATTR(tia_capacitance1, AFE4404_TIA_GAIN, AFE4404_TIA_GAIN_CAP, afe4404_cap_table); | 248 | static AFE440X_ATTR(tia_capacitance1, TIA_CF, afe4404_cap_table); |
244 | 249 | ||
245 | static AFE440X_ATTR(tia_resistance2, AFE4404_TIA_GAIN_SEP, AFE4404_TIA_GAIN_RES, afe4404_res_table); | 250 | static AFE440X_ATTR(tia_resistance2, F_TIA_GAIN_SEP, afe4404_res_table); |
246 | static AFE440X_ATTR(tia_capacitance2, AFE4404_TIA_GAIN_SEP, AFE4404_TIA_GAIN_CAP, afe4404_cap_table); | 251 | static AFE440X_ATTR(tia_capacitance2, F_TIA_CF_SEP, afe4404_cap_table); |
247 | 252 | ||
248 | static struct attribute *afe440x_attributes[] = { | 253 | static struct attribute *afe440x_attributes[] = { |
249 | &afe440x_attr_tia_resistance1.dev_attr.attr, | 254 | &afe440x_attr_tia_resistance1.dev_attr.attr, |
@@ -264,35 +269,32 @@ static int afe4404_read_raw(struct iio_dev *indio_dev, | |||
264 | int *val, int *val2, long mask) | 269 | int *val, int *val2, long mask) |
265 | { | 270 | { |
266 | struct afe4404_data *afe = iio_priv(indio_dev); | 271 | struct afe4404_data *afe = iio_priv(indio_dev); |
267 | const struct afe440x_reg_info reg_info = afe4404_reg_info[chan->address]; | 272 | unsigned int value_reg = afe4404_channel_values[chan->address]; |
273 | unsigned int led_field = afe4404_channel_leds[chan->address]; | ||
274 | unsigned int offdac_field = afe4404_channel_offdacs[chan->address]; | ||
268 | int ret; | 275 | int ret; |
269 | 276 | ||
270 | switch (chan->type) { | 277 | switch (chan->type) { |
271 | case IIO_INTENSITY: | 278 | case IIO_INTENSITY: |
272 | switch (mask) { | 279 | switch (mask) { |
273 | case IIO_CHAN_INFO_RAW: | 280 | case IIO_CHAN_INFO_RAW: |
274 | ret = regmap_read(afe->regmap, reg_info.reg, val); | 281 | ret = regmap_read(afe->regmap, value_reg, val); |
275 | if (ret) | 282 | if (ret) |
276 | return ret; | 283 | return ret; |
277 | return IIO_VAL_INT; | 284 | return IIO_VAL_INT; |
278 | case IIO_CHAN_INFO_OFFSET: | 285 | case IIO_CHAN_INFO_OFFSET: |
279 | ret = regmap_read(afe->regmap, reg_info.offreg, | 286 | ret = regmap_field_read(afe->fields[offdac_field], val); |
280 | val); | ||
281 | if (ret) | 287 | if (ret) |
282 | return ret; | 288 | return ret; |
283 | *val &= reg_info.mask; | ||
284 | *val >>= reg_info.shift; | ||
285 | return IIO_VAL_INT; | 289 | return IIO_VAL_INT; |
286 | } | 290 | } |
287 | break; | 291 | break; |
288 | case IIO_CURRENT: | 292 | case IIO_CURRENT: |
289 | switch (mask) { | 293 | switch (mask) { |
290 | case IIO_CHAN_INFO_RAW: | 294 | case IIO_CHAN_INFO_RAW: |
291 | ret = regmap_read(afe->regmap, reg_info.reg, val); | 295 | ret = regmap_field_read(afe->fields[led_field], val); |
292 | if (ret) | 296 | if (ret) |
293 | return ret; | 297 | return ret; |
294 | *val &= reg_info.mask; | ||
295 | *val >>= reg_info.shift; | ||
296 | return IIO_VAL_INT; | 298 | return IIO_VAL_INT; |
297 | case IIO_CHAN_INFO_SCALE: | 299 | case IIO_CHAN_INFO_SCALE: |
298 | *val = 0; | 300 | *val = 0; |
@@ -312,25 +314,20 @@ static int afe4404_write_raw(struct iio_dev *indio_dev, | |||
312 | int val, int val2, long mask) | 314 | int val, int val2, long mask) |
313 | { | 315 | { |
314 | struct afe4404_data *afe = iio_priv(indio_dev); | 316 | struct afe4404_data *afe = iio_priv(indio_dev); |
315 | const struct afe440x_reg_info reg_info = afe4404_reg_info[chan->address]; | 317 | unsigned int led_field = afe4404_channel_leds[chan->address]; |
318 | unsigned int offdac_field = afe4404_channel_offdacs[chan->address]; | ||
316 | 319 | ||
317 | switch (chan->type) { | 320 | switch (chan->type) { |
318 | case IIO_INTENSITY: | 321 | case IIO_INTENSITY: |
319 | switch (mask) { | 322 | switch (mask) { |
320 | case IIO_CHAN_INFO_OFFSET: | 323 | case IIO_CHAN_INFO_OFFSET: |
321 | return regmap_update_bits(afe->regmap, | 324 | return regmap_field_write(afe->fields[offdac_field], val); |
322 | reg_info.offreg, | ||
323 | reg_info.mask, | ||
324 | (val << reg_info.shift)); | ||
325 | } | 325 | } |
326 | break; | 326 | break; |
327 | case IIO_CURRENT: | 327 | case IIO_CURRENT: |
328 | switch (mask) { | 328 | switch (mask) { |
329 | case IIO_CHAN_INFO_RAW: | 329 | case IIO_CHAN_INFO_RAW: |
330 | return regmap_update_bits(afe->regmap, | 330 | return regmap_field_write(afe->fields[led_field], val); |
331 | reg_info.reg, | ||
332 | reg_info.mask, | ||
333 | (val << reg_info.shift)); | ||
334 | } | 331 | } |
335 | break; | 332 | break; |
336 | default: | 333 | default: |
@@ -357,7 +354,7 @@ static irqreturn_t afe4404_trigger_handler(int irq, void *private) | |||
357 | 354 | ||
358 | for_each_set_bit(bit, indio_dev->active_scan_mask, | 355 | for_each_set_bit(bit, indio_dev->active_scan_mask, |
359 | indio_dev->masklength) { | 356 | indio_dev->masklength) { |
360 | ret = regmap_read(afe->regmap, afe4404_reg_info[bit].reg, | 357 | ret = regmap_read(afe->regmap, afe4404_channel_values[bit], |
361 | &buffer[i++]); | 358 | &buffer[i++]); |
362 | if (ret) | 359 | if (ret) |
363 | goto err; | 360 | goto err; |
@@ -490,7 +487,7 @@ static int afe4404_probe(struct i2c_client *client, | |||
490 | { | 487 | { |
491 | struct iio_dev *indio_dev; | 488 | struct iio_dev *indio_dev; |
492 | struct afe4404_data *afe; | 489 | struct afe4404_data *afe; |
493 | int ret; | 490 | int i, ret; |
494 | 491 | ||
495 | indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*afe)); | 492 | indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*afe)); |
496 | if (!indio_dev) | 493 | if (!indio_dev) |
@@ -508,6 +505,15 @@ static int afe4404_probe(struct i2c_client *client, | |||
508 | return PTR_ERR(afe->regmap); | 505 | return PTR_ERR(afe->regmap); |
509 | } | 506 | } |
510 | 507 | ||
508 | for (i = 0; i < F_MAX_FIELDS; i++) { | ||
509 | afe->fields[i] = devm_regmap_field_alloc(afe->dev, afe->regmap, | ||
510 | afe4404_reg_fields[i]); | ||
511 | if (IS_ERR(afe->fields[i])) { | ||
512 | dev_err(afe->dev, "Unable to allocate regmap fields\n"); | ||
513 | return PTR_ERR(afe->fields[i]); | ||
514 | } | ||
515 | } | ||
516 | |||
511 | afe->regulator = devm_regulator_get(afe->dev, "tx_sup"); | 517 | afe->regulator = devm_regulator_get(afe->dev, "tx_sup"); |
512 | if (IS_ERR(afe->regulator)) { | 518 | if (IS_ERR(afe->regulator)) { |
513 | dev_err(afe->dev, "Unable to get regulator\n"); | 519 | dev_err(afe->dev, "Unable to get regulator\n"); |
diff --git a/drivers/iio/health/afe440x.h b/drivers/iio/health/afe440x.h index 713972fd4601..1a0f247043ca 100644 --- a/drivers/iio/health/afe440x.h +++ b/drivers/iio/health/afe440x.h | |||
@@ -88,21 +88,6 @@ | |||
88 | #define AFE440X_CONTROL0_WRITE 0x0 | 88 | #define AFE440X_CONTROL0_WRITE 0x0 |
89 | #define AFE440X_CONTROL0_READ 0x1 | 89 | #define AFE440X_CONTROL0_READ 0x1 |
90 | 90 | ||
91 | struct afe440x_reg_info { | ||
92 | unsigned int reg; | ||
93 | unsigned int offreg; | ||
94 | unsigned int shift; | ||
95 | unsigned int mask; | ||
96 | }; | ||
97 | |||
98 | #define AFE440X_REG_INFO(_reg, _offreg, _sm) \ | ||
99 | { \ | ||
100 | .reg = _reg, \ | ||
101 | .offreg = _offreg, \ | ||
102 | .shift = _sm ## _SHIFT, \ | ||
103 | .mask = _sm ## _MASK, \ | ||
104 | } | ||
105 | |||
106 | #define AFE440X_INTENSITY_CHAN(_index, _mask) \ | 91 | #define AFE440X_INTENSITY_CHAN(_index, _mask) \ |
107 | { \ | 92 | { \ |
108 | .type = IIO_INTENSITY, \ | 93 | .type = IIO_INTENSITY, \ |
@@ -157,9 +142,7 @@ static DEVICE_ATTR_RO(_name) | |||
157 | 142 | ||
158 | struct afe440x_attr { | 143 | struct afe440x_attr { |
159 | struct device_attribute dev_attr; | 144 | struct device_attribute dev_attr; |
160 | unsigned int reg; | 145 | unsigned int field; |
161 | unsigned int shift; | ||
162 | unsigned int mask; | ||
163 | const struct afe440x_val_table *val_table; | 146 | const struct afe440x_val_table *val_table; |
164 | unsigned int table_size; | 147 | unsigned int table_size; |
165 | }; | 148 | }; |
@@ -167,14 +150,12 @@ struct afe440x_attr { | |||
167 | #define to_afe440x_attr(_dev_attr) \ | 150 | #define to_afe440x_attr(_dev_attr) \ |
168 | container_of(_dev_attr, struct afe440x_attr, dev_attr) | 151 | container_of(_dev_attr, struct afe440x_attr, dev_attr) |
169 | 152 | ||
170 | #define AFE440X_ATTR(_name, _reg, _field, _table) \ | 153 | #define AFE440X_ATTR(_name, _field, _table) \ |
171 | struct afe440x_attr afe440x_attr_##_name = { \ | 154 | struct afe440x_attr afe440x_attr_##_name = { \ |
172 | .dev_attr = __ATTR(_name, (S_IRUGO | S_IWUSR), \ | 155 | .dev_attr = __ATTR(_name, (S_IRUGO | S_IWUSR), \ |
173 | afe440x_show_register, \ | 156 | afe440x_show_register, \ |
174 | afe440x_store_register), \ | 157 | afe440x_store_register), \ |
175 | .reg = _reg, \ | 158 | .field = _field, \ |
176 | .shift = _field ## _SHIFT, \ | ||
177 | .mask = _field ## _MASK, \ | ||
178 | .val_table = _table, \ | 159 | .val_table = _table, \ |
179 | .table_size = ARRAY_SIZE(_table), \ | 160 | .table_size = ARRAY_SIZE(_table), \ |
180 | } | 161 | } |