drm/i915: Drop WaDisablePSDDualDispatchEnable:ivb for IVB GT2

Both Bspec and the W/A database state that WaDisablePSDDualDispatchEnable
is only needed for IVB GT1.

The only real confusion here is that the the W/A database also says to
write to the GT2 only register as well, which is strange if the W/A is
only for GT1.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 0 insertions, 7 deletions

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 987e8312641e..df18bb6ffb6f 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4825,13 +4825,6 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
         if (IS_IVB_GT1(dev))
                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
-        else {
-                /* must write both registers */
-                I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
-                           _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
-                I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
-                           _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
-        }
 
         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,