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authorCarlos Santa <carlos.santa@intel.com>2016-08-17 15:30:37 -0400
committerRodrigo Vivi <rodrigo.vivi@intel.com>2016-09-07 19:07:07 -0400
commit8d9c20e1d1e3833b5c4dab33d59cb92ea162da6a (patch)
tree020ceac47334f6597c6daf245a165001fb557731 /drivers/gpu/drm
parent6e3b84d831113804fcae3646b99816556915b881 (diff)
drm/i915: Remove .is_mobile field from platform struct
As recommended by Ville Syrjala removing .is_mobile field from the platform struct definition for vlv and hsw+ GPUs as there's no need to make the distinction in later hardware anymore. Keep it for older GPUs as it is still needed for ilk-ivb. Signed-off-by: Carlos Santa <carlos.santa@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r--drivers/gpu/drm/i915/i915_pci.c45
1 files changed, 8 insertions, 37 deletions
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index e1caa0b63f3b..b5ec8a761b8b 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -250,13 +250,7 @@ static const struct intel_device_info intel_ivybridge_q_info = {
250 GEN_DEFAULT_PIPEOFFSETS, \ 250 GEN_DEFAULT_PIPEOFFSETS, \
251 CURSOR_OFFSETS 251 CURSOR_OFFSETS
252 252
253static const struct intel_device_info intel_valleyview_m_info = { 253static const struct intel_device_info intel_valleyview_info = {
254 VLV_FEATURES,
255 .is_valleyview = 1,
256 .is_mobile = 1,
257};
258
259static const struct intel_device_info intel_valleyview_d_info = {
260 VLV_FEATURES, 254 VLV_FEATURES,
261 .is_valleyview = 1, 255 .is_valleyview = 1,
262}; 256};
@@ -268,47 +262,28 @@ static const struct intel_device_info intel_valleyview_d_info = {
268 .has_fpga_dbg = 1, \ 262 .has_fpga_dbg = 1, \
269 .has_psr = 1 263 .has_psr = 1
270 264
271static const struct intel_device_info intel_haswell_d_info = { 265static const struct intel_device_info intel_haswell_info = {
272 HSW_FEATURES, 266 HSW_FEATURES,
273 .is_haswell = 1, 267 .is_haswell = 1,
274}; 268};
275 269
276static const struct intel_device_info intel_haswell_m_info = {
277 HSW_FEATURES,
278 .is_haswell = 1,
279 .is_mobile = 1,
280};
281
282#define BDW_FEATURES \ 270#define BDW_FEATURES \
283 HSW_FEATURES, \ 271 HSW_FEATURES, \
284 BDW_COLORS 272 BDW_COLORS
285 273
286static const struct intel_device_info intel_broadwell_d_info = { 274static const struct intel_device_info intel_broadwell_info = {
287 BDW_FEATURES, 275 BDW_FEATURES,
288 .gen = 8, 276 .gen = 8,
289 .is_broadwell = 1, 277 .is_broadwell = 1,
290}; 278};
291 279
292static const struct intel_device_info intel_broadwell_m_info = { 280static const struct intel_device_info intel_broadwell_gt3_info = {
293 BDW_FEATURES,
294 .gen = 8, .is_mobile = 1,
295 .is_broadwell = 1,
296};
297
298static const struct intel_device_info intel_broadwell_gt3d_info = {
299 BDW_FEATURES, 281 BDW_FEATURES,
300 .gen = 8, 282 .gen = 8,
301 .is_broadwell = 1, 283 .is_broadwell = 1,
302 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING, 284 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
303}; 285};
304 286
305static const struct intel_device_info intel_broadwell_gt3m_info = {
306 BDW_FEATURES,
307 .gen = 8, .is_mobile = 1,
308 .is_broadwell = 1,
309 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
310};
311
312static const struct intel_device_info intel_cherryview_info = { 287static const struct intel_device_info intel_cherryview_info = {
313 .gen = 8, .num_pipes = 3, 288 .gen = 8, .num_pipes = 3,
314 .need_gfx_hws = 1, .has_hotplug = 1, 289 .need_gfx_hws = 1, .has_hotplug = 1,
@@ -390,14 +365,10 @@ static const struct pci_device_id pciidlist[] = {
390 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ 365 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
391 INTEL_IVB_M_IDS(&intel_ivybridge_m_info), 366 INTEL_IVB_M_IDS(&intel_ivybridge_m_info),
392 INTEL_IVB_D_IDS(&intel_ivybridge_d_info), 367 INTEL_IVB_D_IDS(&intel_ivybridge_d_info),
393 INTEL_HSW_D_IDS(&intel_haswell_d_info), 368 INTEL_HSW_IDS(&intel_haswell_info),
394 INTEL_HSW_M_IDS(&intel_haswell_m_info), 369 INTEL_VLV_IDS(&intel_valleyview_info),
395 INTEL_VLV_M_IDS(&intel_valleyview_m_info), 370 INTEL_BDW_GT12_IDS(&intel_broadwell_info),
396 INTEL_VLV_D_IDS(&intel_valleyview_d_info), 371 INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info),
397 INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info),
398 INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info),
399 INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info),
400 INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info),
401 INTEL_CHV_IDS(&intel_cherryview_info), 372 INTEL_CHV_IDS(&intel_cherryview_info),
402 INTEL_SKL_GT1_IDS(&intel_skylake_info), 373 INTEL_SKL_GT1_IDS(&intel_skylake_info),
403 INTEL_SKL_GT2_IDS(&intel_skylake_info), 374 INTEL_SKL_GT2_IDS(&intel_skylake_info),