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authorCarlos Santa <carlos.santa@intel.com>2016-08-17 15:30:56 -0400
committerRodrigo Vivi <rodrigo.vivi@intel.com>2016-09-07 19:07:09 -0400
commit3177659a41cc4362cb740c24a982c2097962eb1b (patch)
tree4d0acdecae340933fe729ba4466af0b988c2dc67 /drivers/gpu/drm
parent804b87125e3ce49b20d9e8f39a70280e9adc5de1 (diff)
drm/i915: Make HWS_NEEDS_PHYSICAL the exception
Make the .hws_needs_physical the exception by switching the flag on earlier platforms since they are fewer to support. Remove the flag on later GPUs hardware since they all use GTT hws by default. Switch the logic as well in the driver to reflect this change Signed-off-by: Carlos Santa <carlos.santa@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h4
-rw-r--r--drivers/gpu/drm/i915/i915_gpu_error.c2
-rw-r--r--drivers/gpu/drm/i915/i915_pci.c27
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.c20
4 files changed, 30 insertions, 23 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index fcba6fe3caaf..755799e06a21 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -639,7 +639,7 @@ struct intel_csr {
639 func(is_i915g) sep \ 639 func(is_i915g) sep \
640 func(is_i945gm) sep \ 640 func(is_i945gm) sep \
641 func(is_g33) sep \ 641 func(is_g33) sep \
642 func(need_gfx_hws) sep \ 642 func(hws_needs_physical) sep \
643 func(is_g4x) sep \ 643 func(is_g4x) sep \
644 func(is_pineview) sep \ 644 func(is_pineview) sep \
645 func(is_broadwater) sep \ 645 func(is_broadwater) sep \
@@ -2748,7 +2748,7 @@ struct drm_i915_cmd_table {
2748#define HAS_EDRAM(dev) (!!(__I915__(dev)->edram_cap & EDRAM_ENABLED)) 2748#define HAS_EDRAM(dev) (!!(__I915__(dev)->edram_cap & EDRAM_ENABLED))
2749#define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \ 2749#define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2750 HAS_EDRAM(dev)) 2750 HAS_EDRAM(dev))
2751#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) 2751#define HWS_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->hws_needs_physical)
2752 2752
2753#define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->has_hw_contexts) 2753#define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->has_hw_contexts)
2754#define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->has_logical_ring_contexts) 2754#define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->has_logical_ring_contexts)
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index d45a959b7c53..334f15df7c8d 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1025,7 +1025,7 @@ static void error_record_engine_registers(struct drm_i915_error_state *error,
1025 if (INTEL_GEN(dev_priv) > 2) 1025 if (INTEL_GEN(dev_priv) > 2)
1026 ee->mode = I915_READ_MODE(engine); 1026 ee->mode = I915_READ_MODE(engine);
1027 1027
1028 if (I915_NEED_GFX_HWS(dev_priv)) { 1028 if (!HWS_NEEDS_PHYSICAL(dev_priv)) {
1029 i915_reg_t mmio; 1029 i915_reg_t mmio;
1030 1030
1031 if (IS_GEN7(dev_priv)) { 1031 if (IS_GEN7(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 0f1eb4a5153d..05603b151acd 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -58,6 +58,7 @@
58 .gen = 2, .num_pipes = 1, \ 58 .gen = 2, .num_pipes = 1, \
59 .has_overlay = 1, .overlay_needs_physical = 1, \ 59 .has_overlay = 1, .overlay_needs_physical = 1, \
60 .has_gmch_display = 1, \ 60 .has_gmch_display = 1, \
61 .hws_needs_physical = 1, \
61 .ring_mask = RENDER_RING, \ 62 .ring_mask = RENDER_RING, \
62 GEN_DEFAULT_PIPEOFFSETS, \ 63 GEN_DEFAULT_PIPEOFFSETS, \
63 CURSOR_OFFSETS 64 CURSOR_OFFSETS
@@ -95,6 +96,7 @@ static const struct intel_device_info intel_i915g_info = {
95 GEN3_FEATURES, 96 GEN3_FEATURES,
96 .is_i915g = 1, .cursor_needs_physical = 1, 97 .is_i915g = 1, .cursor_needs_physical = 1,
97 .has_overlay = 1, .overlay_needs_physical = 1, 98 .has_overlay = 1, .overlay_needs_physical = 1,
99 .hws_needs_physical = 1,
98}; 100};
99static const struct intel_device_info intel_i915gm_info = { 101static const struct intel_device_info intel_i915gm_info = {
100 GEN3_FEATURES, 102 GEN3_FEATURES,
@@ -103,11 +105,13 @@ static const struct intel_device_info intel_i915gm_info = {
103 .has_overlay = 1, .overlay_needs_physical = 1, 105 .has_overlay = 1, .overlay_needs_physical = 1,
104 .supports_tv = 1, 106 .supports_tv = 1,
105 .has_fbc = 1, 107 .has_fbc = 1,
108 .hws_needs_physical = 1,
106}; 109};
107static const struct intel_device_info intel_i945g_info = { 110static const struct intel_device_info intel_i945g_info = {
108 GEN3_FEATURES, 111 GEN3_FEATURES,
109 .has_hotplug = 1, .cursor_needs_physical = 1, 112 .has_hotplug = 1, .cursor_needs_physical = 1,
110 .has_overlay = 1, .overlay_needs_physical = 1, 113 .has_overlay = 1, .overlay_needs_physical = 1,
114 .hws_needs_physical = 1,
111}; 115};
112static const struct intel_device_info intel_i945gm_info = { 116static const struct intel_device_info intel_i945gm_info = {
113 GEN3_FEATURES, 117 GEN3_FEATURES,
@@ -116,6 +120,7 @@ static const struct intel_device_info intel_i945gm_info = {
116 .has_overlay = 1, .overlay_needs_physical = 1, 120 .has_overlay = 1, .overlay_needs_physical = 1,
117 .supports_tv = 1, 121 .supports_tv = 1,
118 .has_fbc = 1, 122 .has_fbc = 1,
123 .hws_needs_physical = 1,
119}; 124};
120 125
121#define GEN4_FEATURES \ 126#define GEN4_FEATURES \
@@ -130,6 +135,7 @@ static const struct intel_device_info intel_i965g_info = {
130 GEN4_FEATURES, 135 GEN4_FEATURES,
131 .is_broadwater = 1, 136 .is_broadwater = 1,
132 .has_overlay = 1, 137 .has_overlay = 1,
138 .hws_needs_physical = 1,
133}; 139};
134 140
135static const struct intel_device_info intel_i965gm_info = { 141static const struct intel_device_info intel_i965gm_info = {
@@ -138,18 +144,19 @@ static const struct intel_device_info intel_i965gm_info = {
138 .is_mobile = 1, .has_fbc = 1, 144 .is_mobile = 1, .has_fbc = 1,
139 .has_overlay = 1, 145 .has_overlay = 1,
140 .supports_tv = 1, 146 .supports_tv = 1,
147 .hws_needs_physical = 1,
141}; 148};
142 149
143static const struct intel_device_info intel_g33_info = { 150static const struct intel_device_info intel_g33_info = {
144 GEN3_FEATURES, 151 GEN3_FEATURES,
145 .is_g33 = 1, 152 .is_g33 = 1,
146 .need_gfx_hws = 1, .has_hotplug = 1, 153 .has_hotplug = 1,
147 .has_overlay = 1, 154 .has_overlay = 1,
148}; 155};
149 156
150static const struct intel_device_info intel_g45_info = { 157static const struct intel_device_info intel_g45_info = {
151 GEN4_FEATURES, 158 GEN4_FEATURES,
152 .is_g4x = 1, .need_gfx_hws = 1, 159 .is_g4x = 1,
153 .has_pipe_cxsr = 1, 160 .has_pipe_cxsr = 1,
154 .ring_mask = RENDER_RING | BSD_RING, 161 .ring_mask = RENDER_RING | BSD_RING,
155}; 162};
@@ -157,7 +164,7 @@ static const struct intel_device_info intel_g45_info = {
157static const struct intel_device_info intel_gm45_info = { 164static const struct intel_device_info intel_gm45_info = {
158 GEN4_FEATURES, 165 GEN4_FEATURES,
159 .is_g4x = 1, 166 .is_g4x = 1,
160 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, 167 .is_mobile = 1, .has_fbc = 1,
161 .has_pipe_cxsr = 1, 168 .has_pipe_cxsr = 1,
162 .supports_tv = 1, 169 .supports_tv = 1,
163 .ring_mask = RENDER_RING | BSD_RING, 170 .ring_mask = RENDER_RING | BSD_RING,
@@ -166,13 +173,13 @@ static const struct intel_device_info intel_gm45_info = {
166static const struct intel_device_info intel_pineview_info = { 173static const struct intel_device_info intel_pineview_info = {
167 GEN3_FEATURES, 174 GEN3_FEATURES,
168 .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, 175 .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
169 .need_gfx_hws = 1, .has_hotplug = 1, 176 .has_hotplug = 1,
170 .has_overlay = 1, 177 .has_overlay = 1,
171}; 178};
172 179
173#define GEN5_FEATURES \ 180#define GEN5_FEATURES \
174 .gen = 5, .num_pipes = 2, \ 181 .gen = 5, .num_pipes = 2, \
175 .need_gfx_hws = 1, .has_hotplug = 1, \ 182 .has_hotplug = 1, \
176 .has_gmbus_irq = 1, \ 183 .has_gmbus_irq = 1, \
177 .ring_mask = RENDER_RING | BSD_RING, \ 184 .ring_mask = RENDER_RING | BSD_RING, \
178 GEN_DEFAULT_PIPEOFFSETS, \ 185 GEN_DEFAULT_PIPEOFFSETS, \
@@ -189,7 +196,7 @@ static const struct intel_device_info intel_ironlake_m_info = {
189 196
190#define GEN6_FEATURES \ 197#define GEN6_FEATURES \
191 .gen = 6, .num_pipes = 2, \ 198 .gen = 6, .num_pipes = 2, \
192 .need_gfx_hws = 1, .has_hotplug = 1, \ 199 .has_hotplug = 1, \
193 .has_fbc = 1, \ 200 .has_fbc = 1, \
194 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ 201 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
195 .has_llc = 1, \ 202 .has_llc = 1, \
@@ -211,7 +218,7 @@ static const struct intel_device_info intel_sandybridge_m_info = {
211 218
212#define GEN7_FEATURES \ 219#define GEN7_FEATURES \
213 .gen = 7, .num_pipes = 3, \ 220 .gen = 7, .num_pipes = 3, \
214 .need_gfx_hws = 1, .has_hotplug = 1, \ 221 .has_hotplug = 1, \
215 .has_fbc = 1, \ 222 .has_fbc = 1, \
216 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ 223 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
217 .has_llc = 1, \ 224 .has_llc = 1, \
@@ -250,7 +257,7 @@ static const struct intel_device_info intel_ivybridge_q_info = {
250 .has_gmbus_irq = 1, \ 257 .has_gmbus_irq = 1, \
251 .has_hw_contexts = 1, \ 258 .has_hw_contexts = 1, \
252 .has_gmch_display = 1, \ 259 .has_gmch_display = 1, \
253 .need_gfx_hws = 1, .has_hotplug = 1, \ 260 .has_hotplug = 1, \
254 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ 261 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
255 .display_mmio_offset = VLV_DISPLAY_BASE, \ 262 .display_mmio_offset = VLV_DISPLAY_BASE, \
256 GEN_DEFAULT_PIPEOFFSETS, \ 263 GEN_DEFAULT_PIPEOFFSETS, \
@@ -298,7 +305,7 @@ static const struct intel_device_info intel_broadwell_gt3_info = {
298 305
299static const struct intel_device_info intel_cherryview_info = { 306static const struct intel_device_info intel_cherryview_info = {
300 .gen = 8, .num_pipes = 3, 307 .gen = 8, .num_pipes = 3,
301 .need_gfx_hws = 1, .has_hotplug = 1, 308 .has_hotplug = 1,
302 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, 309 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
303 .is_cherryview = 1, 310 .is_cherryview = 1,
304 .has_psr = 1, 311 .has_psr = 1,
@@ -333,7 +340,7 @@ static const struct intel_device_info intel_skylake_gt3_info = {
333static const struct intel_device_info intel_broxton_info = { 340static const struct intel_device_info intel_broxton_info = {
334 .is_broxton = 1, 341 .is_broxton = 1,
335 .gen = 9, 342 .gen = 9,
336 .need_gfx_hws = 1, .has_hotplug = 1, 343 .has_hotplug = 1,
337 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, 344 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
338 .num_pipes = 3, 345 .num_pipes = 3,
339 .has_ddi = 1, 346 .has_ddi = 1,
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 4472752812cb..fd8fcc6ec970 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -559,10 +559,10 @@ static int init_ring_common(struct intel_engine_cs *engine)
559 } 559 }
560 } 560 }
561 561
562 if (I915_NEED_GFX_HWS(dev_priv)) 562 if (HWS_NEEDS_PHYSICAL(dev_priv))
563 intel_ring_setup_status_page(engine);
564 else
565 ring_setup_phys_status_page(engine); 563 ring_setup_phys_status_page(engine);
564 else
565 intel_ring_setup_status_page(engine);
566 566
567 /* Enforce ordering by reading HEAD register back */ 567 /* Enforce ordering by reading HEAD register back */
568 I915_READ_HEAD(engine); 568 I915_READ_HEAD(engine);
@@ -2109,13 +2109,13 @@ static int intel_init_ring_buffer(struct intel_engine_cs *engine)
2109 goto error; 2109 goto error;
2110 } 2110 }
2111 2111
2112 if (I915_NEED_GFX_HWS(dev_priv)) { 2112 if (HWS_NEEDS_PHYSICAL(dev_priv)) {
2113 ret = init_status_page(engine); 2113 WARN_ON(engine->id != RCS);
2114 ret = init_phys_status_page(engine);
2114 if (ret) 2115 if (ret)
2115 goto error; 2116 goto error;
2116 } else { 2117 } else {
2117 WARN_ON(engine->id != RCS); 2118 ret = init_status_page(engine);
2118 ret = init_phys_status_page(engine);
2119 if (ret) 2119 if (ret)
2120 goto error; 2120 goto error;
2121 } 2121 }
@@ -2155,11 +2155,11 @@ void intel_engine_cleanup(struct intel_engine_cs *engine)
2155 if (engine->cleanup) 2155 if (engine->cleanup)
2156 engine->cleanup(engine); 2156 engine->cleanup(engine);
2157 2157
2158 if (I915_NEED_GFX_HWS(dev_priv)) { 2158 if (HWS_NEEDS_PHYSICAL(dev_priv)) {
2159 cleanup_status_page(engine);
2160 } else {
2161 WARN_ON(engine->id != RCS); 2159 WARN_ON(engine->id != RCS);
2162 cleanup_phys_status_page(engine); 2160 cleanup_phys_status_page(engine);
2161 } else {
2162 cleanup_status_page(engine);
2163 } 2163 }
2164 2164
2165 intel_engine_cleanup_common(engine); 2165 intel_engine_cleanup_common(engine);