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authorAlex Deucher <alexdeucher@gmail.com>2010-03-26 19:36:33 -0400
committerDave Airlie <airlied@redhat.com>2010-03-30 23:12:39 -0400
commit97586c422b38c4c12e2b5011d59c401d03d09ed6 (patch)
tree873cb566e3fbb3c698f8b56fb3972361d53f3f78 /drivers/gpu/drm/radeon/reg_srcs
parent6bb118012ab0462d5ebc3ab17eb278416532cf15 (diff)
drm/radeon/r6xx/r7xx: further safe reg clean up
- remove a few more drm only regs - remove sampler, alu, bool, loop constant regs. They are set via separate packet3's already Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/reg_srcs')
-rw-r--r--drivers/gpu/drm/radeon/reg_srcs/r60019
1 files changed, 0 insertions, 19 deletions
diff --git a/drivers/gpu/drm/radeon/reg_srcs/r600 b/drivers/gpu/drm/radeon/reg_srcs/r600
index bc062f9a847f..af0da4ae3f55 100644
--- a/drivers/gpu/drm/radeon/reg_srcs/r600
+++ b/drivers/gpu/drm/radeon/reg_srcs/r600
@@ -26,20 +26,16 @@ r600 0x9400
260x00028408 VGT_INDX_OFFSET 260x00028408 VGT_INDX_OFFSET
270x00028AA0 VGT_INSTANCE_STEP_RATE_0 270x00028AA0 VGT_INSTANCE_STEP_RATE_0
280x00028AA4 VGT_INSTANCE_STEP_RATE_1 280x00028AA4 VGT_INSTANCE_STEP_RATE_1
290x000088C0 VGT_LAST_COPY_STATE
300x00028400 VGT_MAX_VTX_INDX 290x00028400 VGT_MAX_VTX_INDX
310x000088D8 VGT_MC_LAT_CNTL
320x00028404 VGT_MIN_VTX_INDX 300x00028404 VGT_MIN_VTX_INDX
330x00028A94 VGT_MULTI_PRIM_IB_RESET_EN 310x00028A94 VGT_MULTI_PRIM_IB_RESET_EN
340x0002840C VGT_MULTI_PRIM_IB_RESET_INDX 320x0002840C VGT_MULTI_PRIM_IB_RESET_INDX
350x00008970 VGT_NUM_INDICES 330x00008970 VGT_NUM_INDICES
360x00008974 VGT_NUM_INSTANCES 340x00008974 VGT_NUM_INSTANCES
370x00028A10 VGT_OUTPUT_PATH_CNTL 350x00028A10 VGT_OUTPUT_PATH_CNTL
380x00028C5C VGT_OUT_DEALLOC_CNTL
390x00028A84 VGT_PRIMITIVEID_EN 360x00028A84 VGT_PRIMITIVEID_EN
400x00008958 VGT_PRIMITIVE_TYPE 370x00008958 VGT_PRIMITIVE_TYPE
410x00028AB4 VGT_REUSE_OFF 380x00028AB4 VGT_REUSE_OFF
420x00028C58 VGT_VERTEX_REUSE_BLOCK_CNTL
430x00028AB8 VGT_VTX_CNT_EN 390x00028AB8 VGT_VTX_CNT_EN
440x000088B0 VGT_VTX_VECT_EJECT_REG 400x000088B0 VGT_VTX_VECT_EJECT_REG
450x00028810 PA_CL_CLIP_CNTL 410x00028810 PA_CL_CLIP_CNTL
@@ -319,18 +315,6 @@ r600 0x9400
3190x000283FC SQ_VTX_SEMANTIC_31 3150x000283FC SQ_VTX_SEMANTIC_31
3200x000288E0 SQ_VTX_SEMANTIC_CLEAR 3160x000288E0 SQ_VTX_SEMANTIC_CLEAR
3210x0003CFF4 SQ_VTX_START_INST_LOC 3170x0003CFF4 SQ_VTX_START_INST_LOC
3220x0003C000 SQ_TEX_SAMPLER_WORD0_0
3230x0003C004 SQ_TEX_SAMPLER_WORD1_0
3240x0003C008 SQ_TEX_SAMPLER_WORD2_0
3250x00030000 SQ_ALU_CONSTANT0_0
3260x00030004 SQ_ALU_CONSTANT1_0
3270x00030008 SQ_ALU_CONSTANT2_0
3280x0003000C SQ_ALU_CONSTANT3_0
3290x0003E380 SQ_BOOL_CONST_0
3300x0003E384 SQ_BOOL_CONST_1
3310x0003E388 SQ_BOOL_CONST_2
3320x0003E200 SQ_LOOP_CONST_0
3330x0003E200 SQ_LOOP_CONST_DX10_0
3340x000281C0 SQ_ALU_CONST_BUFFER_SIZE_GS_0 3180x000281C0 SQ_ALU_CONST_BUFFER_SIZE_GS_0
3350x000281C4 SQ_ALU_CONST_BUFFER_SIZE_GS_1 3190x000281C4 SQ_ALU_CONST_BUFFER_SIZE_GS_1
3360x000281C8 SQ_ALU_CONST_BUFFER_SIZE_GS_2 3200x000281C8 SQ_ALU_CONST_BUFFER_SIZE_GS_2
@@ -445,9 +429,6 @@ r600 0x9400
4450x00028438 SX_ALPHA_REF 4290x00028438 SX_ALPHA_REF
4460x00028410 SX_ALPHA_TEST_CONTROL 4300x00028410 SX_ALPHA_TEST_CONTROL
4470x00028350 SX_MISC 4310x00028350 SX_MISC
4480x0000A020 SMX_DC_CTL0
4490x0000A024 SMX_DC_CTL1
4500x0000A028 SMX_DC_CTL2
4510x00009604 TC_INVALIDATE 4320x00009604 TC_INVALIDATE
4520x00009400 TD_FILTER4 4330x00009400 TD_FILTER4
4530x00009404 TD_FILTER4_1 4340x00009404 TD_FILTER4_1
generated by cgit v1.2.2 (git 2.25.0) at 2026-04-25 12:25:57 -0400