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authorAlex Deucher <alexdeucher@gmail.com>2010-01-19 17:16:10 -0500
committerDave Airlie <airlied@redhat.com>2010-01-24 02:24:23 -0500
commitfc10332b8ac5ca32d11f898027d84c007543bd80 (patch)
tree28b24fb83e4c4bfc71286ce93f01271fa5027c95 /drivers/gpu/drm/radeon/radeon_legacy_crtc.c
parenta348c84d953f61c776e53cde0a63a4e407a23c18 (diff)
drm/radeon/kms: clean up pll struct
- add a new flag for fixed post div - pull the pll flags into the struct Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_legacy_crtc.c')
-rw-r--r--drivers/gpu/drm/radeon/radeon_legacy_crtc.c14
1 files changed, 7 insertions, 7 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
index 762e07b08951..b6d8081e1246 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
@@ -692,7 +692,6 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
692 uint32_t post_divider = 0; 692 uint32_t post_divider = 0;
693 uint32_t freq = 0; 693 uint32_t freq = 0;
694 uint8_t pll_gain; 694 uint8_t pll_gain;
695 int pll_flags = RADEON_PLL_LEGACY;
696 bool use_bios_divs = false; 695 bool use_bios_divs = false;
697 /* PLL registers */ 696 /* PLL registers */
698 uint32_t pll_ref_div = 0; 697 uint32_t pll_ref_div = 0;
@@ -726,10 +725,12 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
726 else 725 else
727 pll = &rdev->clock.p1pll; 726 pll = &rdev->clock.p1pll;
728 727
728 pll->flags = RADEON_PLL_LEGACY;
729
729 if (mode->clock > 200000) /* range limits??? */ 730 if (mode->clock > 200000) /* range limits??? */
730 pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; 731 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
731 else 732 else
732 pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; 733 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
733 734
734 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 735 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
735 if (encoder->crtc == crtc) { 736 if (encoder->crtc == crtc) {
@@ -741,7 +742,7 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
741 } 742 }
742 743
743 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) 744 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
744 pll_flags |= RADEON_PLL_NO_ODD_POST_DIV; 745 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
745 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) { 746 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) {
746 if (!rdev->is_atom_bios) { 747 if (!rdev->is_atom_bios) {
747 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 748 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
@@ -756,7 +757,7 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
756 } 757 }
757 } 758 }
758 } 759 }
759 pll_flags |= RADEON_PLL_USE_REF_DIV; 760 pll->flags |= RADEON_PLL_USE_REF_DIV;
760 } 761 }
761 } 762 }
762 } 763 }
@@ -766,8 +767,7 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
766 if (!use_bios_divs) { 767 if (!use_bios_divs) {
767 radeon_compute_pll(pll, mode->clock, 768 radeon_compute_pll(pll, mode->clock,
768 &freq, &feedback_div, &frac_fb_div, 769 &freq, &feedback_div, &frac_fb_div,
769 &reference_div, &post_divider, 770 &reference_div, &post_divider);
770 pll_flags);
771 771
772 for (post_div = &post_divs[0]; post_div->divider; ++post_div) { 772 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
773 if (post_div->divider == post_divider) 773 if (post_div->divider == post_divider)