diff options
author | Michel Dänzer <daenzer@vmware.com> | 2009-08-13 05:10:51 -0400 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2009-08-15 18:36:19 -0400 |
commit | 7ed220d738cf16adff6bc3b31ad25b8848a2fa9c (patch) | |
tree | a751003e7cf1dc63ea478181dffef936f04cc24e /drivers/gpu/drm/radeon/radeon_asic.h | |
parent | 3f8befec95d5c1bbc6e247e1a5dafa82519530f9 (diff) |
drm/radeon/kms: Fix up vertical blank interrupt support.
Fixes 3D apps timing out in the WAIT_VBLANK ioctl.
AVIVO bits compile-tested only.
Signed-off-by: Michel Dänzer <daenzer@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_asic.h')
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_asic.h | 23 |
1 files changed, 17 insertions, 6 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h index c0ae2d923254..7ca6c13569b5 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.h +++ b/drivers/gpu/drm/radeon/radeon_asic.h | |||
@@ -49,6 +49,7 @@ void r100_vram_info(struct radeon_device *rdev); | |||
49 | int r100_gpu_reset(struct radeon_device *rdev); | 49 | int r100_gpu_reset(struct radeon_device *rdev); |
50 | int r100_mc_init(struct radeon_device *rdev); | 50 | int r100_mc_init(struct radeon_device *rdev); |
51 | void r100_mc_fini(struct radeon_device *rdev); | 51 | void r100_mc_fini(struct radeon_device *rdev); |
52 | u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc); | ||
52 | int r100_wb_init(struct radeon_device *rdev); | 53 | int r100_wb_init(struct radeon_device *rdev); |
53 | void r100_wb_fini(struct radeon_device *rdev); | 54 | void r100_wb_fini(struct radeon_device *rdev); |
54 | int r100_gart_enable(struct radeon_device *rdev); | 55 | int r100_gart_enable(struct radeon_device *rdev); |
@@ -96,6 +97,7 @@ static struct radeon_asic r100_asic = { | |||
96 | .ring_start = &r100_ring_start, | 97 | .ring_start = &r100_ring_start, |
97 | .irq_set = &r100_irq_set, | 98 | .irq_set = &r100_irq_set, |
98 | .irq_process = &r100_irq_process, | 99 | .irq_process = &r100_irq_process, |
100 | .get_vblank_counter = &r100_get_vblank_counter, | ||
99 | .fence_ring_emit = &r100_fence_ring_emit, | 101 | .fence_ring_emit = &r100_fence_ring_emit, |
100 | .cs_parse = &r100_cs_parse, | 102 | .cs_parse = &r100_cs_parse, |
101 | .copy_blit = &r100_copy_blit, | 103 | .copy_blit = &r100_copy_blit, |
@@ -156,6 +158,7 @@ static struct radeon_asic r300_asic = { | |||
156 | .ring_start = &r300_ring_start, | 158 | .ring_start = &r300_ring_start, |
157 | .irq_set = &r100_irq_set, | 159 | .irq_set = &r100_irq_set, |
158 | .irq_process = &r100_irq_process, | 160 | .irq_process = &r100_irq_process, |
161 | .get_vblank_counter = &r100_get_vblank_counter, | ||
159 | .fence_ring_emit = &r300_fence_ring_emit, | 162 | .fence_ring_emit = &r300_fence_ring_emit, |
160 | .cs_parse = &r300_cs_parse, | 163 | .cs_parse = &r300_cs_parse, |
161 | .copy_blit = &r100_copy_blit, | 164 | .copy_blit = &r100_copy_blit, |
@@ -196,6 +199,7 @@ static struct radeon_asic r420_asic = { | |||
196 | .ring_start = &r300_ring_start, | 199 | .ring_start = &r300_ring_start, |
197 | .irq_set = &r100_irq_set, | 200 | .irq_set = &r100_irq_set, |
198 | .irq_process = &r100_irq_process, | 201 | .irq_process = &r100_irq_process, |
202 | .get_vblank_counter = &r100_get_vblank_counter, | ||
199 | .fence_ring_emit = &r300_fence_ring_emit, | 203 | .fence_ring_emit = &r300_fence_ring_emit, |
200 | .cs_parse = &r300_cs_parse, | 204 | .cs_parse = &r300_cs_parse, |
201 | .copy_blit = &r100_copy_blit, | 205 | .copy_blit = &r100_copy_blit, |
@@ -243,6 +247,7 @@ static struct radeon_asic rs400_asic = { | |||
243 | .ring_start = &r300_ring_start, | 247 | .ring_start = &r300_ring_start, |
244 | .irq_set = &r100_irq_set, | 248 | .irq_set = &r100_irq_set, |
245 | .irq_process = &r100_irq_process, | 249 | .irq_process = &r100_irq_process, |
250 | .get_vblank_counter = &r100_get_vblank_counter, | ||
246 | .fence_ring_emit = &r300_fence_ring_emit, | 251 | .fence_ring_emit = &r300_fence_ring_emit, |
247 | .cs_parse = &r300_cs_parse, | 252 | .cs_parse = &r300_cs_parse, |
248 | .copy_blit = &r100_copy_blit, | 253 | .copy_blit = &r100_copy_blit, |
@@ -266,6 +271,8 @@ void rs600_vram_info(struct radeon_device *rdev); | |||
266 | int rs600_mc_init(struct radeon_device *rdev); | 271 | int rs600_mc_init(struct radeon_device *rdev); |
267 | void rs600_mc_fini(struct radeon_device *rdev); | 272 | void rs600_mc_fini(struct radeon_device *rdev); |
268 | int rs600_irq_set(struct radeon_device *rdev); | 273 | int rs600_irq_set(struct radeon_device *rdev); |
274 | int rs600_irq_process(struct radeon_device *rdev); | ||
275 | u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc); | ||
269 | int rs600_gart_enable(struct radeon_device *rdev); | 276 | int rs600_gart_enable(struct radeon_device *rdev); |
270 | void rs600_gart_disable(struct radeon_device *rdev); | 277 | void rs600_gart_disable(struct radeon_device *rdev); |
271 | void rs600_gart_tlb_flush(struct radeon_device *rdev); | 278 | void rs600_gart_tlb_flush(struct radeon_device *rdev); |
@@ -291,7 +298,8 @@ static struct radeon_asic rs600_asic = { | |||
291 | .cp_disable = &r100_cp_disable, | 298 | .cp_disable = &r100_cp_disable, |
292 | .ring_start = &r300_ring_start, | 299 | .ring_start = &r300_ring_start, |
293 | .irq_set = &rs600_irq_set, | 300 | .irq_set = &rs600_irq_set, |
294 | .irq_process = &r100_irq_process, | 301 | .irq_process = &rs600_irq_process, |
302 | .get_vblank_counter = &rs600_get_vblank_counter, | ||
295 | .fence_ring_emit = &r300_fence_ring_emit, | 303 | .fence_ring_emit = &r300_fence_ring_emit, |
296 | .cs_parse = &r300_cs_parse, | 304 | .cs_parse = &r300_cs_parse, |
297 | .copy_blit = &r100_copy_blit, | 305 | .copy_blit = &r100_copy_blit, |
@@ -334,7 +342,8 @@ static struct radeon_asic rs690_asic = { | |||
334 | .cp_disable = &r100_cp_disable, | 342 | .cp_disable = &r100_cp_disable, |
335 | .ring_start = &r300_ring_start, | 343 | .ring_start = &r300_ring_start, |
336 | .irq_set = &rs600_irq_set, | 344 | .irq_set = &rs600_irq_set, |
337 | .irq_process = &r100_irq_process, | 345 | .irq_process = &rs600_irq_process, |
346 | .get_vblank_counter = &rs600_get_vblank_counter, | ||
338 | .fence_ring_emit = &r300_fence_ring_emit, | 347 | .fence_ring_emit = &r300_fence_ring_emit, |
339 | .cs_parse = &r300_cs_parse, | 348 | .cs_parse = &r300_cs_parse, |
340 | .copy_blit = &r100_copy_blit, | 349 | .copy_blit = &r100_copy_blit, |
@@ -382,8 +391,9 @@ static struct radeon_asic rv515_asic = { | |||
382 | .cp_fini = &r100_cp_fini, | 391 | .cp_fini = &r100_cp_fini, |
383 | .cp_disable = &r100_cp_disable, | 392 | .cp_disable = &r100_cp_disable, |
384 | .ring_start = &rv515_ring_start, | 393 | .ring_start = &rv515_ring_start, |
385 | .irq_set = &r100_irq_set, | 394 | .irq_set = &rs600_irq_set, |
386 | .irq_process = &r100_irq_process, | 395 | .irq_process = &rs600_irq_process, |
396 | .get_vblank_counter = &rs600_get_vblank_counter, | ||
387 | .fence_ring_emit = &r300_fence_ring_emit, | 397 | .fence_ring_emit = &r300_fence_ring_emit, |
388 | .cs_parse = &r300_cs_parse, | 398 | .cs_parse = &r300_cs_parse, |
389 | .copy_blit = &r100_copy_blit, | 399 | .copy_blit = &r100_copy_blit, |
@@ -424,8 +434,9 @@ static struct radeon_asic r520_asic = { | |||
424 | .cp_fini = &r100_cp_fini, | 434 | .cp_fini = &r100_cp_fini, |
425 | .cp_disable = &r100_cp_disable, | 435 | .cp_disable = &r100_cp_disable, |
426 | .ring_start = &rv515_ring_start, | 436 | .ring_start = &rv515_ring_start, |
427 | .irq_set = &r100_irq_set, | 437 | .irq_set = &rs600_irq_set, |
428 | .irq_process = &r100_irq_process, | 438 | .irq_process = &rs600_irq_process, |
439 | .get_vblank_counter = &rs600_get_vblank_counter, | ||
429 | .fence_ring_emit = &r300_fence_ring_emit, | 440 | .fence_ring_emit = &r300_fence_ring_emit, |
430 | .cs_parse = &r300_cs_parse, | 441 | .cs_parse = &r300_cs_parse, |
431 | .copy_blit = &r100_copy_blit, | 442 | .copy_blit = &r100_copy_blit, |