drm/radeon: fixup tiling group size and backendmap on r6xx-r9xx (v4)

Tiling group size is always 256bits on r6xx/r7xx/r8xx/9xx. Also fix and
simplify render backend map. This now properly sets up the backend map
on r6xx-9xx which should improve 3D performance.

Vadim benchmarked also:
Some benchmarks on juniper (5750), fullscreen 1920x1080,
first result - kernel 3.4.0+ (fb21affa), second - with these patches:

Lightsmark:   91 fps => 123 fps    +35%
Doom3:        74 fps => 101 fps    +36%

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

1 files changed, 45 insertions, 323 deletions

diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 6a57f0d4dae8..01550d05e273 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -1558,163 +1558,10 @@ int evergreen_cp_resume(struct radeon_device *rdev)
 /*
  * Core functions
  */
-static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
-                                                  u32 num_tile_pipes,
-                                                  u32 num_backends,
-                                                  u32 backend_disable_mask)
-{
-        u32 backend_map = 0;
-        u32 enabled_backends_mask = 0;
-        u32 enabled_backends_count = 0;
-        u32 cur_pipe;
-        u32 swizzle_pipe[EVERGREEN_MAX_PIPES];
-        u32 cur_backend = 0;
-        u32 i;
-        bool force_no_swizzle;
-
-        if (num_tile_pipes > EVERGREEN_MAX_PIPES)
-                num_tile_pipes = EVERGREEN_MAX_PIPES;
-        if (num_tile_pipes < 1)
-                num_tile_pipes = 1;
-        if (num_backends > EVERGREEN_MAX_BACKENDS)
-                num_backends = EVERGREEN_MAX_BACKENDS;
-        if (num_backends < 1)
-                num_backends = 1;
-
-        for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
-                if (((backend_disable_mask >> i) & 1) == 0) {
-                        enabled_backends_mask |= (1 << i);
-                        ++enabled_backends_count;
-                }
-                if (enabled_backends_count == num_backends)
-                        break;
-        }
-
-        if (enabled_backends_count == 0) {
-                enabled_backends_mask = 1;
-                enabled_backends_count = 1;
-        }
-
-        if (enabled_backends_count != num_backends)
-                num_backends = enabled_backends_count;
-
-        memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * EVERGREEN_MAX_PIPES);
-        switch (rdev->family) {
-        case CHIP_CEDAR:
-        case CHIP_REDWOOD:
-        case CHIP_PALM:
-        case CHIP_SUMO:
-        case CHIP_SUMO2:
-        case CHIP_TURKS:
-        case CHIP_CAICOS:
-                force_no_swizzle = false;
-                break;
-        case CHIP_CYPRESS:
-        case CHIP_HEMLOCK:
-        case CHIP_JUNIPER:
-        case CHIP_BARTS:
-        default:
-                force_no_swizzle = true;
-                break;
-        }
-        if (force_no_swizzle) {
-                bool last_backend_enabled = false;
-
-                force_no_swizzle = false;
-                for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
-                        if (((enabled_backends_mask >> i) & 1) == 1) {
-                                if (last_backend_enabled)
-                                        force_no_swizzle = true;
-                                last_backend_enabled = true;
-                        } else
-                                last_backend_enabled = false;
-                }
-        }
-
-        switch (num_tile_pipes) {
-        case 1:
-        case 3:
-        case 5:
-        case 7:
-                DRM_ERROR("odd number of pipes!\n");
-                break;
-        case 2:
-                swizzle_pipe[0] = 0;
-                swizzle_pipe[1] = 1;
-                break;
-        case 4:
-                if (force_no_swizzle) {
-                        swizzle_pipe[0] = 0;
-                        swizzle_pipe[1] = 1;
-                        swizzle_pipe[2] = 2;
-                        swizzle_pipe[3] = 3;
-                } else {
-                        swizzle_pipe[0] = 0;
-                        swizzle_pipe[1] = 2;
-                        swizzle_pipe[2] = 1;
-                        swizzle_pipe[3] = 3;
-                }
-                break;
-        case 6:
-                if (force_no_swizzle) {
-                        swizzle_pipe[0] = 0;
-                        swizzle_pipe[1] = 1;
-                        swizzle_pipe[2] = 2;
-                        swizzle_pipe[3] = 3;
-                        swizzle_pipe[4] = 4;
-                        swizzle_pipe[5] = 5;
-                } else {
-                        swizzle_pipe[0] = 0;
-                        swizzle_pipe[1] = 2;
-                        swizzle_pipe[2] = 4;
-                        swizzle_pipe[3] = 1;
-                        swizzle_pipe[4] = 3;
-                        swizzle_pipe[5] = 5;
-                }
-                break;
-        case 8:
-                if (force_no_swizzle) {
-                        swizzle_pipe[0] = 0;
-                        swizzle_pipe[1] = 1;
-                        swizzle_pipe[2] = 2;
-                        swizzle_pipe[3] = 3;
-                        swizzle_pipe[4] = 4;
-                        swizzle_pipe[5] = 5;
-                        swizzle_pipe[6] = 6;
-                        swizzle_pipe[7] = 7;
-                } else {
-                        swizzle_pipe[0] = 0;
-                        swizzle_pipe[1] = 2;
-                        swizzle_pipe[2] = 4;
-                        swizzle_pipe[3] = 6;
-                        swizzle_pipe[4] = 1;
-                        swizzle_pipe[5] = 3;
-                        swizzle_pipe[6] = 5;
-                        swizzle_pipe[7] = 7;
-                }
-                break;
-        }
-
-        for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
-                while (((1 << cur_backend) & enabled_backends_mask) == 0)
-                        cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
-
-                backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4)));
-
-                cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
-        }
-
-        return backend_map;
-}
-
 static void evergreen_gpu_init(struct radeon_device *rdev)
 {
-        u32 cc_rb_backend_disable = 0;
-        u32 cc_gc_shader_pipe_config;
-        u32 gb_addr_config = 0;
+        u32 gb_addr_config;
         u32 mc_shared_chmap, mc_arb_ramcfg;
-        u32 gb_backend_map;
-        u32 grbm_gfx_index;
         u32 sx_debug_1;
         u32 smx_dc_ctl0;
         u32 sq_config;
@@ -1729,6 +1576,7 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
         u32 sq_stack_resource_mgmt_3;
         u32 vgt_cache_invalidation;
         u32 hdp_host_path_cntl, tmp;
+        u32 disabled_rb_mask;
         int i, j, num_shader_engines, ps_thread_count;
 
         switch (rdev->family) {
@@ -1753,6 +1601,7 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
+                gb_addr_config = CYPRESS_GB_ADDR_CONFIG_GOLDEN;
                 break;
         case CHIP_JUNIPER:
                 rdev->config.evergreen.num_ses = 1;
@@ -1774,6 +1623,7 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
+                gb_addr_config = JUNIPER_GB_ADDR_CONFIG_GOLDEN;
                 break;
         case CHIP_REDWOOD:
                 rdev->config.evergreen.num_ses = 1;
@@ -1795,6 +1645,7 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
+                gb_addr_config = REDWOOD_GB_ADDR_CONFIG_GOLDEN;
                 break;
         case CHIP_CEDAR:
         default:
@@ -1817,6 +1668,7 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
+                gb_addr_config = CEDAR_GB_ADDR_CONFIG_GOLDEN;
                 break;
         case CHIP_PALM:
                 rdev->config.evergreen.num_ses = 1;
@@ -1838,6 +1690,7 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
+                gb_addr_config = CEDAR_GB_ADDR_CONFIG_GOLDEN;
                 break;
         case CHIP_SUMO:
                 rdev->config.evergreen.num_ses = 1;
@@ -1865,6 +1718,7 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
+                gb_addr_config = REDWOOD_GB_ADDR_CONFIG_GOLDEN;
                 break;
         case CHIP_SUMO2:
                 rdev->config.evergreen.num_ses = 1;
@@ -1886,6 +1740,7 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
+                gb_addr_config = REDWOOD_GB_ADDR_CONFIG_GOLDEN;
                 break;
         case CHIP_BARTS:
                 rdev->config.evergreen.num_ses = 2;
@@ -1907,6 +1762,7 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
+                gb_addr_config = BARTS_GB_ADDR_CONFIG_GOLDEN;
                 break;
         case CHIP_TURKS:
                 rdev->config.evergreen.num_ses = 1;
@@ -1928,6 +1784,7 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
+                gb_addr_config = TURKS_GB_ADDR_CONFIG_GOLDEN;
                 break;
         case CHIP_CAICOS:
                 rdev->config.evergreen.num_ses = 1;
@@ -1949,6 +1806,7 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
+                gb_addr_config = CAICOS_GB_ADDR_CONFIG_GOLDEN;
                 break;
         }
 
@@ -1965,20 +1823,6 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
 
         evergreen_fix_pci_max_read_req_size(rdev);
 
-        cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & ~2;
-
-        cc_gc_shader_pipe_config |=
-                INACTIVE_QD_PIPES((EVERGREEN_MAX_PIPES_MASK << rdev->config.evergreen.max_pipes)
-                                  & EVERGREEN_MAX_PIPES_MASK);
-        cc_gc_shader_pipe_config |=
-                INACTIVE_SIMDS((EVERGREEN_MAX_SIMDS_MASK << rdev->config.evergreen.max_simds)
-                               & EVERGREEN_MAX_SIMDS_MASK);
-
-        cc_rb_backend_disable =
-                BACKEND_DISABLE((EVERGREEN_MAX_BACKENDS_MASK << rdev->config.evergreen.max_backends)
-                                & EVERGREEN_MAX_BACKENDS_MASK);
-
-
         mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
         if ((rdev->family == CHIP_PALM) ||
             (rdev->family == CHIP_SUMO) ||
@@ -1987,134 +1831,6 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
         else
                 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
 
-        switch (rdev->config.evergreen.max_tile_pipes) {
-        case 1:
-        default:
-                gb_addr_config |= NUM_PIPES(0);
-                break;
-        case 2:
-                gb_addr_config |= NUM_PIPES(1);
-                break;
-        case 4:
-                gb_addr_config |= NUM_PIPES(2);
-                break;
-        case 8:
-                gb_addr_config |= NUM_PIPES(3);
-                break;
-        }
-
-        gb_addr_config |= PIPE_INTERLEAVE_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
-        gb_addr_config |= BANK_INTERLEAVE_SIZE(0);
-        gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.evergreen.num_ses - 1);
-        gb_addr_config |= SHADER_ENGINE_TILE_SIZE(1);
-        gb_addr_config |= NUM_GPUS(0); /* Hemlock? */
-        gb_addr_config |= MULTI_GPU_TILE_SIZE(2);
-
-        if (((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) > 2)
-                gb_addr_config |= ROW_SIZE(2);
-        else
-                gb_addr_config |= ROW_SIZE((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT);
-
-        if (rdev->ddev->pdev->device == 0x689e) {
-                u32 efuse_straps_4;
-                u32 efuse_straps_3;
-                u8 efuse_box_bit_131_124;
-
-                WREG32(RCU_IND_INDEX, 0x204);
-                efuse_straps_4 = RREG32(RCU_IND_DATA);
-                WREG32(RCU_IND_INDEX, 0x203);
-                efuse_straps_3 = RREG32(RCU_IND_DATA);
-                efuse_box_bit_131_124 = (u8)(((efuse_straps_4 & 0xf) << 4) | ((efuse_straps_3 & 0xf0000000) >> 28));
-
-                switch(efuse_box_bit_131_124) {
-                case 0x00:
-                        gb_backend_map = 0x76543210;
-                        break;
-                case 0x55:
-                        gb_backend_map = 0x77553311;
-                        break;
-                case 0x56:
-                        gb_backend_map = 0x77553300;
-                        break;
-                case 0x59:
-                        gb_backend_map = 0x77552211;
-                        break;
-                case 0x66:
-                        gb_backend_map = 0x77443300;
-                        break;
-                case 0x99:
-                        gb_backend_map = 0x66552211;
-                        break;
-                case 0x5a:
-                        gb_backend_map = 0x77552200;
-                        break;
-                case 0xaa:
-                        gb_backend_map = 0x66442200;
-                        break;
-                case 0x95:
-                        gb_backend_map = 0x66553311;
-                        break;
-                default:
-                        DRM_ERROR("bad backend map, using default\n");
-                        gb_backend_map =
-                                evergreen_get_tile_pipe_to_backend_map(rdev,
-                                                                       rdev->config.evergreen.max_tile_pipes,
-                                                                       rdev->config.evergreen.max_backends,
-                                                                       ((EVERGREEN_MAX_BACKENDS_MASK <<
-                                                                   rdev->config.evergreen.max_backends) &
-                                                                        EVERGREEN_MAX_BACKENDS_MASK));
-                        break;
-                }
-        } else if (rdev->ddev->pdev->device == 0x68b9) {
-                u32 efuse_straps_3;
-                u8 efuse_box_bit_127_124;
-
-                WREG32(RCU_IND_INDEX, 0x203);
-                efuse_straps_3 = RREG32(RCU_IND_DATA);
-                efuse_box_bit_127_124 = (u8)((efuse_straps_3 & 0xF0000000) >> 28);
-
-                switch(efuse_box_bit_127_124) {
-                case 0x0:
-                        gb_backend_map = 0x00003210;
-                        break;
-                case 0x5:
-                case 0x6:
-                case 0x9:
-                case 0xa:
-                        gb_backend_map = 0x00003311;
-                        break;
-                default:
-                        DRM_ERROR("bad backend map, using default\n");
-                        gb_backend_map =
-                                evergreen_get_tile_pipe_to_backend_map(rdev,
-                                                                       rdev->config.evergreen.max_tile_pipes,
-                                                                       rdev->config.evergreen.max_backends,
-                                                                       ((EVERGREEN_MAX_BACKENDS_MASK <<
-                                                                   rdev->config.evergreen.max_backends) &
-                                                                        EVERGREEN_MAX_BACKENDS_MASK));
-                        break;
-                }
-        } else {
-                switch (rdev->family) {
-                case CHIP_CYPRESS:
-                case CHIP_HEMLOCK:
-                case CHIP_BARTS:
-                        gb_backend_map = 0x66442200;
-                        break;
-                case CHIP_JUNIPER:
-                        gb_backend_map = 0x00002200;
-                        break;
-                default:
-                        gb_backend_map =
-                                evergreen_get_tile_pipe_to_backend_map(rdev,
-                                                                       rdev->config.evergreen.max_tile_pipes,
-                                                                       rdev->config.evergreen.max_backends,
-                                                                       ((EVERGREEN_MAX_BACKENDS_MASK <<
-                                                                         rdev->config.evergreen.max_backends) &
-                                                                        EVERGREEN_MAX_BACKENDS_MASK));
-                }
-        }
-
         /* setup tiling info dword.  gb_addr_config is not adequate since it does
          * not have bank info, so create a custom tiling dword.
          * bits 3:0   num_pipes
@@ -2147,42 +1863,48 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
                 else
                         rdev->config.evergreen.tile_config |= 0 << 4;
         }
-        rdev->config.evergreen.tile_config |=
-                ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT) << 8;
+        rdev->config.evergreen.tile_config |= 0 << 8;
         rdev->config.evergreen.tile_config |=
                 ((gb_addr_config & 0x30000000) >> 28) << 12;
 
-        rdev->config.evergreen.backend_map = gb_backend_map;
-        WREG32(GB_BACKEND_MAP, gb_backend_map);
-        WREG32(GB_ADDR_CONFIG, gb_addr_config);
-        WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
-        WREG32(HDP_ADDR_CONFIG, gb_addr_config);
-
-        num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1;
-        grbm_gfx_index = INSTANCE_BROADCAST_WRITES;
+        num_shader_engines = (gb_addr_config & NUM_SHADER_ENGINES(3) >> 12) + 1;
 
-        for (i = 0; i < rdev->config.evergreen.num_ses; i++) {
-                u32 rb = cc_rb_backend_disable | (0xf0 << 16);
-                u32 sp = cc_gc_shader_pipe_config;
-                u32 gfx = grbm_gfx_index | SE_INDEX(i);
+        if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK)) {
+                u32 efuse_straps_4;
+                u32 efuse_straps_3;
 
-                if (i == num_shader_engines) {
-                        rb |= BACKEND_DISABLE(EVERGREEN_MAX_BACKENDS_MASK);
-                        sp |= INACTIVE_SIMDS(EVERGREEN_MAX_SIMDS_MASK);
+                WREG32(RCU_IND_INDEX, 0x204);
+                efuse_straps_4 = RREG32(RCU_IND_DATA);
+                WREG32(RCU_IND_INDEX, 0x203);
+                efuse_straps_3 = RREG32(RCU_IND_DATA);
+                tmp = (((efuse_straps_4 & 0xf) << 4) |
+                      ((efuse_straps_3 & 0xf0000000) >> 28));
+        } else {
+                tmp = 0;
+                for (i = (rdev->config.evergreen.num_ses - 1); i >= 0; i--) {
+                        u32 rb_disable_bitmap;
+
+                        WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
+                        WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
+                        rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16;
+                        tmp <<= 4;
+                        tmp |= rb_disable_bitmap;
                 }
+        }
+        /* enabled rb are just the one not disabled :) */
+        disabled_rb_mask = tmp;
 
-                WREG32(GRBM_GFX_INDEX, gfx);
-                WREG32(RLC_GFX_INDEX, gfx);
+        WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
+        WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
 
-                WREG32(CC_RB_BACKEND_DISABLE, rb);
-                WREG32(CC_SYS_RB_BACKEND_DISABLE, rb);
-                WREG32(GC_USER_RB_BACKEND_DISABLE, rb);
-                WREG32(CC_GC_SHADER_PIPE_CONFIG, sp);
-        }
+        WREG32(GB_ADDR_CONFIG, gb_addr_config);
+        WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
+        WREG32(HDP_ADDR_CONFIG, gb_addr_config);
 
-        grbm_gfx_index = INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES;
-        WREG32(GRBM_GFX_INDEX, grbm_gfx_index);
-        WREG32(RLC_GFX_INDEX, grbm_gfx_index);
+        tmp = gb_addr_config & NUM_PIPES_MASK;
+        tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.evergreen.max_backends,
+                                        EVERGREEN_MAX_BACKENDS, disabled_rb_mask);
+        WREG32(GB_BACKEND_MAP, tmp);
 
         WREG32(CGTS_SYS_TCC_DISABLE, 0);
         WREG32(CGTS_TCC_DISABLE, 0);