diff options
author | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2016-05-17 07:01:10 -0400 |
---|---|---|
committer | Tomi Valkeinen <tomi.valkeinen@ti.com> | 2016-05-19 13:19:04 -0400 |
commit | 3b63ca75661decc7db44b492cafbbe60adaf3731 (patch) | |
tree | 9886af34e8f9760292d6330f90e0c169ab821f82 /drivers/gpu/drm/omapdrm | |
parent | 407bd564ed3beec31d82fe10f7c3defcf4f071d8 (diff) |
drm/omap: rename dss_clk_source enums
The names of the enum dss_clk_source's values are legacy names, only
correct for OMAP3 DSS. Rename the names to more generic ones.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Diffstat (limited to 'drivers/gpu/drm/omapdrm')
-rw-r--r-- | drivers/gpu/drm/omapdrm/dss/dispc.c | 12 | ||||
-rw-r--r-- | drivers/gpu/drm/omapdrm/dss/dpi.c | 10 | ||||
-rw-r--r-- | drivers/gpu/drm/omapdrm/dss/dsi.c | 30 | ||||
-rw-r--r-- | drivers/gpu/drm/omapdrm/dss/dss.c | 42 | ||||
-rw-r--r-- | drivers/gpu/drm/omapdrm/dss/dss.h | 15 |
5 files changed, 54 insertions, 55 deletions
diff --git a/drivers/gpu/drm/omapdrm/dss/dispc.c b/drivers/gpu/drm/omapdrm/dss/dispc.c index e3eaae945946..333a347f877b 100644 --- a/drivers/gpu/drm/omapdrm/dss/dispc.c +++ b/drivers/gpu/drm/omapdrm/dss/dispc.c | |||
@@ -3303,17 +3303,17 @@ static unsigned long dispc_fclk_rate(void) | |||
3303 | unsigned long r = 0; | 3303 | unsigned long r = 0; |
3304 | 3304 | ||
3305 | switch (dss_get_dispc_clk_source()) { | 3305 | switch (dss_get_dispc_clk_source()) { |
3306 | case OMAP_DSS_CLK_SRC_FCK: | 3306 | case DSS_CLK_SRC_FCK: |
3307 | r = dss_get_dispc_clk_rate(); | 3307 | r = dss_get_dispc_clk_rate(); |
3308 | break; | 3308 | break; |
3309 | case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC: | 3309 | case DSS_CLK_SRC_PLL1_1: |
3310 | pll = dss_pll_find("dsi0"); | 3310 | pll = dss_pll_find("dsi0"); |
3311 | if (!pll) | 3311 | if (!pll) |
3312 | pll = dss_pll_find("video0"); | 3312 | pll = dss_pll_find("video0"); |
3313 | 3313 | ||
3314 | r = pll->cinfo.clkout[0]; | 3314 | r = pll->cinfo.clkout[0]; |
3315 | break; | 3315 | break; |
3316 | case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC: | 3316 | case DSS_CLK_SRC_PLL2_1: |
3317 | pll = dss_pll_find("dsi1"); | 3317 | pll = dss_pll_find("dsi1"); |
3318 | if (!pll) | 3318 | if (!pll) |
3319 | pll = dss_pll_find("video1"); | 3319 | pll = dss_pll_find("video1"); |
@@ -3341,17 +3341,17 @@ static unsigned long dispc_mgr_lclk_rate(enum omap_channel channel) | |||
3341 | lcd = FLD_GET(l, 23, 16); | 3341 | lcd = FLD_GET(l, 23, 16); |
3342 | 3342 | ||
3343 | switch (dss_get_lcd_clk_source(channel)) { | 3343 | switch (dss_get_lcd_clk_source(channel)) { |
3344 | case OMAP_DSS_CLK_SRC_FCK: | 3344 | case DSS_CLK_SRC_FCK: |
3345 | r = dss_get_dispc_clk_rate(); | 3345 | r = dss_get_dispc_clk_rate(); |
3346 | break; | 3346 | break; |
3347 | case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC: | 3347 | case DSS_CLK_SRC_PLL1_1: |
3348 | pll = dss_pll_find("dsi0"); | 3348 | pll = dss_pll_find("dsi0"); |
3349 | if (!pll) | 3349 | if (!pll) |
3350 | pll = dss_pll_find("video0"); | 3350 | pll = dss_pll_find("video0"); |
3351 | 3351 | ||
3352 | r = pll->cinfo.clkout[0]; | 3352 | r = pll->cinfo.clkout[0]; |
3353 | break; | 3353 | break; |
3354 | case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC: | 3354 | case DSS_CLK_SRC_PLL2_1: |
3355 | pll = dss_pll_find("dsi1"); | 3355 | pll = dss_pll_find("dsi1"); |
3356 | if (!pll) | 3356 | if (!pll) |
3357 | pll = dss_pll_find("video1"); | 3357 | pll = dss_pll_find("video1"); |
diff --git a/drivers/gpu/drm/omapdrm/dss/dpi.c b/drivers/gpu/drm/omapdrm/dss/dpi.c index f2e9638400f2..487d0549bd23 100644 --- a/drivers/gpu/drm/omapdrm/dss/dpi.c +++ b/drivers/gpu/drm/omapdrm/dss/dpi.c | |||
@@ -127,15 +127,15 @@ static enum dss_clk_source dpi_get_alt_clk_src(enum omap_channel channel) | |||
127 | { | 127 | { |
128 | switch (channel) { | 128 | switch (channel) { |
129 | case OMAP_DSS_CHANNEL_LCD: | 129 | case OMAP_DSS_CHANNEL_LCD: |
130 | return OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC; | 130 | return DSS_CLK_SRC_PLL1_1; |
131 | case OMAP_DSS_CHANNEL_LCD2: | 131 | case OMAP_DSS_CHANNEL_LCD2: |
132 | return OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC; | 132 | return DSS_CLK_SRC_PLL2_1; |
133 | case OMAP_DSS_CHANNEL_LCD3: | 133 | case OMAP_DSS_CHANNEL_LCD3: |
134 | return OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC; | 134 | return DSS_CLK_SRC_PLL2_1; |
135 | default: | 135 | default: |
136 | /* this shouldn't happen */ | 136 | /* this shouldn't happen */ |
137 | WARN_ON(1); | 137 | WARN_ON(1); |
138 | return OMAP_DSS_CLK_SRC_FCK; | 138 | return DSS_CLK_SRC_FCK; |
139 | } | 139 | } |
140 | } | 140 | } |
141 | 141 | ||
@@ -465,7 +465,7 @@ static void dpi_display_disable(struct omap_dss_device *dssdev) | |||
465 | dss_mgr_disable(channel); | 465 | dss_mgr_disable(channel); |
466 | 466 | ||
467 | if (dpi->pll) { | 467 | if (dpi->pll) { |
468 | dss_select_lcd_clk_source(channel, OMAP_DSS_CLK_SRC_FCK); | 468 | dss_select_lcd_clk_source(channel, DSS_CLK_SRC_FCK); |
469 | dss_pll_disable(dpi->pll); | 469 | dss_pll_disable(dpi->pll); |
470 | } | 470 | } |
471 | 471 | ||
diff --git a/drivers/gpu/drm/omapdrm/dss/dsi.c b/drivers/gpu/drm/omapdrm/dss/dsi.c index b13257743059..290bd07520f6 100644 --- a/drivers/gpu/drm/omapdrm/dss/dsi.c +++ b/drivers/gpu/drm/omapdrm/dss/dsi.c | |||
@@ -1271,7 +1271,7 @@ static unsigned long dsi_fclk_rate(struct platform_device *dsidev) | |||
1271 | unsigned long r; | 1271 | unsigned long r; |
1272 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | 1272 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
1273 | 1273 | ||
1274 | if (dss_get_dsi_clk_source(dsi->module_id) == OMAP_DSS_CLK_SRC_FCK) { | 1274 | if (dss_get_dsi_clk_source(dsi->module_id) == DSS_CLK_SRC_FCK) { |
1275 | /* DSI FCLK source is DSS_CLK_FCK */ | 1275 | /* DSI FCLK source is DSS_CLK_FCK */ |
1276 | r = clk_get_rate(dsi->dss_clk); | 1276 | r = clk_get_rate(dsi->dss_clk); |
1277 | } else { | 1277 | } else { |
@@ -1505,20 +1505,20 @@ static void dsi_dump_dsidev_clocks(struct platform_device *dsidev, | |||
1505 | 1505 | ||
1506 | seq_printf(s, "DSI_PLL_HSDIV_DISPC (%s)\t%-16lum_dispc %u\t(%s)\n", | 1506 | seq_printf(s, "DSI_PLL_HSDIV_DISPC (%s)\t%-16lum_dispc %u\t(%s)\n", |
1507 | dss_get_clk_source_name(dsi_module == 0 ? | 1507 | dss_get_clk_source_name(dsi_module == 0 ? |
1508 | OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC : | 1508 | DSS_CLK_SRC_PLL1_1 : |
1509 | OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC), | 1509 | DSS_CLK_SRC_PLL2_1), |
1510 | cinfo->clkout[HSDIV_DISPC], | 1510 | cinfo->clkout[HSDIV_DISPC], |
1511 | cinfo->mX[HSDIV_DISPC], | 1511 | cinfo->mX[HSDIV_DISPC], |
1512 | dispc_clk_src == OMAP_DSS_CLK_SRC_FCK ? | 1512 | dispc_clk_src == DSS_CLK_SRC_FCK ? |
1513 | "off" : "on"); | 1513 | "off" : "on"); |
1514 | 1514 | ||
1515 | seq_printf(s, "DSI_PLL_HSDIV_DSI (%s)\t%-16lum_dsi %u\t(%s)\n", | 1515 | seq_printf(s, "DSI_PLL_HSDIV_DSI (%s)\t%-16lum_dsi %u\t(%s)\n", |
1516 | dss_get_clk_source_name(dsi_module == 0 ? | 1516 | dss_get_clk_source_name(dsi_module == 0 ? |
1517 | OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI : | 1517 | DSS_CLK_SRC_PLL1_2 : |
1518 | OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI), | 1518 | DSS_CLK_SRC_PLL2_2), |
1519 | cinfo->clkout[HSDIV_DSI], | 1519 | cinfo->clkout[HSDIV_DSI], |
1520 | cinfo->mX[HSDIV_DSI], | 1520 | cinfo->mX[HSDIV_DSI], |
1521 | dsi_clk_src == OMAP_DSS_CLK_SRC_FCK ? | 1521 | dsi_clk_src == DSS_CLK_SRC_FCK ? |
1522 | "off" : "on"); | 1522 | "off" : "on"); |
1523 | 1523 | ||
1524 | seq_printf(s, "- DSI%d -\n", dsi_module + 1); | 1524 | seq_printf(s, "- DSI%d -\n", dsi_module + 1); |
@@ -4110,8 +4110,8 @@ static int dsi_display_init_dispc(struct platform_device *dsidev, | |||
4110 | int r; | 4110 | int r; |
4111 | 4111 | ||
4112 | dss_select_lcd_clk_source(channel, dsi->module_id == 0 ? | 4112 | dss_select_lcd_clk_source(channel, dsi->module_id == 0 ? |
4113 | OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC : | 4113 | DSS_CLK_SRC_PLL1_1 : |
4114 | OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC); | 4114 | DSS_CLK_SRC_PLL2_1); |
4115 | 4115 | ||
4116 | if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) { | 4116 | if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) { |
4117 | r = dss_mgr_register_framedone_handler(channel, | 4117 | r = dss_mgr_register_framedone_handler(channel, |
@@ -4158,7 +4158,7 @@ err1: | |||
4158 | dss_mgr_unregister_framedone_handler(channel, | 4158 | dss_mgr_unregister_framedone_handler(channel, |
4159 | dsi_framedone_irq_callback, dsidev); | 4159 | dsi_framedone_irq_callback, dsidev); |
4160 | err: | 4160 | err: |
4161 | dss_select_lcd_clk_source(channel, OMAP_DSS_CLK_SRC_FCK); | 4161 | dss_select_lcd_clk_source(channel, DSS_CLK_SRC_FCK); |
4162 | return r; | 4162 | return r; |
4163 | } | 4163 | } |
4164 | 4164 | ||
@@ -4171,7 +4171,7 @@ static void dsi_display_uninit_dispc(struct platform_device *dsidev, | |||
4171 | dss_mgr_unregister_framedone_handler(channel, | 4171 | dss_mgr_unregister_framedone_handler(channel, |
4172 | dsi_framedone_irq_callback, dsidev); | 4172 | dsi_framedone_irq_callback, dsidev); |
4173 | 4173 | ||
4174 | dss_select_lcd_clk_source(channel, OMAP_DSS_CLK_SRC_FCK); | 4174 | dss_select_lcd_clk_source(channel, DSS_CLK_SRC_FCK); |
4175 | } | 4175 | } |
4176 | 4176 | ||
4177 | static int dsi_configure_dsi_clocks(struct platform_device *dsidev) | 4177 | static int dsi_configure_dsi_clocks(struct platform_device *dsidev) |
@@ -4205,8 +4205,8 @@ static int dsi_display_init_dsi(struct platform_device *dsidev) | |||
4205 | goto err1; | 4205 | goto err1; |
4206 | 4206 | ||
4207 | dss_select_dsi_clk_source(dsi->module_id, dsi->module_id == 0 ? | 4207 | dss_select_dsi_clk_source(dsi->module_id, dsi->module_id == 0 ? |
4208 | OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI : | 4208 | DSS_CLK_SRC_PLL1_2 : |
4209 | OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI); | 4209 | DSS_CLK_SRC_PLL2_2); |
4210 | 4210 | ||
4211 | DSSDBG("PLL OK\n"); | 4211 | DSSDBG("PLL OK\n"); |
4212 | 4212 | ||
@@ -4238,7 +4238,7 @@ static int dsi_display_init_dsi(struct platform_device *dsidev) | |||
4238 | err3: | 4238 | err3: |
4239 | dsi_cio_uninit(dsidev); | 4239 | dsi_cio_uninit(dsidev); |
4240 | err2: | 4240 | err2: |
4241 | dss_select_dsi_clk_source(dsi->module_id, OMAP_DSS_CLK_SRC_FCK); | 4241 | dss_select_dsi_clk_source(dsi->module_id, DSS_CLK_SRC_FCK); |
4242 | err1: | 4242 | err1: |
4243 | dss_pll_disable(&dsi->pll); | 4243 | dss_pll_disable(&dsi->pll); |
4244 | err0: | 4244 | err0: |
@@ -4260,7 +4260,7 @@ static void dsi_display_uninit_dsi(struct platform_device *dsidev, | |||
4260 | dsi_vc_enable(dsidev, 2, 0); | 4260 | dsi_vc_enable(dsidev, 2, 0); |
4261 | dsi_vc_enable(dsidev, 3, 0); | 4261 | dsi_vc_enable(dsidev, 3, 0); |
4262 | 4262 | ||
4263 | dss_select_dsi_clk_source(dsi->module_id, OMAP_DSS_CLK_SRC_FCK); | 4263 | dss_select_dsi_clk_source(dsi->module_id, DSS_CLK_SRC_FCK); |
4264 | dsi_cio_uninit(dsidev); | 4264 | dsi_cio_uninit(dsidev); |
4265 | dsi_pll_uninit(dsidev, disconnect_lanes); | 4265 | dsi_pll_uninit(dsidev, disconnect_lanes); |
4266 | } | 4266 | } |
diff --git a/drivers/gpu/drm/omapdrm/dss/dss.c b/drivers/gpu/drm/omapdrm/dss/dss.c index 9de30ff4f537..58d20530059a 100644 --- a/drivers/gpu/drm/omapdrm/dss/dss.c +++ b/drivers/gpu/drm/omapdrm/dss/dss.c | |||
@@ -105,11 +105,11 @@ static struct { | |||
105 | } dss; | 105 | } dss; |
106 | 106 | ||
107 | static const char * const dss_generic_clk_source_names[] = { | 107 | static const char * const dss_generic_clk_source_names[] = { |
108 | [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "DSI_PLL_HSDIV_DISPC", | 108 | [DSS_CLK_SRC_FCK] = "FCK", |
109 | [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "DSI_PLL_HSDIV_DSI", | 109 | [DSS_CLK_SRC_PLL1_1] = "PLL1:1", |
110 | [OMAP_DSS_CLK_SRC_FCK] = "DSS_FCK", | 110 | [DSS_CLK_SRC_PLL1_2] = "PLL1:2", |
111 | [OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC] = "DSI_PLL2_HSDIV_DISPC", | 111 | [DSS_CLK_SRC_PLL2_1] = "PLL2:1", |
112 | [OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI] = "DSI_PLL2_HSDIV_DSI", | 112 | [DSS_CLK_SRC_PLL2_2] = "PLL2:2", |
113 | }; | 113 | }; |
114 | 114 | ||
115 | static bool dss_initialized; | 115 | static bool dss_initialized; |
@@ -368,7 +368,7 @@ void dss_dump_clocks(struct seq_file *s) | |||
368 | 368 | ||
369 | seq_printf(s, "- DSS -\n"); | 369 | seq_printf(s, "- DSS -\n"); |
370 | 370 | ||
371 | fclk_name = dss_get_clk_source_name(OMAP_DSS_CLK_SRC_FCK); | 371 | fclk_name = dss_get_clk_source_name(DSS_CLK_SRC_FCK); |
372 | fclk_rate = clk_get_rate(dss.dss_clk); | 372 | fclk_rate = clk_get_rate(dss.dss_clk); |
373 | 373 | ||
374 | seq_printf(s, "%s = %lu\n", | 374 | seq_printf(s, "%s = %lu\n", |
@@ -407,13 +407,13 @@ static void dss_select_dispc_clk_source(enum dss_clk_source clk_src) | |||
407 | u8 start, end; | 407 | u8 start, end; |
408 | 408 | ||
409 | switch (clk_src) { | 409 | switch (clk_src) { |
410 | case OMAP_DSS_CLK_SRC_FCK: | 410 | case DSS_CLK_SRC_FCK: |
411 | b = 0; | 411 | b = 0; |
412 | break; | 412 | break; |
413 | case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC: | 413 | case DSS_CLK_SRC_PLL1_1: |
414 | b = 1; | 414 | b = 1; |
415 | break; | 415 | break; |
416 | case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC: | 416 | case DSS_CLK_SRC_PLL2_1: |
417 | b = 2; | 417 | b = 2; |
418 | break; | 418 | break; |
419 | default: | 419 | default: |
@@ -434,14 +434,14 @@ void dss_select_dsi_clk_source(int dsi_module, | |||
434 | int b, pos; | 434 | int b, pos; |
435 | 435 | ||
436 | switch (clk_src) { | 436 | switch (clk_src) { |
437 | case OMAP_DSS_CLK_SRC_FCK: | 437 | case DSS_CLK_SRC_FCK: |
438 | b = 0; | 438 | b = 0; |
439 | break; | 439 | break; |
440 | case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI: | 440 | case DSS_CLK_SRC_PLL1_2: |
441 | BUG_ON(dsi_module != 0); | 441 | BUG_ON(dsi_module != 0); |
442 | b = 1; | 442 | b = 1; |
443 | break; | 443 | break; |
444 | case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI: | 444 | case DSS_CLK_SRC_PLL2_2: |
445 | BUG_ON(dsi_module != 1); | 445 | BUG_ON(dsi_module != 1); |
446 | b = 1; | 446 | b = 1; |
447 | break; | 447 | break; |
@@ -467,14 +467,14 @@ void dss_select_lcd_clk_source(enum omap_channel channel, | |||
467 | } | 467 | } |
468 | 468 | ||
469 | switch (clk_src) { | 469 | switch (clk_src) { |
470 | case OMAP_DSS_CLK_SRC_FCK: | 470 | case DSS_CLK_SRC_FCK: |
471 | b = 0; | 471 | b = 0; |
472 | break; | 472 | break; |
473 | case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC: | 473 | case DSS_CLK_SRC_PLL1_1: |
474 | BUG_ON(channel != OMAP_DSS_CHANNEL_LCD); | 474 | BUG_ON(channel != OMAP_DSS_CHANNEL_LCD); |
475 | b = 1; | 475 | b = 1; |
476 | break; | 476 | break; |
477 | case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC: | 477 | case DSS_CLK_SRC_PLL2_1: |
478 | BUG_ON(channel != OMAP_DSS_CHANNEL_LCD2 && | 478 | BUG_ON(channel != OMAP_DSS_CHANNEL_LCD2 && |
479 | channel != OMAP_DSS_CHANNEL_LCD3); | 479 | channel != OMAP_DSS_CHANNEL_LCD3); |
480 | b = 1; | 480 | b = 1; |
@@ -1141,18 +1141,18 @@ static int dss_bind(struct device *dev) | |||
1141 | /* Select DPLL */ | 1141 | /* Select DPLL */ |
1142 | REG_FLD_MOD(DSS_CONTROL, 0, 0, 0); | 1142 | REG_FLD_MOD(DSS_CONTROL, 0, 0, 0); |
1143 | 1143 | ||
1144 | dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK); | 1144 | dss_select_dispc_clk_source(DSS_CLK_SRC_FCK); |
1145 | 1145 | ||
1146 | #ifdef CONFIG_OMAP2_DSS_VENC | 1146 | #ifdef CONFIG_OMAP2_DSS_VENC |
1147 | REG_FLD_MOD(DSS_CONTROL, 1, 4, 4); /* venc dac demen */ | 1147 | REG_FLD_MOD(DSS_CONTROL, 1, 4, 4); /* venc dac demen */ |
1148 | REG_FLD_MOD(DSS_CONTROL, 1, 3, 3); /* venc clock 4x enable */ | 1148 | REG_FLD_MOD(DSS_CONTROL, 1, 3, 3); /* venc clock 4x enable */ |
1149 | REG_FLD_MOD(DSS_CONTROL, 0, 2, 2); /* venc clock mode = normal */ | 1149 | REG_FLD_MOD(DSS_CONTROL, 0, 2, 2); /* venc clock mode = normal */ |
1150 | #endif | 1150 | #endif |
1151 | dss.dsi_clk_source[0] = OMAP_DSS_CLK_SRC_FCK; | 1151 | dss.dsi_clk_source[0] = DSS_CLK_SRC_FCK; |
1152 | dss.dsi_clk_source[1] = OMAP_DSS_CLK_SRC_FCK; | 1152 | dss.dsi_clk_source[1] = DSS_CLK_SRC_FCK; |
1153 | dss.dispc_clk_source = OMAP_DSS_CLK_SRC_FCK; | 1153 | dss.dispc_clk_source = DSS_CLK_SRC_FCK; |
1154 | dss.lcd_clk_source[0] = OMAP_DSS_CLK_SRC_FCK; | 1154 | dss.lcd_clk_source[0] = DSS_CLK_SRC_FCK; |
1155 | dss.lcd_clk_source[1] = OMAP_DSS_CLK_SRC_FCK; | 1155 | dss.lcd_clk_source[1] = DSS_CLK_SRC_FCK; |
1156 | 1156 | ||
1157 | rev = dss_read_reg(DSS_REVISION); | 1157 | rev = dss_read_reg(DSS_REVISION); |
1158 | printk(KERN_INFO "OMAP DSS rev %d.%d\n", | 1158 | printk(KERN_INFO "OMAP DSS rev %d.%d\n", |
diff --git a/drivers/gpu/drm/omapdrm/dss/dss.h b/drivers/gpu/drm/omapdrm/dss/dss.h index 5c54c9a808de..56c2d277341a 100644 --- a/drivers/gpu/drm/omapdrm/dss/dss.h +++ b/drivers/gpu/drm/omapdrm/dss/dss.h | |||
@@ -103,14 +103,13 @@ enum dss_writeback_channel { | |||
103 | }; | 103 | }; |
104 | 104 | ||
105 | enum dss_clk_source { | 105 | enum dss_clk_source { |
106 | OMAP_DSS_CLK_SRC_FCK = 0, /* OMAP2/3: DSS1_ALWON_FCLK | 106 | DSS_CLK_SRC_FCK = 0, |
107 | * OMAP4: DSS_FCLK */ | 107 | |
108 | OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, /* OMAP3: DSI1_PLL_FCLK | 108 | DSS_CLK_SRC_PLL1_1, |
109 | * OMAP4: PLL1_CLK1 */ | 109 | DSS_CLK_SRC_PLL1_2, |
110 | OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, /* OMAP3: DSI2_PLL_FCLK | 110 | |
111 | * OMAP4: PLL1_CLK2 */ | 111 | DSS_CLK_SRC_PLL2_1, |
112 | OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC, /* OMAP4: PLL2_CLK1 */ | 112 | DSS_CLK_SRC_PLL2_2, |
113 | OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI, /* OMAP4: PLL2_CLK2 */ | ||
114 | }; | 113 | }; |
115 | 114 | ||
116 | enum dss_pll_id { | 115 | enum dss_pll_id { |