diff options
author | Ben Skeggs <bskeggs@redhat.com> | 2014-08-09 14:10:26 -0400 |
---|---|---|
committer | Ben Skeggs <bskeggs@redhat.com> | 2014-08-09 15:28:07 -0400 |
commit | bf0eb89859439f016a1fab4cdf737c95f36dbb2e (patch) | |
tree | 59709bbd702fe904e63a2237d200162f90d820b4 /drivers/gpu/drm/nouveau/nvif/class.h | |
parent | 2c04ae01df38f95dd3e553c85cdac670a80110f5 (diff) |
drm/nv50-/disp: audit and version DAC_PWR method
The full object interfaces are about to be exposed to userspace, so we
need to check for any security-related issues and version the structs
to make it easier to handle any changes we may need in the future.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nvif/class.h')
-rw-r--r-- | drivers/gpu/drm/nouveau/nvif/class.h | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/nvif/class.h b/drivers/gpu/drm/nouveau/nvif/class.h index 50c5413ff523..9681a102970d 100644 --- a/drivers/gpu/drm/nouveau/nvif/class.h +++ b/drivers/gpu/drm/nouveau/nvif/class.h | |||
@@ -290,4 +290,47 @@ struct kepler_channel_gpfifo_a_v0 { | |||
290 | __u64 ioffset; | 290 | __u64 ioffset; |
291 | }; | 291 | }; |
292 | 292 | ||
293 | /******************************************************************************* | ||
294 | * legacy display | ||
295 | ******************************************************************************/ | ||
296 | |||
297 | |||
298 | /******************************************************************************* | ||
299 | * display | ||
300 | ******************************************************************************/ | ||
301 | |||
302 | #define NV50_DISP_MTHD 0x00 | ||
303 | |||
304 | struct nv50_disp_mthd_v0 { | ||
305 | __u8 version; | ||
306 | __u8 method; | ||
307 | __u8 head; | ||
308 | __u8 pad03[5]; | ||
309 | }; | ||
310 | |||
311 | struct nv50_disp_mthd_v1 { | ||
312 | __u8 version; | ||
313 | #define NV50_DISP_MTHD_V1_DAC_PWR 0x10 | ||
314 | #define NV50_DISP_MTHD_V1_DAC_LOAD 0x11 | ||
315 | #define NV50_DISP_MTHD_V1_SOR_PWR 0x20 | ||
316 | #define NV50_DISP_MTHD_V1_SOR_HDA_ELD 0x21 | ||
317 | #define NV50_DISP_MTHD_V1_SOR_HDMI_PWR 0x22 | ||
318 | #define NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT 0x23 | ||
319 | #define NV50_DISP_MTHD_V1_SOR_DP_PWR 0x24 | ||
320 | #define NV50_DISP_MTHD_V1_PIOR_PWR 0x30 | ||
321 | __u8 method; | ||
322 | __u16 hasht; | ||
323 | __u16 hashm; | ||
324 | __u8 pad06[2]; | ||
325 | }; | ||
326 | |||
327 | struct nv50_disp_dac_pwr_v0 { | ||
328 | __u8 version; | ||
329 | __u8 state; | ||
330 | __u8 data; | ||
331 | __u8 vsync; | ||
332 | __u8 hsync; | ||
333 | __u8 pad05[3]; | ||
334 | }; | ||
335 | |||
293 | #endif | 336 | #endif |