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authorBen Skeggs <bskeggs@redhat.com>2012-07-04 09:44:54 -0400
committerBen Skeggs <bskeggs@redhat.com>2012-10-02 23:12:43 -0400
commit02a841d434513c7b3620250271c372fabce56de5 (patch)
tree464e7651bc65e8b100ad9eb949729da3d491591a /drivers/gpu/drm/nouveau/nv31_mpeg.c
parent3a92d37e4099054fe187b485a9d27c439c10eca7 (diff)
drm/nouveau: restructure source tree, split core from drm implementation
Future work will be headed in the way of separating the policy supplied by the nouveau drm module from the mechanisms provided by the driver core. There will be a couple of major classes (subdev, engine) of driver modules that have clearly defined tasks, and the further directory structure change is to reflect this. No code changes here whatsoever, aside from fixing up a couple of include file pathnames. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nv31_mpeg.c')
-rw-r--r--drivers/gpu/drm/nouveau/nv31_mpeg.c346
1 files changed, 0 insertions, 346 deletions
diff --git a/drivers/gpu/drm/nouveau/nv31_mpeg.c b/drivers/gpu/drm/nouveau/nv31_mpeg.c
deleted file mode 100644
index 5f239bf658c4..000000000000
--- a/drivers/gpu/drm/nouveau/nv31_mpeg.c
+++ /dev/null
@@ -1,346 +0,0 @@
1/*
2 * Copyright 2011 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include "drmP.h"
26#include "nouveau_drv.h"
27#include "nouveau_fifo.h"
28#include "nouveau_ramht.h"
29
30struct nv31_mpeg_engine {
31 struct nouveau_exec_engine base;
32 atomic_t refcount;
33};
34
35
36static int
37nv31_mpeg_context_new(struct nouveau_channel *chan, int engine)
38{
39 struct nv31_mpeg_engine *pmpeg = nv_engine(chan->dev, engine);
40
41 if (!atomic_add_unless(&pmpeg->refcount, 1, 1))
42 return -EBUSY;
43
44 chan->engctx[engine] = (void *)0xdeadcafe;
45 return 0;
46}
47
48static void
49nv31_mpeg_context_del(struct nouveau_channel *chan, int engine)
50{
51 struct nv31_mpeg_engine *pmpeg = nv_engine(chan->dev, engine);
52 atomic_dec(&pmpeg->refcount);
53 chan->engctx[engine] = NULL;
54}
55
56static int
57nv40_mpeg_context_new(struct nouveau_channel *chan, int engine)
58{
59 struct drm_device *dev = chan->dev;
60 struct drm_nouveau_private *dev_priv = dev->dev_private;
61 struct nouveau_gpuobj *ctx = NULL;
62 unsigned long flags;
63 int ret;
64
65 NV_DEBUG(dev, "ch%d\n", chan->id);
66
67 ret = nouveau_gpuobj_new(dev, NULL, 264 * 4, 16, NVOBJ_FLAG_ZERO_ALLOC |
68 NVOBJ_FLAG_ZERO_FREE, &ctx);
69 if (ret)
70 return ret;
71
72 nv_wo32(ctx, 0x78, 0x02001ec1);
73
74 spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
75 nv_mask(dev, 0x002500, 0x00000001, 0x00000000);
76 if ((nv_rd32(dev, 0x003204) & 0x1f) == chan->id)
77 nv_wr32(dev, 0x00330c, ctx->pinst >> 4);
78 nv_wo32(chan->ramfc, 0x54, ctx->pinst >> 4);
79 nv_mask(dev, 0x002500, 0x00000001, 0x00000001);
80 spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
81
82 chan->engctx[engine] = ctx;
83 return 0;
84}
85
86static void
87nv40_mpeg_context_del(struct nouveau_channel *chan, int engine)
88{
89 struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
90 struct nouveau_gpuobj *ctx = chan->engctx[engine];
91 struct drm_device *dev = chan->dev;
92 unsigned long flags;
93 u32 inst = 0x80000000 | (ctx->pinst >> 4);
94
95 spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
96 nv_mask(dev, 0x00b32c, 0x00000001, 0x00000000);
97 if (nv_rd32(dev, 0x00b318) == inst)
98 nv_mask(dev, 0x00b318, 0x80000000, 0x00000000);
99 nv_mask(dev, 0x00b32c, 0x00000001, 0x00000001);
100 spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
101
102 nouveau_gpuobj_ref(NULL, &ctx);
103 chan->engctx[engine] = NULL;
104}
105
106static int
107nv31_mpeg_object_new(struct nouveau_channel *chan, int engine,
108 u32 handle, u16 class)
109{
110 struct drm_device *dev = chan->dev;
111 struct nouveau_gpuobj *obj = NULL;
112 int ret;
113
114 ret = nouveau_gpuobj_new(dev, chan, 20, 16, NVOBJ_FLAG_ZERO_ALLOC |
115 NVOBJ_FLAG_ZERO_FREE, &obj);
116 if (ret)
117 return ret;
118 obj->engine = 2;
119 obj->class = class;
120
121 nv_wo32(obj, 0x00, class);
122
123 ret = nouveau_ramht_insert(chan, handle, obj);
124 nouveau_gpuobj_ref(NULL, &obj);
125 return ret;
126}
127
128static int
129nv31_mpeg_init(struct drm_device *dev, int engine)
130{
131 struct drm_nouveau_private *dev_priv = dev->dev_private;
132 struct nv31_mpeg_engine *pmpeg = nv_engine(dev, engine);
133 int i;
134
135 /* VPE init */
136 nv_mask(dev, 0x000200, 0x00000002, 0x00000000);
137 nv_mask(dev, 0x000200, 0x00000002, 0x00000002);
138 nv_wr32(dev, 0x00b0e0, 0x00000020); /* nvidia: rd 0x01, wr 0x20 */
139 nv_wr32(dev, 0x00b0e8, 0x00000020); /* nvidia: rd 0x01, wr 0x20 */
140
141 for (i = 0; i < dev_priv->engine.fb.num_tiles; i++)
142 pmpeg->base.set_tile_region(dev, i);
143
144 /* PMPEG init */
145 nv_wr32(dev, 0x00b32c, 0x00000000);
146 nv_wr32(dev, 0x00b314, 0x00000100);
147 nv_wr32(dev, 0x00b220, nv44_graph_class(dev) ? 0x00000044 : 0x00000031);
148 nv_wr32(dev, 0x00b300, 0x02001ec1);
149 nv_mask(dev, 0x00b32c, 0x00000001, 0x00000001);
150
151 nv_wr32(dev, 0x00b100, 0xffffffff);
152 nv_wr32(dev, 0x00b140, 0xffffffff);
153
154 if (!nv_wait(dev, 0x00b200, 0x00000001, 0x00000000)) {
155 NV_ERROR(dev, "PMPEG init: 0x%08x\n", nv_rd32(dev, 0x00b200));
156 return -EBUSY;
157 }
158
159 return 0;
160}
161
162static int
163nv31_mpeg_fini(struct drm_device *dev, int engine, bool suspend)
164{
165 /*XXX: context save? */
166 nv_mask(dev, 0x00b32c, 0x00000001, 0x00000000);
167 nv_wr32(dev, 0x00b140, 0x00000000);
168 return 0;
169}
170
171static int
172nv31_mpeg_mthd_dma(struct nouveau_channel *chan, u32 class, u32 mthd, u32 data)
173{
174 struct drm_device *dev = chan->dev;
175 u32 inst = data << 4;
176 u32 dma0 = nv_ri32(dev, inst + 0);
177 u32 dma1 = nv_ri32(dev, inst + 4);
178 u32 dma2 = nv_ri32(dev, inst + 8);
179 u32 base = (dma2 & 0xfffff000) | (dma0 >> 20);
180 u32 size = dma1 + 1;
181
182 /* only allow linear DMA objects */
183 if (!(dma0 & 0x00002000))
184 return -EINVAL;
185
186 if (mthd == 0x0190) {
187 /* DMA_CMD */
188 nv_mask(dev, 0x00b300, 0x00030000, (dma0 & 0x00030000));
189 nv_wr32(dev, 0x00b334, base);
190 nv_wr32(dev, 0x00b324, size);
191 } else
192 if (mthd == 0x01a0) {
193 /* DMA_DATA */
194 nv_mask(dev, 0x00b300, 0x000c0000, (dma0 & 0x00030000) << 2);
195 nv_wr32(dev, 0x00b360, base);
196 nv_wr32(dev, 0x00b364, size);
197 } else {
198 /* DMA_IMAGE, VRAM only */
199 if (dma0 & 0x000c0000)
200 return -EINVAL;
201
202 nv_wr32(dev, 0x00b370, base);
203 nv_wr32(dev, 0x00b374, size);
204 }
205
206 return 0;
207}
208
209static int
210nv31_mpeg_isr_chid(struct drm_device *dev, u32 inst)
211{
212 struct nouveau_fifo_priv *pfifo = nv_engine(dev, NVOBJ_ENGINE_FIFO);
213 struct drm_nouveau_private *dev_priv = dev->dev_private;
214 struct nouveau_gpuobj *ctx;
215 unsigned long flags;
216 int i;
217
218 /* hardcode drm channel id on nv3x, so swmthd lookup works */
219 if (dev_priv->card_type < NV_40)
220 return 0;
221
222 spin_lock_irqsave(&dev_priv->channels.lock, flags);
223 for (i = 0; i < pfifo->channels; i++) {
224 if (!dev_priv->channels.ptr[i])
225 continue;
226
227 ctx = dev_priv->channels.ptr[i]->engctx[NVOBJ_ENGINE_MPEG];
228 if (ctx && ctx->pinst == inst)
229 break;
230 }
231 spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
232 return i;
233}
234
235static void
236nv31_vpe_set_tile_region(struct drm_device *dev, int i)
237{
238 struct drm_nouveau_private *dev_priv = dev->dev_private;
239 struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
240
241 nv_wr32(dev, 0x00b008 + (i * 0x10), tile->pitch);
242 nv_wr32(dev, 0x00b004 + (i * 0x10), tile->limit);
243 nv_wr32(dev, 0x00b000 + (i * 0x10), tile->addr);
244}
245
246static void
247nv31_mpeg_isr(struct drm_device *dev)
248{
249 u32 inst = (nv_rd32(dev, 0x00b318) & 0x000fffff) << 4;
250 u32 chid = nv31_mpeg_isr_chid(dev, inst);
251 u32 stat = nv_rd32(dev, 0x00b100);
252 u32 type = nv_rd32(dev, 0x00b230);
253 u32 mthd = nv_rd32(dev, 0x00b234);
254 u32 data = nv_rd32(dev, 0x00b238);
255 u32 show = stat;
256
257 if (stat & 0x01000000) {
258 /* happens on initial binding of the object */
259 if (type == 0x00000020 && mthd == 0x0000) {
260 nv_mask(dev, 0x00b308, 0x00000000, 0x00000000);
261 show &= ~0x01000000;
262 }
263
264 if (type == 0x00000010) {
265 if (!nouveau_gpuobj_mthd_call2(dev, chid, 0x3174, mthd, data))
266 show &= ~0x01000000;
267 }
268 }
269
270 nv_wr32(dev, 0x00b100, stat);
271 nv_wr32(dev, 0x00b230, 0x00000001);
272
273 if (show && nouveau_ratelimit()) {
274 NV_INFO(dev, "PMPEG: Ch %d [0x%08x] 0x%08x 0x%08x 0x%08x 0x%08x\n",
275 chid, inst, stat, type, mthd, data);
276 }
277}
278
279static void
280nv31_vpe_isr(struct drm_device *dev)
281{
282 if (nv_rd32(dev, 0x00b100))
283 nv31_mpeg_isr(dev);
284
285 if (nv_rd32(dev, 0x00b800)) {
286 u32 stat = nv_rd32(dev, 0x00b800);
287 NV_INFO(dev, "PMSRCH: 0x%08x\n", stat);
288 nv_wr32(dev, 0xb800, stat);
289 }
290}
291
292static void
293nv31_mpeg_destroy(struct drm_device *dev, int engine)
294{
295 struct nv31_mpeg_engine *pmpeg = nv_engine(dev, engine);
296
297 nouveau_irq_unregister(dev, 0);
298
299 NVOBJ_ENGINE_DEL(dev, MPEG);
300 kfree(pmpeg);
301}
302
303int
304nv31_mpeg_create(struct drm_device *dev)
305{
306 struct drm_nouveau_private *dev_priv = dev->dev_private;
307 struct nv31_mpeg_engine *pmpeg;
308
309 pmpeg = kzalloc(sizeof(*pmpeg), GFP_KERNEL);
310 if (!pmpeg)
311 return -ENOMEM;
312 atomic_set(&pmpeg->refcount, 0);
313
314 pmpeg->base.destroy = nv31_mpeg_destroy;
315 pmpeg->base.init = nv31_mpeg_init;
316 pmpeg->base.fini = nv31_mpeg_fini;
317 if (dev_priv->card_type < NV_40) {
318 pmpeg->base.context_new = nv31_mpeg_context_new;
319 pmpeg->base.context_del = nv31_mpeg_context_del;
320 } else {
321 pmpeg->base.context_new = nv40_mpeg_context_new;
322 pmpeg->base.context_del = nv40_mpeg_context_del;
323 }
324 pmpeg->base.object_new = nv31_mpeg_object_new;
325
326 /* ISR vector, PMC_ENABLE bit, and TILE regs are shared between
327 * all VPE engines, for this driver's purposes the PMPEG engine
328 * will be treated as the "master" and handle the global VPE
329 * bits too
330 */
331 pmpeg->base.set_tile_region = nv31_vpe_set_tile_region;
332 nouveau_irq_register(dev, 0, nv31_vpe_isr);
333
334 NVOBJ_ENGINE_ADD(dev, MPEG, &pmpeg->base);
335 NVOBJ_CLASS(dev, 0x3174, MPEG);
336 NVOBJ_MTHD (dev, 0x3174, 0x0190, nv31_mpeg_mthd_dma);
337 NVOBJ_MTHD (dev, 0x3174, 0x01a0, nv31_mpeg_mthd_dma);
338 NVOBJ_MTHD (dev, 0x3174, 0x01b0, nv31_mpeg_mthd_dma);
339
340#if 0
341 NVOBJ_ENGINE_ADD(dev, ME, &pme->base);
342 NVOBJ_CLASS(dev, 0x4075, ME);
343#endif
344 return 0;
345
346}
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