drm/nouveau: initial pass at moving to struct nvif_device

This is an attempt at isolating some of the changes necessary to port
to NVIF in a separate commit.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

13 files changed, 124 insertions, 124 deletions

diff --git a/drivers/gpu/drm/nouveau/dispnv04/arb.c b/drivers/gpu/drm/nouveau/dispnv04/arb.c
index c64db854cc26..c6361422a0b2 100644
--- a/drivers/gpu/drm/nouveau/dispnv04/arb.c
+++ b/drivers/gpu/drm/nouveau/dispnv04/arb.c
@@ -198,7 +198,7 @@ nv04_update_arb(struct drm_device *dev, int VClk, int bpp,
                 int *burst, int *lwm)
 {
         struct nouveau_drm *drm = nouveau_drm(dev);
-        struct nouveau_object *device = nouveau_drm(dev)->device;
+        struct nvif_device *device = &nouveau_drm(dev)->device;
         struct nv_fifo_info fifo_data;
         struct nv_sim_state sim_data;
         int MClk = nouveau_hw_get_clock(dev, PLL_MEMORY);
@@ -227,7 +227,7 @@ nv04_update_arb(struct drm_device *dev, int VClk, int bpp,
                 sim_data.mem_page_miss = ((cfg1 >> 4) & 0xf) + ((cfg1 >> 31) & 0x1);
         }
 
-        if (nv_device(drm->device)->card_type == NV_04)
+        if (drm->device.info.family == NV_DEVICE_INFO_V0_TNT)
                 nv04_calc_arb(&fifo_data, &sim_data);
         else
                 nv10_calc_arb(&fifo_data, &sim_data);
@@ -254,7 +254,7 @@ nouveau_calc_arb(struct drm_device *dev, int vclk, int bpp, int *burst, int *lwm
 {
         struct nouveau_drm *drm = nouveau_drm(dev);
 
-        if (nv_device(drm->device)->card_type < NV_20)
+        if (drm->device.info.family < NV_DEVICE_INFO_V0_KELVIN)
                 nv04_update_arb(dev, vclk, bpp, burst, lwm);
         else if ((dev->pdev->device & 0xfff0) == 0x0240 /*CHIPSET_C51*/ ||
                  (dev->pdev->device & 0xfff0) == 0x03d0 /*CHIPSET_C512*/) {
diff --git a/drivers/gpu/drm/nouveau/dispnv04/crtc.c b/drivers/gpu/drm/nouveau/dispnv04/crtc.c
index 8b17d7d49e26..b90aa5c1f90a 100644
--- a/drivers/gpu/drm/nouveau/dispnv04/crtc.c
+++ b/drivers/gpu/drm/nouveau/dispnv04/crtc.c
@@ -111,8 +111,8 @@ static void nv_crtc_calc_state_ext(struct drm_crtc *crtc, struct drm_display_mod
 {
         struct drm_device *dev = crtc->dev;
         struct nouveau_drm *drm = nouveau_drm(dev);
-        struct nouveau_bios *bios = nouveau_bios(drm->device);
-        struct nouveau_clock *clk = nouveau_clock(drm->device);
+        struct nouveau_bios *bios = nvkm_bios(&drm->device);
+        struct nouveau_clock *clk = nvkm_clock(&drm->device);
         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
         struct nv04_mode_state *state = &nv04_display(dev)->mode_reg;
         struct nv04_crtc_reg *regp = &state->crtc_reg[nv_crtc->index];
@@ -136,7 +136,7 @@ static void nv_crtc_calc_state_ext(struct drm_crtc *crtc, struct drm_display_mod
          * has yet been observed in allowing the use a single stage pll on all
          * nv43 however.  the behaviour of single stage use is untested on nv40
          */
-        if (nv_device(drm->device)->chipset > 0x40 && dot_clock <= (pll_lim.vco1.max_freq / 2))
+        if (drm->device.info.chipset > 0x40 && dot_clock <= (pll_lim.vco1.max_freq / 2))
                 memset(&pll_lim.vco2, 0, sizeof(pll_lim.vco2));
 
 
@@ -146,10 +146,10 @@ static void nv_crtc_calc_state_ext(struct drm_crtc *crtc, struct drm_display_mod
         state->pllsel &= PLLSEL_VPLL1_MASK | PLLSEL_VPLL2_MASK | PLLSEL_TV_MASK;
 
         /* The blob uses this always, so let's do the same */
-        if (nv_device(drm->device)->card_type == NV_40)
+        if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE)
                 state->pllsel |= NV_PRAMDAC_PLL_COEFF_SELECT_USE_VPLL2_TRUE;
         /* again nv40 and some nv43 act more like nv3x as described above */
-        if (nv_device(drm->device)->chipset < 0x41)
+        if (drm->device.info.chipset < 0x41)
                 state->pllsel |= NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_MPLL |
                                  NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_NVPLL;
         state->pllsel |= nv_crtc->index ? PLLSEL_VPLL2_MASK : PLLSEL_VPLL1_MASK;
@@ -275,7 +275,7 @@ nv_crtc_mode_set_vga(struct drm_crtc *crtc, struct drm_display_mode *mode)
                 horizEnd = horizTotal - 2;
                 horizBlankEnd = horizTotal + 4;
 #if 0
-                if (dev->overlayAdaptor && nv_device(drm->device)->card_type >= NV_10)
+                if (dev->overlayAdaptor && drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS)
                         /* This reportedly works around some video overlay bandwidth problems */
                         horizTotal += 2;
 #endif
@@ -509,7 +509,7 @@ nv_crtc_mode_set_regs(struct drm_crtc *crtc, struct drm_display_mode * mode)
         regp->cursor_cfg = NV_PCRTC_CURSOR_CONFIG_CUR_LINES_64 |
                              NV_PCRTC_CURSOR_CONFIG_CUR_PIXELS_64 |
                              NV_PCRTC_CURSOR_CONFIG_ADDRESS_SPACE_PNVM;
-        if (nv_device(drm->device)->chipset >= 0x11)
+        if (drm->device.info.chipset >= 0x11)
                 regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_CUR_BPP_32;
         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
                 regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_DOUBLE_SCAN_ENABLE;
@@ -550,26 +550,26 @@ nv_crtc_mode_set_regs(struct drm_crtc *crtc, struct drm_display_mode * mode)
          * 1 << 30 on 0x60.830), for no apparent reason */
         regp->CRTC[NV_CIO_CRE_59] = off_chip_digital;
 
-        if (nv_device(drm->device)->card_type >= NV_30)
+        if (drm->device.info.family >= NV_DEVICE_INFO_V0_RANKINE)
                 regp->CRTC[0x9f] = off_chip_digital ? 0x11 : 0x1;
 
         regp->crtc_830 = mode->crtc_vdisplay - 3;
         regp->crtc_834 = mode->crtc_vdisplay - 1;
 
-        if (nv_device(drm->device)->card_type == NV_40)
+        if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE)
                 /* This is what the blob does */
                 regp->crtc_850 = NVReadCRTC(dev, 0, NV_PCRTC_850);
 
-        if (nv_device(drm->device)->card_type >= NV_30)
+        if (drm->device.info.family >= NV_DEVICE_INFO_V0_RANKINE)
                 regp->gpio_ext = NVReadCRTC(dev, 0, NV_PCRTC_GPIO_EXT);
 
-        if (nv_device(drm->device)->card_type >= NV_10)
+        if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS)
                 regp->crtc_cfg = NV10_PCRTC_CONFIG_START_ADDRESS_HSYNC;
         else
                 regp->crtc_cfg = NV04_PCRTC_CONFIG_START_ADDRESS_HSYNC;
 
         /* Some misc regs */
-        if (nv_device(drm->device)->card_type == NV_40) {
+        if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) {
                 regp->CRTC[NV_CIO_CRE_85] = 0xFF;
                 regp->CRTC[NV_CIO_CRE_86] = 0x1;
         }
@@ -581,7 +581,7 @@ nv_crtc_mode_set_regs(struct drm_crtc *crtc, struct drm_display_mode * mode)
 
         /* Generic PRAMDAC regs */
 
-        if (nv_device(drm->device)->card_type >= NV_10)
+        if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS)
                 /* Only bit that bios and blob set. */
                 regp->nv10_cursync = (1 << 25);
 
@@ -590,7 +590,7 @@ nv_crtc_mode_set_regs(struct drm_crtc *crtc, struct drm_display_mode * mode)
                                 NV_PRAMDAC_GENERAL_CONTROL_PIXMIX_ON;
         if (crtc->primary->fb->depth == 16)
                 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL;
-        if (nv_device(drm->device)->chipset >= 0x11)
+        if (drm->device.info.chipset >= 0x11)
                 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_PIPE_LONG;
 
         regp->ramdac_630 = 0; /* turn off green mode (tv test pattern?) */
@@ -653,7 +653,7 @@ nv_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode,
 
         nv_crtc_mode_set_vga(crtc, adjusted_mode);
         /* calculated in nv04_dfp_prepare, nv40 needs it written before calculating PLLs */
-        if (nv_device(drm->device)->card_type == NV_40)
+        if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE)
                 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, nv04_display(dev)->mode_reg.sel_clk);
         nv_crtc_mode_set_regs(crtc, adjusted_mode);
         nv_crtc_calc_state_ext(crtc, mode, adjusted_mode->clock);
@@ -714,7 +714,7 @@ static void nv_crtc_prepare(struct drm_crtc *crtc)
 
         /* Some more preparation. */
         NVWriteCRTC(dev, nv_crtc->index, NV_PCRTC_CONFIG, NV_PCRTC_CONFIG_START_ADDRESS_NON_VGA);
-        if (nv_device(drm->device)->card_type == NV_40) {
+        if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) {
                 uint32_t reg900 = NVReadRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900);
                 NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900, reg900 & ~0x10000);
         }
@@ -888,7 +888,7 @@ nv04_crtc_do_mode_set_base(struct drm_crtc *crtc,
         crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FF_INDEX);
         crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FFLWM__INDEX);
 
-        if (nv_device(drm->device)->card_type >= NV_20) {
+        if (drm->device.info.family >= NV_DEVICE_INFO_V0_KELVIN) {
                 regp->CRTC[NV_CIO_CRE_47] = arb_lwm >> 8;
                 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_47);
         }
@@ -969,7 +969,7 @@ static void nv11_cursor_upload(struct drm_device *dev, struct nouveau_bo *src,
                 {
                         struct nouveau_drm *drm = nouveau_drm(dev);
 
-                        if (nv_device(drm->device)->chipset == 0x11) {
+                        if (drm->device.info.chipset == 0x11) {
                                 pixel = ((pixel & 0x000000ff) << 24) |
                                         ((pixel & 0x0000ff00) << 8) |
                                         ((pixel & 0x00ff0000) >> 8) |
@@ -1010,7 +1010,7 @@ nv04_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
         if (ret)
                 goto out;
 
-        if (nv_device(drm->device)->chipset >= 0x11)
+        if (drm->device.info.chipset >= 0x11)
                 nv11_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo);
         else
                 nv04_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo);
diff --git a/drivers/gpu/drm/nouveau/dispnv04/cursor.c b/drivers/gpu/drm/nouveau/dispnv04/cursor.c
index a810303169de..4e61173c3353 100644
--- a/drivers/gpu/drm/nouveau/dispnv04/cursor.c
+++ b/drivers/gpu/drm/nouveau/dispnv04/cursor.c
@@ -55,7 +55,7 @@ nv04_cursor_set_offset(struct nouveau_crtc *nv_crtc, uint32_t offset)
         crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX);
         crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX);
         crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX);
-        if (nv_device(drm->device)->card_type == NV_40)
+        if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE)
                 nv_fix_nv40_hw_cursor(dev, nv_crtc->index);
 }
 
diff --git a/drivers/gpu/drm/nouveau/dispnv04/dac.c b/drivers/gpu/drm/nouveau/dispnv04/dac.c
index 3fec5e6b66b1..2d8056cde996 100644
--- a/drivers/gpu/drm/nouveau/dispnv04/dac.c
+++ b/drivers/gpu/drm/nouveau/dispnv04/dac.c
@@ -65,8 +65,8 @@ int nv04_dac_output_offset(struct drm_encoder *encoder)
 
 static int sample_load_twice(struct drm_device *dev, bool sense[2])
 {
-        struct nouveau_object *device = nouveau_drm(dev)->device;
-        struct nouveau_timer *ptimer = nouveau_timer(device);
+        struct nvif_device *device = &nouveau_drm(dev)->device;
+        struct nouveau_timer *ptimer = nvkm_timer(device);
         int i;
 
         for (i = 0; i < 2; i++) {
@@ -128,7 +128,7 @@ static enum drm_connector_status nv04_dac_detect(struct drm_encoder *encoder,
                                                  struct drm_connector *connector)
 {
         struct drm_device *dev = encoder->dev;
-        struct nouveau_object *device = nouveau_drm(dev)->device;
+        struct nvif_device *device = &nouveau_drm(dev)->device;
         struct nouveau_drm *drm = nouveau_drm(dev);
         uint8_t saved_seq1, saved_pi, saved_rpc1, saved_cr_mode;
         uint8_t saved_palette0[3], saved_palette_mask;
@@ -231,8 +231,8 @@ uint32_t nv17_dac_sample_load(struct drm_encoder *encoder)
 {
         struct drm_device *dev = encoder->dev;
         struct nouveau_drm *drm = nouveau_drm(dev);
-        struct nouveau_object *device = nouveau_drm(dev)->device;
-        struct nouveau_gpio *gpio = nouveau_gpio(device);
+        struct nvif_device *device = &nouveau_drm(dev)->device;
+        struct nouveau_gpio *gpio = nvkm_gpio(device);
         struct dcb_output *dcb = nouveau_encoder(encoder)->dcb;
         uint32_t sample, testval, regoffset = nv04_dac_output_offset(encoder);
         uint32_t saved_powerctrl_2 = 0, saved_powerctrl_4 = 0, saved_routput,
@@ -283,7 +283,7 @@ uint32_t nv17_dac_sample_load(struct drm_encoder *encoder)
         /* nv driver and nv31 use 0xfffffeee, nv34 and 6600 use 0xfffffece */
         routput = (saved_routput & 0xfffffece) | head << 8;
 
-        if (nv_device(drm->device)->card_type >= NV_40) {
+        if (drm->device.info.family >= NV_DEVICE_INFO_V0_CURIE) {
                 if (dcb->type == DCB_OUTPUT_TV)
                         routput |= 0x1a << 16;
                 else
@@ -398,7 +398,7 @@ static void nv04_dac_mode_set(struct drm_encoder *encoder,
         }
 
         /* This could use refinement for flatpanels, but it should work this way */
-        if (nv_device(drm->device)->chipset < 0x44)
+        if (drm->device.info.chipset < 0x44)
                 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0xf0000000);
         else
                 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0x00100000);
diff --git a/drivers/gpu/drm/nouveau/dispnv04/dfp.c b/drivers/gpu/drm/nouveau/dispnv04/dfp.c
index a9f510e01c2f..42a5435259f7 100644
--- a/drivers/gpu/drm/nouveau/dispnv04/dfp.c
+++ b/drivers/gpu/drm/nouveau/dispnv04/dfp.c
@@ -281,7 +281,7 @@ static void nv04_dfp_mode_set(struct drm_encoder *encoder,
                               struct drm_display_mode *adjusted_mode)
 {
         struct drm_device *dev = encoder->dev;
-        struct nouveau_object *device = nouveau_drm(dev)->device;
+        struct nvif_device *device = &nouveau_drm(dev)->device;
         struct nouveau_drm *drm = nouveau_drm(dev);
         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
         struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
@@ -416,7 +416,7 @@ static void nv04_dfp_mode_set(struct drm_encoder *encoder,
         if ((nv_connector->dithering_mode == DITHERING_MODE_ON) ||
             (nv_connector->dithering_mode == DITHERING_MODE_AUTO &&
              encoder->crtc->primary->fb->depth > connector->display_info.bpc * 3)) {
-                if (nv_device(drm->device)->chipset == 0x11)
+                if (drm->device.info.chipset == 0x11)
                         regp->dither = savep->dither | 0x00010000;
                 else {
                         int i;
@@ -427,7 +427,7 @@ static void nv04_dfp_mode_set(struct drm_encoder *encoder,
                         }
                 }
         } else {
-                if (nv_device(drm->device)->chipset != 0x11) {
+                if (drm->device.info.chipset != 0x11) {
                         /* reset them */
                         int i;
                         for (i = 0; i < 3; i++) {
@@ -463,7 +463,7 @@ static void nv04_dfp_commit(struct drm_encoder *encoder)
                 NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL);
 
         /* This could use refinement for flatpanels, but it should work this way */
-        if (nv_device(drm->device)->chipset < 0x44)
+        if (drm->device.info.chipset < 0x44)
                 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0xf0000000);
         else
                 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0x00100000);
@@ -485,7 +485,7 @@ static void nv04_dfp_update_backlight(struct drm_encoder *encoder, int mode)
 {
 #ifdef __powerpc__
         struct drm_device *dev = encoder->dev;
-        struct nouveau_object *device = nouveau_drm(dev)->device;
+        struct nvif_device *device = &nouveau_drm(dev)->device;
 
         /* BIOS scripts usually take care of the backlight, thanks
          * Apple for your consistency.
@@ -623,7 +623,7 @@ static void nv04_tmds_slave_init(struct drm_encoder *encoder)
         struct drm_device *dev = encoder->dev;
         struct dcb_output *dcb = nouveau_encoder(encoder)->dcb;
         struct nouveau_drm *drm = nouveau_drm(dev);
-        struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
+        struct nouveau_i2c *i2c = nvkm_i2c(&drm->device);
         struct nouveau_i2c_port *port = i2c->find(i2c, 2);
         struct nouveau_i2c_board_info info[] = {
                 {
diff --git a/drivers/gpu/drm/nouveau/dispnv04/disp.c b/drivers/gpu/drm/nouveau/dispnv04/disp.c
index 4342fdaee707..e63f5d694c55 100644
--- a/drivers/gpu/drm/nouveau/dispnv04/disp.c
+++ b/drivers/gpu/drm/nouveau/dispnv04/disp.c
@@ -58,7 +58,7 @@ int
 nv04_display_create(struct drm_device *dev)
 {
         struct nouveau_drm *drm = nouveau_drm(dev);
-        struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
+        struct nouveau_i2c *i2c = nvkm_i2c(&drm->device);
         struct dcb_table *dcb = &drm->vbios.dcb;
         struct drm_connector *connector, *ct;
         struct drm_encoder *encoder;
diff --git a/drivers/gpu/drm/nouveau/dispnv04/disp.h b/drivers/gpu/drm/nouveau/dispnv04/disp.h
index 99408cf03af0..17b899d9aba3 100644
--- a/drivers/gpu/drm/nouveau/dispnv04/disp.h
+++ b/drivers/gpu/drm/nouveau/dispnv04/disp.h
@@ -131,7 +131,7 @@ nv_two_heads(struct drm_device *dev)
         struct nouveau_drm *drm = nouveau_drm(dev);
         const int impl = dev->pdev->device & 0x0ff0;
 
-        if (nv_device(drm->device)->card_type >= NV_10 && impl != 0x0100 &&
+        if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS && impl != 0x0100 &&
             impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
                 return true;
 
@@ -150,7 +150,7 @@ nv_two_reg_pll(struct drm_device *dev)
         struct nouveau_drm *drm = nouveau_drm(dev);
         const int impl = dev->pdev->device & 0x0ff0;
 
-        if (impl == 0x0310 || impl == 0x0340 || nv_device(drm->device)->card_type >= NV_40)
+        if (impl == 0x0310 || impl == 0x0340 || drm->device.info.family >= NV_DEVICE_INFO_V0_CURIE)
                 return true;
         return false;
 }
@@ -172,7 +172,7 @@ nouveau_bios_run_init_table(struct drm_device *dev, u16 table,
                             struct dcb_output *outp, int crtc)
 {
         struct nouveau_drm *drm = nouveau_drm(dev);
-        struct nouveau_bios *bios = nouveau_bios(drm->device);
+        struct nouveau_bios *bios = nvkm_bios(&drm->device);
         struct nvbios_init init = {
                 .subdev = nv_subdev(bios),
                 .bios = bios,
diff --git a/drivers/gpu/drm/nouveau/dispnv04/hw.c b/drivers/gpu/drm/nouveau/dispnv04/hw.c
index e09c35a948ca..c12f3a871da1 100644
--- a/drivers/gpu/drm/nouveau/dispnv04/hw.c
+++ b/drivers/gpu/drm/nouveau/dispnv04/hw.c
@@ -92,7 +92,7 @@ NVSetOwner(struct drm_device *dev, int owner)
         if (owner == 1)
                 owner *= 3;
 
-        if (nv_device(drm->device)->chipset == 0x11) {
+        if (drm->device.info.chipset == 0x11) {
                 /* This might seem stupid, but the blob does it and
                  * omitting it often locks the system up.
                  */
@@ -103,7 +103,7 @@ NVSetOwner(struct drm_device *dev, int owner)
         /* CR44 is always changed on CRTC0 */
         NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_44, owner);
 
-        if (nv_device(drm->device)->chipset == 0x11) {  /* set me harder */
+        if (drm->device.info.chipset == 0x11) { /* set me harder */
                 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_2E, owner);
                 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_2E, owner);
         }
@@ -152,7 +152,7 @@ nouveau_hw_decode_pll(struct drm_device *dev, uint32_t reg1, uint32_t pll1,
                 pllvals->NM1 = pll1 & 0xffff;
                 if (nv_two_reg_pll(dev) && pll2 & NV31_RAMDAC_ENABLE_VCO2)
                         pllvals->NM2 = pll2 & 0xffff;
-                else if (nv_device(drm->device)->chipset == 0x30 || nv_device(drm->device)->chipset == 0x35) {
+                else if (drm->device.info.chipset == 0x30 || drm->device.info.chipset == 0x35) {
                         pllvals->M1 &= 0xf; /* only 4 bits */
                         if (pll1 & NV30_RAMDAC_ENABLE_VCO2) {
                                 pllvals->M2 = (pll1 >> 4) & 0x7;
@@ -168,8 +168,8 @@ nouveau_hw_get_pllvals(struct drm_device *dev, enum nvbios_pll_type plltype,
                        struct nouveau_pll_vals *pllvals)
 {
         struct nouveau_drm *drm = nouveau_drm(dev);
-        struct nouveau_object *device = drm->device;
-        struct nouveau_bios *bios = nouveau_bios(device);
+        struct nvif_device *device = &drm->device;
+        struct nouveau_bios *bios = nvkm_bios(device);
         uint32_t reg1, pll1, pll2 = 0;
         struct nvbios_pll pll_lim;
         int ret;
@@ -187,7 +187,7 @@ nouveau_hw_get_pllvals(struct drm_device *dev, enum nvbios_pll_type plltype,
                 pll2 = nvif_rd32(device, reg2);
         }
 
-        if (nv_device(drm->device)->card_type == 0x40 && reg1 >= NV_PRAMDAC_VPLL_COEFF) {
+        if (drm->device.info.family == NV_DEVICE_INFO_V0_CELSIUS && reg1 >= NV_PRAMDAC_VPLL_COEFF) {
                 uint32_t ramdac580 = NVReadRAMDAC(dev, 0, NV_PRAMDAC_580);
 
                 /* check whether vpll has been forced into single stage mode */
@@ -255,9 +255,9 @@ nouveau_hw_fix_bad_vpll(struct drm_device *dev, int head)
          */
 
         struct nouveau_drm *drm = nouveau_drm(dev);
-        struct nouveau_object *device = drm->device;
-        struct nouveau_clock *clk = nouveau_clock(device);
-        struct nouveau_bios *bios = nouveau_bios(device);
+        struct nvif_device *device = &drm->device;
+        struct nouveau_clock *clk = nvkm_clock(device);
+        struct nouveau_bios *bios = nvkm_bios(device);
         struct nvbios_pll pll_lim;
         struct nouveau_pll_vals pv;
         enum nvbios_pll_type pll = head ? PLL_VPLL1 : PLL_VPLL0;
@@ -394,21 +394,21 @@ nv_save_state_ramdac(struct drm_device *dev, int head,
         struct nv04_crtc_reg *regp = &state->crtc_reg[head];
         int i;
 
-        if (nv_device(drm->device)->card_type >= NV_10)
+        if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS)
                 regp->nv10_cursync = NVReadRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC);
 
         nouveau_hw_get_pllvals(dev, head ? PLL_VPLL1 : PLL_VPLL0, &regp->pllvals);
         state->pllsel = NVReadRAMDAC(dev, 0, NV_PRAMDAC_PLL_COEFF_SELECT);
         if (nv_two_heads(dev))
                 state->sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK);
-        if (nv_device(drm->device)->chipset == 0x11)
+        if (drm->device.info.chipset == 0x11)
                 regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11);
 
         regp->ramdac_gen_ctrl = NVReadRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL);
 
         if (nv_gf4_disp_arch(dev))
                 regp->ramdac_630 = NVReadRAMDAC(dev, head, NV_PRAMDAC_630);
-        if (nv_device(drm->device)->chipset >= 0x30)
+        if (drm->device.info.chipset >= 0x30)
                 regp->ramdac_634 = NVReadRAMDAC(dev, head, NV_PRAMDAC_634);
 
         regp->tv_setup = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP);
@@ -450,7 +450,7 @@ nv_save_state_ramdac(struct drm_device *dev, int head,
         if (nv_gf4_disp_arch(dev))
                 regp->ramdac_8c0 = NVReadRAMDAC(dev, head, NV_PRAMDAC_8C0);
 
-        if (nv_device(drm->device)->card_type == NV_40) {
+        if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) {
                 regp->ramdac_a20 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A20);
                 regp->ramdac_a24 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A24);
                 regp->ramdac_a34 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A34);
@@ -466,26 +466,26 @@ nv_load_state_ramdac(struct drm_device *dev, int head,
                      struct nv04_mode_state *state)
 {
         struct nouveau_drm *drm = nouveau_drm(dev);
-        struct nouveau_clock *clk = nouveau_clock(drm->device);
+        struct nouveau_clock *clk = nvkm_clock(&drm->device);
         struct nv04_crtc_reg *regp = &state->crtc_reg[head];
         uint32_t pllreg = head ? NV_RAMDAC_VPLL2 : NV_PRAMDAC_VPLL_COEFF;
         int i;
 
-        if (nv_device(drm->device)->card_type >= NV_10)
+        if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS)
                 NVWriteRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync);
 
         clk->pll_prog(clk, pllreg, &regp->pllvals);
         NVWriteRAMDAC(dev, 0, NV_PRAMDAC_PLL_COEFF_SELECT, state->pllsel);
         if (nv_two_heads(dev))
                 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, state->sel_clk);
-        if (nv_device(drm->device)->chipset == 0x11)
+        if (drm->device.info.chipset == 0x11)
                 NVWriteRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11, regp->dither);
 
         NVWriteRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL, regp->ramdac_gen_ctrl);
 
         if (nv_gf4_disp_arch(dev))
                 NVWriteRAMDAC(dev, head, NV_PRAMDAC_630, regp->ramdac_630);
-        if (nv_device(drm->device)->chipset >= 0x30)
+        if (drm->device.info.chipset >= 0x30)
                 NVWriteRAMDAC(dev, head, NV_PRAMDAC_634, regp->ramdac_634);
 
         NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP, regp->tv_setup);
@@ -522,7 +522,7 @@ nv_load_state_ramdac(struct drm_device *dev, int head,
         if (nv_gf4_disp_arch(dev))
                 NVWriteRAMDAC(dev, head, NV_PRAMDAC_8C0, regp->ramdac_8c0);
 
-        if (nv_device(drm->device)->card_type == NV_40) {
+        if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) {
                 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A20, regp->ramdac_a20);
                 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A24, regp->ramdac_a24);
                 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A34, regp->ramdac_a34);
@@ -603,10 +603,10 @@ nv_save_state_ext(struct drm_device *dev, int head,
         rd_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX);
         rd_cio_state(dev, head, regp, NV_CIO_CRE_21);
 
-        if (nv_device(drm->device)->card_type >= NV_20)
+        if (drm->device.info.family >= NV_DEVICE_INFO_V0_KELVIN)
                 rd_cio_state(dev, head, regp, NV_CIO_CRE_47);
 
-        if (nv_device(drm->device)->card_type >= NV_30)
+        if (drm->device.info.family >= NV_DEVICE_INFO_V0_RANKINE)
                 rd_cio_state(dev, head, regp, 0x9f);
 
         rd_cio_state(dev, head, regp, NV_CIO_CRE_49);
@@ -615,14 +615,14 @@ nv_save_state_ext(struct drm_device *dev, int head,
         rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX);
         rd_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX);
 
-        if (nv_device(drm->device)->card_type >= NV_10) {
+        if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) {
                 regp->crtc_830 = NVReadCRTC(dev, head, NV_PCRTC_830);
                 regp->crtc_834 = NVReadCRTC(dev, head, NV_PCRTC_834);
 
-                if (nv_device(drm->device)->card_type >= NV_30)
+                if (drm->device.info.family >= NV_DEVICE_INFO_V0_RANKINE)
                         regp->gpio_ext = NVReadCRTC(dev, head, NV_PCRTC_GPIO_EXT);
 
-                if (nv_device(drm->device)->card_type == NV_40)
+                if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE)
                         regp->crtc_850 = NVReadCRTC(dev, head, NV_PCRTC_850);
 
                 if (nv_two_heads(dev))
@@ -634,7 +634,7 @@ nv_save_state_ext(struct drm_device *dev, int head,
 
         rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX);
         rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX);
-        if (nv_device(drm->device)->card_type >= NV_10) {
+        if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) {
                 rd_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX);
                 rd_cio_state(dev, head, regp, NV_CIO_CRE_CSB);
                 rd_cio_state(dev, head, regp, NV_CIO_CRE_4B);
@@ -663,14 +663,14 @@ nv_load_state_ext(struct drm_device *dev, int head,
                   struct nv04_mode_state *state)
 {
         struct nouveau_drm *drm = nouveau_drm(dev);
-        struct nouveau_object *device = drm->device;
-        struct nouveau_timer *ptimer = nouveau_timer(device);
-        struct nouveau_fb *pfb = nouveau_fb(device);
+        struct nvif_device *device = &drm->device;
+        struct nouveau_timer *ptimer = nvkm_timer(device);
+        struct nouveau_fb *pfb = nvkm_fb(device);
         struct nv04_crtc_reg *regp = &state->crtc_reg[head];
         uint32_t reg900;
         int i;
 
-        if (nv_device(drm->device)->card_type >= NV_10) {
+        if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) {
                 if (nv_two_heads(dev))
                         /* setting ENGINE_CTRL (EC) *must* come before
                          * CIO_CRE_LCD, as writing CRE_LCD sets bits 16 & 17 in
@@ -692,10 +692,10 @@ nv_load_state_ext(struct drm_device *dev, int head,
                 NVWriteCRTC(dev, head, NV_PCRTC_830, regp->crtc_830);
                 NVWriteCRTC(dev, head, NV_PCRTC_834, regp->crtc_834);
 
-                if (nv_device(drm->device)->card_type >= NV_30)
+                if (drm->device.info.family >= NV_DEVICE_INFO_V0_RANKINE)
                         NVWriteCRTC(dev, head, NV_PCRTC_GPIO_EXT, regp->gpio_ext);
 
-                if (nv_device(drm->device)->card_type == NV_40) {
+                if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) {
                         NVWriteCRTC(dev, head, NV_PCRTC_850, regp->crtc_850);
 
                         reg900 = NVReadRAMDAC(dev, head, NV_PRAMDAC_900);
@@ -718,23 +718,23 @@ nv_load_state_ext(struct drm_device *dev, int head,
         wr_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX);
         wr_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX);
 
-        if (nv_device(drm->device)->card_type >= NV_20)
+        if (drm->device.info.family >= NV_DEVICE_INFO_V0_KELVIN)
                 wr_cio_state(dev, head, regp, NV_CIO_CRE_47);
 
-        if (nv_device(drm->device)->card_type >= NV_30)
+        if (drm->device.info.family >= NV_DEVICE_INFO_V0_RANKINE)
                 wr_cio_state(dev, head, regp, 0x9f);
 
         wr_cio_state(dev, head, regp, NV_CIO_CRE_49);
         wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX);
         wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX);
         wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX);
-        if (nv_device(drm->device)->card_type == NV_40)
+        if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE)
                 nv_fix_nv40_hw_cursor(dev, head);
         wr_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX);
 
         wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX);
         wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX);
-        if (nv_device(drm->device)->card_type >= NV_10) {
+        if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) {
                 wr_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX);
                 wr_cio_state(dev, head, regp, NV_CIO_CRE_CSB);
                 wr_cio_state(dev, head, regp, NV_CIO_CRE_4B);
@@ -742,7 +742,7 @@ nv_load_state_ext(struct drm_device *dev, int head,
         }
         /* NV11 and NV20 stop at 0x52. */
         if (nv_gf4_disp_arch(dev)) {
-                if (nv_device(drm->device)->card_type < NV_20) {
+                if (drm->device.info.family < NV_DEVICE_INFO_V0_KELVIN) {
                         /* Not waiting for vertical retrace before modifying
                            CRE_53/CRE_54 causes lockups. */
                         nouveau_timer_wait_eq(ptimer, 650000000, NV_PRMCIO_INP0__COLOR, 0x8, 0x8);
@@ -769,7 +769,7 @@ static void
 nv_save_state_palette(struct drm_device *dev, int head,
                       struct nv04_mode_state *state)
 {
-        struct nouveau_object *device = nouveau_drm(dev)->device;
+        struct nvif_device *device = &nouveau_drm(dev)->device;
         int head_offset = head * NV_PRMDIO_SIZE, i;
 
         nvif_wr08(device, NV_PRMDIO_PIXEL_MASK + head_offset,
@@ -788,7 +788,7 @@ void
 nouveau_hw_load_state_palette(struct drm_device *dev, int head,
                               struct nv04_mode_state *state)
 {
-        struct nouveau_object *device = nouveau_drm(dev)->device;
+        struct nvif_device *device = &nouveau_drm(dev)->device;
         int head_offset = head * NV_PRMDIO_SIZE, i;
 
         nvif_wr08(device, NV_PRMDIO_PIXEL_MASK + head_offset,
@@ -808,7 +808,7 @@ void nouveau_hw_save_state(struct drm_device *dev, int head,
 {
         struct nouveau_drm *drm = nouveau_drm(dev);
 
-        if (nv_device(drm->device)->chipset == 0x11)
+        if (drm->device.info.chipset == 0x11)
                 /* NB: no attempt is made to restore the bad pll later on */
                 nouveau_hw_fix_bad_vpll(dev, head);
         nv_save_state_ramdac(dev, head, state);
diff --git a/drivers/gpu/drm/nouveau/dispnv04/hw.h b/drivers/gpu/drm/nouveau/dispnv04/hw.h
index ebaf33dbc1a1..7f53c571f31f 100644
--- a/drivers/gpu/drm/nouveau/dispnv04/hw.h
+++ b/drivers/gpu/drm/nouveau/dispnv04/hw.h
@@ -60,7 +60,7 @@ extern void nouveau_calc_arb(struct drm_device *, int vclk, int bpp,
 static inline uint32_t NVReadCRTC(struct drm_device *dev,
                                         int head, uint32_t reg)
 {
-        struct nouveau_object *device = nouveau_drm(dev)->device;
+        struct nvif_device *device = &nouveau_drm(dev)->device;
         uint32_t val;
         if (head)
                 reg += NV_PCRTC0_SIZE;
@@ -71,7 +71,7 @@ static inline uint32_t NVReadCRTC(struct drm_device *dev,
 static inline void NVWriteCRTC(struct drm_device *dev,
                                         int head, uint32_t reg, uint32_t val)
 {
-        struct nouveau_object *device = nouveau_drm(dev)->device;
+        struct nvif_device *device = &nouveau_drm(dev)->device;
         if (head)
                 reg += NV_PCRTC0_SIZE;
         nvif_wr32(device, reg, val);
@@ -80,7 +80,7 @@ static inline void NVWriteCRTC(struct drm_device *dev,
 static inline uint32_t NVReadRAMDAC(struct drm_device *dev,
                                         int head, uint32_t reg)
 {
-        struct nouveau_object *device = nouveau_drm(dev)->device;
+        struct nvif_device *device = &nouveau_drm(dev)->device;
         uint32_t val;
         if (head)
                 reg += NV_PRAMDAC0_SIZE;
@@ -91,7 +91,7 @@ static inline uint32_t NVReadRAMDAC(struct drm_device *dev,
 static inline void NVWriteRAMDAC(struct drm_device *dev,
                                         int head, uint32_t reg, uint32_t val)
 {
-        struct nouveau_object *device = nouveau_drm(dev)->device;
+        struct nvif_device *device = &nouveau_drm(dev)->device;
         if (head)
                 reg += NV_PRAMDAC0_SIZE;
         nvif_wr32(device, reg, val);
@@ -120,7 +120,7 @@ static inline void nv_write_tmds(struct drm_device *dev,
 static inline void NVWriteVgaCrtc(struct drm_device *dev,
                                         int head, uint8_t index, uint8_t value)
 {
-        struct nouveau_object *device = nouveau_drm(dev)->device;
+        struct nvif_device *device = &nouveau_drm(dev)->device;
         nvif_wr08(device, NV_PRMCIO_CRX__COLOR + head * NV_PRMCIO_SIZE, index);
         nvif_wr08(device, NV_PRMCIO_CR__COLOR + head * NV_PRMCIO_SIZE, value);
 }
@@ -128,7 +128,7 @@ static inline void NVWriteVgaCrtc(struct drm_device *dev,
 static inline uint8_t NVReadVgaCrtc(struct drm_device *dev,
                                         int head, uint8_t index)
 {
-        struct nouveau_object *device = nouveau_drm(dev)->device;
+        struct nvif_device *device = &nouveau_drm(dev)->device;
         uint8_t val;
         nvif_wr08(device, NV_PRMCIO_CRX__COLOR + head * NV_PRMCIO_SIZE, index);
         val = nvif_rd08(device, NV_PRMCIO_CR__COLOR + head * NV_PRMCIO_SIZE);
@@ -165,13 +165,13 @@ static inline uint8_t NVReadVgaCrtc5758(struct drm_device *dev, int head, uint8_
 static inline uint8_t NVReadPRMVIO(struct drm_device *dev,
                                         int head, uint32_t reg)
 {
-        struct nouveau_object *device = nouveau_drm(dev)->device;
+        struct nvif_device *device = &nouveau_drm(dev)->device;
         struct nouveau_drm *drm = nouveau_drm(dev);
         uint8_t val;
 
         /* Only NV4x have two pvio ranges; other twoHeads cards MUST call
          * NVSetOwner for the relevant head to be programmed */
-        if (head && nv_device(drm->device)->card_type == NV_40)
+        if (head && drm->device.info.family == NV_DEVICE_INFO_V0_CURIE)
                 reg += NV_PRMVIO_SIZE;
 
         val = nvif_rd08(device, reg);
@@ -181,12 +181,12 @@ static inline uint8_t NVReadPRMVIO(struct drm_device *dev,
 static inline void NVWritePRMVIO(struct drm_device *dev,
                                         int head, uint32_t reg, uint8_t value)
 {
-        struct nouveau_object *device = nouveau_drm(dev)->device;
+        struct nvif_device *device = &nouveau_drm(dev)->device;
         struct nouveau_drm *drm = nouveau_drm(dev);
 
         /* Only NV4x have two pvio ranges; other twoHeads cards MUST call
          * NVSetOwner for the relevant head to be programmed */
-        if (head && nv_device(drm->device)->card_type == NV_40)
+        if (head && drm->device.info.family == NV_DEVICE_INFO_V0_CURIE)
                 reg += NV_PRMVIO_SIZE;
 
         nvif_wr08(device, reg, value);
@@ -194,14 +194,14 @@ static inline void NVWritePRMVIO(struct drm_device *dev,
 
 static inline void NVSetEnablePalette(struct drm_device *dev, int head, bool enable)
 {
-        struct nouveau_object *device = nouveau_drm(dev)->device;
+        struct nvif_device *device = &nouveau_drm(dev)->device;
         nvif_rd08(device, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE);
         nvif_wr08(device, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE, enable ? 0 : 0x20);
 }
 
 static inline bool NVGetEnablePalette(struct drm_device *dev, int head)
 {
-        struct nouveau_object *device = nouveau_drm(dev)->device;
+        struct nvif_device *device = &nouveau_drm(dev)->device;
         nvif_rd08(device, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE);
         return !(nvif_rd08(device, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE) & 0x20);
 }
@@ -209,7 +209,7 @@ static inline bool NVGetEnablePalette(struct drm_device *dev, int head)
 static inline void NVWriteVgaAttr(struct drm_device *dev,
                                         int head, uint8_t index, uint8_t value)
 {
-        struct nouveau_object *device = nouveau_drm(dev)->device;
+        struct nvif_device *device = &nouveau_drm(dev)->device;
         if (NVGetEnablePalette(dev, head))
                 index &= ~0x20;
         else
@@ -223,7 +223,7 @@ static inline void NVWriteVgaAttr(struct drm_device *dev,
 static inline uint8_t NVReadVgaAttr(struct drm_device *dev,
                                         int head, uint8_t index)
 {
-        struct nouveau_object *device = nouveau_drm(dev)->device;
+        struct nvif_device *device = &nouveau_drm(dev)->device;
         uint8_t val;
         if (NVGetEnablePalette(dev, head))
                 index &= ~0x20;
@@ -259,10 +259,10 @@ static inline void NVVgaProtect(struct drm_device *dev, int head, bool protect)
 static inline bool
 nv_heads_tied(struct drm_device *dev)
 {
-        struct nouveau_object *device = nouveau_drm(dev)->device;
+        struct nvif_device *device = &nouveau_drm(dev)->device;
         struct nouveau_drm *drm = nouveau_drm(dev);
 
-        if (nv_device(drm->device)->chipset == 0x11)
+        if (drm->device.info.chipset == 0x11)
                 return !!(nvif_rd32(device, NV_PBUS_DEBUG_1) & (1 << 28));
 
         return NVReadVgaCrtc(dev, 0, NV_CIO_CRE_44) & 0x4;
@@ -318,7 +318,7 @@ NVLockVgaCrtcs(struct drm_device *dev, bool lock)
         NVWriteVgaCrtc(dev, 0, NV_CIO_SR_LOCK_INDEX,
                        lock ? NV_CIO_SR_LOCK_VALUE : NV_CIO_SR_UNLOCK_RW_VALUE);
         /* NV11 has independently lockable extended crtcs, except when tied */
-        if (nv_device(drm->device)->chipset == 0x11 && !nv_heads_tied(dev))
+        if (drm->device.info.chipset == 0x11 && !nv_heads_tied(dev))
                 NVWriteVgaCrtc(dev, 1, NV_CIO_SR_LOCK_INDEX,
                                lock ? NV_CIO_SR_LOCK_VALUE :
                                       NV_CIO_SR_UNLOCK_RW_VALUE);
@@ -335,7 +335,7 @@ static inline int nv_cursor_width(struct drm_device *dev)
 {
         struct nouveau_drm *drm = nouveau_drm(dev);
 
-        return nv_device(drm->device)->card_type >= NV_10 ? NV10_CURSOR_SIZE : NV04_CURSOR_SIZE;
+        return drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS ? NV10_CURSOR_SIZE : NV04_CURSOR_SIZE;
 }
 
 static inline void
@@ -357,7 +357,7 @@ nv_set_crtc_base(struct drm_device *dev, int head, uint32_t offset)
 
         NVWriteCRTC(dev, head, NV_PCRTC_START, offset);
 
-        if (nv_device(drm->device)->card_type == NV_04) {
+        if (drm->device.info.family == NV_DEVICE_INFO_V0_TNT) {
                 /*
                  * Hilarious, the 24th bit doesn't want to stick to
                  * PCRTC_START...
@@ -382,7 +382,7 @@ nv_show_cursor(struct drm_device *dev, int head, bool show)
                 *curctl1 &= ~MASK(NV_CIO_CRE_HCUR_ADDR1_ENABLE);
         NVWriteVgaCrtc(dev, head, NV_CIO_CRE_HCUR_ADDR1_INDEX, *curctl1);
 
-        if (nv_device(drm->device)->card_type == NV_40)
+        if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE)
                 nv_fix_nv40_hw_cursor(dev, head);
 }
 
@@ -398,7 +398,7 @@ nv_pitch_align(struct drm_device *dev, uint32_t width, int bpp)
                 bpp = 8;
 
         /* Alignment requirements taken from the Haiku driver */
-        if (nv_device(drm->device)->card_type == NV_04)
+        if (drm->device.info.family == NV_DEVICE_INFO_V0_TNT)
                 mask = 128 / bpp - 1;
         else
                 mask = 512 / bpp - 1;
diff --git a/drivers/gpu/drm/nouveau/dispnv04/overlay.c b/drivers/gpu/drm/nouveau/dispnv04/overlay.c
index bae8068b897f..b36afcbbc83f 100644
--- a/drivers/gpu/drm/nouveau/dispnv04/overlay.c
+++ b/drivers/gpu/drm/nouveau/dispnv04/overlay.c
@@ -96,7 +96,7 @@ nv10_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
                   uint32_t src_x, uint32_t src_y,
                   uint32_t src_w, uint32_t src_h)
 {
-        struct nouveau_object *dev = nouveau_drm(plane->dev)->device;
+        struct nvif_device *dev = &nouveau_drm(plane->dev)->device;
         struct nouveau_plane *nv_plane = (struct nouveau_plane *)plane;
         struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
@@ -117,7 +117,7 @@ nv10_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
         if (format > 0xffff)
                 return -ERANGE;
 
-        if (nv_device(dev)->chipset >= 0x30) {
+        if (dev->info.chipset >= 0x30) {
                 if (crtc_w < (src_w >> 1) || crtc_h < (src_h >> 1))
                         return -ERANGE;
         } else {
@@ -172,7 +172,7 @@ nv10_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 static int
 nv10_disable_plane(struct drm_plane *plane)
 {
-        struct nouveau_object *dev = nouveau_drm(plane->dev)->device;
+        struct nvif_device *dev = &nouveau_drm(plane->dev)->device;
         struct nouveau_plane *nv_plane = (struct nouveau_plane *)plane;
 
         nvif_wr32(dev, NV_PVIDEO_STOP, 1);
@@ -195,7 +195,7 @@ nv_destroy_plane(struct drm_plane *plane)
 static void
 nv10_set_params(struct nouveau_plane *plane)
 {
-        struct nouveau_object *dev = nouveau_drm(plane->base.dev)->device;
+        struct nvif_device *dev = &nouveau_drm(plane->base.dev)->device;
         u32 luma = (plane->brightness - 512) << 16 | plane->contrast;
         u32 chroma = ((sin_mul(plane->hue, plane->saturation) & 0xffff) << 16) |
                 (cos_mul(plane->hue, plane->saturation) & 0xffff);
@@ -264,7 +264,7 @@ nv10_overlay_init(struct drm_device *device)
         if (!plane)
                 return;
 
-        switch (nv_device(drm->device)->chipset) {
+        switch (drm->device.info.chipset) {
         case 0x10:
         case 0x11:
         case 0x15:
@@ -343,7 +343,7 @@ nv04_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
                   uint32_t src_x, uint32_t src_y,
                   uint32_t src_w, uint32_t src_h)
 {
-        struct nouveau_object *dev = nouveau_drm(plane->dev)->device;
+        struct nvif_device *dev = &nouveau_drm(plane->dev)->device;
         struct nouveau_plane *nv_plane = (struct nouveau_plane *)plane;
         struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
         struct nouveau_bo *cur = nv_plane->cur;
@@ -422,7 +422,7 @@ nv04_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 static int
 nv04_disable_plane(struct drm_plane *plane)
 {
-        struct nouveau_object *dev = nouveau_drm(plane->dev)->device;
+        struct nvif_device *dev = &nouveau_drm(plane->dev)->device;
         struct nouveau_plane *nv_plane = (struct nouveau_plane *)plane;
 
         nvif_mask(dev, NV_PVIDEO_OVERLAY, 1, 0);
@@ -489,9 +489,9 @@ err:
 void
 nouveau_overlay_init(struct drm_device *device)
 {
-        struct nouveau_object *dev = nouveau_drm(device)->device;
-        if (nv_device(dev)->chipset < 0x10)
+        struct nvif_device *dev = &nouveau_drm(device)->device;
+        if (dev->info.chipset < 0x10)
                 nv04_overlay_init(device);
-        else if (nv_device(dev)->chipset <= 0x40)
+        else if (dev->info.chipset <= 0x40)
                 nv10_overlay_init(device);
 }
diff --git a/drivers/gpu/drm/nouveau/dispnv04/tvnv04.c b/drivers/gpu/drm/nouveau/dispnv04/tvnv04.c
index 8667620b703a..1ed54c9b5a49 100644
--- a/drivers/gpu/drm/nouveau/dispnv04/tvnv04.c
+++ b/drivers/gpu/drm/nouveau/dispnv04/tvnv04.c
@@ -56,7 +56,7 @@ static struct nouveau_i2c_board_info nv04_tv_encoder_info[] = {
 int nv04_tv_identify(struct drm_device *dev, int i2c_index)
 {
         struct nouveau_drm *drm = nouveau_drm(dev);
-        struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
+        struct nouveau_i2c *i2c = nvkm_i2c(&drm->device);
 
         return i2c->identify(i2c, i2c_index, "TV encoder",
                              nv04_tv_encoder_info, NULL, NULL);
@@ -206,7 +206,7 @@ nv04_tv_create(struct drm_connector *connector, struct dcb_output *entry)
         struct drm_encoder *encoder;
         struct drm_device *dev = connector->dev;
         struct nouveau_drm *drm = nouveau_drm(dev);
-        struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
+        struct nouveau_i2c *i2c = nvkm_i2c(&drm->device);
         struct nouveau_i2c_port *port = i2c->find(i2c, entry->i2c_index);
         int type, ret;
 
diff --git a/drivers/gpu/drm/nouveau/dispnv04/tvnv17.c b/drivers/gpu/drm/nouveau/dispnv04/tvnv17.c
index 195bd8e86c6a..28975b732c6a 100644
--- a/drivers/gpu/drm/nouveau/dispnv04/tvnv17.c
+++ b/drivers/gpu/drm/nouveau/dispnv04/tvnv17.c
@@ -51,7 +51,7 @@ static uint32_t nv42_tv_sample_load(struct drm_encoder *encoder)
 {
         struct drm_device *dev = encoder->dev;
         struct nouveau_drm *drm = nouveau_drm(dev);
-        struct nouveau_gpio *gpio = nouveau_gpio(drm->device);
+        struct nouveau_gpio *gpio = nvkm_gpio(&drm->device);
         uint32_t testval, regoffset = nv04_dac_output_offset(encoder);
         uint32_t gpio0, gpio1, fp_htotal, fp_hsync_start, fp_hsync_end,
                 fp_control, test_ctrl, dacclk, ctv_14, ctv_1c, ctv_6c;
@@ -135,17 +135,17 @@ static bool
 get_tv_detect_quirks(struct drm_device *dev, uint32_t *pin_mask)
 {
         struct nouveau_drm *drm = nouveau_drm(dev);
-        struct nouveau_object *device = drm->device;
+        struct nvif_device *device = &drm->device;
 
         /* Zotac FX5200 */
-        if (nv_device_match(device, 0x0322, 0x19da, 0x1035) ||
-            nv_device_match(device, 0x0322, 0x19da, 0x2035)) {
+        if (nv_device_match(nvkm_object(device), 0x0322, 0x19da, 0x1035) ||
+            nv_device_match(nvkm_object(device), 0x0322, 0x19da, 0x2035)) {
                 *pin_mask = 0xc;
                 return false;
         }
 
         /* MSI nForce2 IGP */
-        if (nv_device_match(device, 0x01f0, 0x1462, 0x5710)) {
+        if (nv_device_match(nvkm_object(device), 0x01f0, 0x1462, 0x5710)) {
                 *pin_mask = 0xc;
                 return false;
         }
@@ -167,8 +167,8 @@ nv17_tv_detect(struct drm_encoder *encoder, struct drm_connector *connector)
                 return connector_status_disconnected;
 
         if (reliable) {
-                if (nv_device(drm->device)->chipset == 0x42 ||
-                    nv_device(drm->device)->chipset == 0x43)
+                if (drm->device.info.chipset == 0x42 ||
+                    drm->device.info.chipset == 0x43)
                         tv_enc->pin_mask =
                                 nv42_tv_sample_load(encoder) >> 28 & 0xe;
                 else
@@ -375,7 +375,7 @@ static void  nv17_tv_dpms(struct drm_encoder *encoder, int mode)
 {
         struct drm_device *dev = encoder->dev;
         struct nouveau_drm *drm = nouveau_drm(dev);
-        struct nouveau_gpio *gpio = nouveau_gpio(drm->device);
+        struct nouveau_gpio *gpio = nvkm_gpio(&drm->device);
         struct nv17_tv_state *regs = &to_tv_enc(encoder)->state;
         struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
 
@@ -448,7 +448,7 @@ static void nv17_tv_prepare(struct drm_encoder *encoder)
         /* Set the DACCLK register */
         dacclk = (NVReadRAMDAC(dev, 0, dacclk_off) & ~0x30) | 0x1;
 
-        if (nv_device(drm->device)->card_type == NV_40)
+        if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE)
                 dacclk |= 0x1a << 16;
 
         if (tv_norm->kind == CTV_ENC_MODE) {
@@ -505,7 +505,7 @@ static void nv17_tv_mode_set(struct drm_encoder *encoder,
                         tv_regs->ptv_614 = 0x13;
                 }
 
-                if (nv_device(drm->device)->card_type >= NV_30) {
+                if (drm->device.info.family >= NV_DEVICE_INFO_V0_RANKINE) {
                         tv_regs->ptv_500 = 0xe8e0;
                         tv_regs->ptv_504 = 0x1710;
                         tv_regs->ptv_604 = 0x0;
@@ -600,7 +600,7 @@ static void nv17_tv_commit(struct drm_encoder *encoder)
         nv17_tv_state_load(dev, &to_tv_enc(encoder)->state);
 
         /* This could use refinement for flatpanels, but it should work */
-        if (nv_device(drm->device)->chipset < 0x44)
+        if (drm->device.info.chipset < 0x44)
                 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL +
                                         nv04_dac_output_offset(encoder),
                                         0xf0000000);
diff --git a/drivers/gpu/drm/nouveau/dispnv04/tvnv17.h b/drivers/gpu/drm/nouveau/dispnv04/tvnv17.h
index ce40e398f895..225894cdcac2 100644
--- a/drivers/gpu/drm/nouveau/dispnv04/tvnv17.h
+++ b/drivers/gpu/drm/nouveau/dispnv04/tvnv17.h
@@ -130,13 +130,13 @@ void nv17_ctv_update_rescaler(struct drm_encoder *encoder);
 static inline void nv_write_ptv(struct drm_device *dev, uint32_t reg,
                                 uint32_t val)
 {
-        struct nouveau_object *device = nouveau_drm(dev)->device;
+        struct nvif_device *device = &nouveau_drm(dev)->device;
         nvif_wr32(device, reg, val);
 }
 
 static inline uint32_t nv_read_ptv(struct drm_device *dev, uint32_t reg)
 {
-        struct nouveau_object *device = nouveau_drm(dev)->device;
+        struct nvif_device *device = &nouveau_drm(dev)->device;
         return nvif_rd32(device, reg);
 }