drm/msm/dsi: Add DSI PLL clock driver support

DSI byte clock and pixel clocks are sourced from DSI PLL.
This change adds the DSI PLL source clock driver under
common clock framework.

This change handles DSI 28nm PLL only.

Signed-off-by: Hai Li <hali@codeaurora.org>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Stephane Viau <sviau@codeaurora.org>
Signed-off-by: Wentao Xu <wentaox@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>

1 files changed, 2 insertions, 1 deletions

diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h
index 10f54d4e379a..321964a6b27e 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.h
@@ -103,7 +103,8 @@ int msm_dsi_host_init(struct msm_dsi *msm_dsi);
 struct msm_dsi_phy;
 enum msm_dsi_phy_type {
         MSM_DSI_PHY_UNKNOWN,
-        MSM_DSI_PHY_28NM,
+        MSM_DSI_PHY_28NM_HPM,
+        MSM_DSI_PHY_28NM_LP,
         MSM_DSI_PHY_MAX
 };
 struct msm_dsi_phy *msm_dsi_phy_init(struct platform_device *pdev,