drm/i915: POSTING_READ the new rps value

In order to keep our cached values in sync with the hardware, we need a
posting read here.

CC: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 2 insertions, 0 deletions

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 36c64091bc90..4e86037ae6b4 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2338,6 +2338,8 @@ void gen6_set_rps(struct drm_device *dev, u8 val)
          */
         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
 
+        POSTING_READ(GEN6_RPNSWREQ);
+
         dev_priv->rps.cur_delay = val;
 
         trace_intel_gpu_freq_change(val * 50);