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authorBen Widawsky <benjamin.widawsky@intel.com>2014-01-28 23:25:41 -0500
committerDaniel Vetter <daniel.vetter@ffwll.ch>2014-02-12 12:53:14 -0500
commitabbf9d2c4886c036eb1556bb141c27c6a7e5a245 (patch)
tree90b218a38ad81e6a53cfac6e61af70a32111db9c /drivers/gpu/drm/i915/intel_pm.c
parent1c79b42fa508bb49db57033e45711239b1fe96e9 (diff)
drm/i915/bdw: Use centralized rc6 info print
Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Reviewed-by: Deepak S <deepak.s@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2edb8c77013e..e4a0c9cc226d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3276,10 +3276,10 @@ static void gen8_enable_rps(struct drm_device *dev)
3276 /* 3: Enable RC6 */ 3276 /* 3: Enable RC6 */
3277 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) 3277 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3278 rc6_mask = GEN6_RC_CTL_RC6_ENABLE; 3278 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
3279 DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off"); 3279 intel_print_rc6_info(dev, rc6_mask);
3280 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | 3280 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
3281 GEN6_RC_CTL_EI_MODE(1) | 3281 GEN6_RC_CTL_EI_MODE(1) |
3282 rc6_mask); 3282 rc6_mask);
3283 3283
3284 /* 4 Program defaults and thresholds for RPS*/ 3284 /* 4 Program defaults and thresholds for RPS*/
3285 I915_WRITE(GEN6_RPNSWREQ, HSW_FREQUENCY(10)); /* Request 500 MHz */ 3285 I915_WRITE(GEN6_RPNSWREQ, HSW_FREQUENCY(10)); /* Request 500 MHz */