diff options
author | Mika Kuoppala <mika.kuoppala@linux.intel.com> | 2016-06-07 10:19:01 -0400 |
---|---|---|
committer | Mika Kuoppala <mika.kuoppala@intel.com> | 2016-07-15 08:51:24 -0400 |
commit | 9146f308d5916e20c53afe3ee0bd4dbd562a0ef9 (patch) | |
tree | 5f1d4c4989b73f0a4e5e775876399cfdc6255e0f /drivers/gpu/drm/i915/intel_pm.c | |
parent | 3d042d4633d7b180e08abead7bd7de0bb194b256 (diff) |
drm/i915/kbl: Add WaDisableSDEUnitClockGating
Add this workaround until upto kbl revid B0.
References: HSD#1802092
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1465309159-30531-10-git-send-email-mika.kuoppala@intel.com
(cherry picked from commit 9498dba7b4ffe40a1e2b23d7718b77e49841248f)
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
-rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 18 |
1 files changed, 16 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 362597580c05..bff740ccb479 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c | |||
@@ -6702,11 +6702,25 @@ static void lpt_suspend_hw(struct drm_device *dev) | |||
6702 | } | 6702 | } |
6703 | } | 6703 | } |
6704 | 6704 | ||
6705 | static void kabylake_init_clock_gating(struct drm_device *dev) | ||
6706 | { | ||
6707 | struct drm_i915_private *dev_priv = dev->dev_private; | ||
6708 | |||
6709 | /* See Bspec note for PSR2_CTL bit 31, Wa#828:kbl */ | ||
6710 | I915_WRITE(CHICKEN_PAR1_1, | ||
6711 | I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP); | ||
6712 | |||
6713 | /* WaDisableSDEUnitClockGating:kbl */ | ||
6714 | if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0)) | ||
6715 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | | ||
6716 | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); | ||
6717 | } | ||
6718 | |||
6705 | static void skylake_init_clock_gating(struct drm_device *dev) | 6719 | static void skylake_init_clock_gating(struct drm_device *dev) |
6706 | { | 6720 | { |
6707 | struct drm_i915_private *dev_priv = dev->dev_private; | 6721 | struct drm_i915_private *dev_priv = dev->dev_private; |
6708 | 6722 | ||
6709 | /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,kbl */ | 6723 | /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl */ |
6710 | I915_WRITE(CHICKEN_PAR1_1, | 6724 | I915_WRITE(CHICKEN_PAR1_1, |
6711 | I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP); | 6725 | I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP); |
6712 | } | 6726 | } |
@@ -7178,7 +7192,7 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv) | |||
7178 | if (IS_SKYLAKE(dev_priv)) | 7192 | if (IS_SKYLAKE(dev_priv)) |
7179 | dev_priv->display.init_clock_gating = skylake_init_clock_gating; | 7193 | dev_priv->display.init_clock_gating = skylake_init_clock_gating; |
7180 | else if (IS_KABYLAKE(dev_priv)) | 7194 | else if (IS_KABYLAKE(dev_priv)) |
7181 | dev_priv->display.init_clock_gating = skylake_init_clock_gating; | 7195 | dev_priv->display.init_clock_gating = kabylake_init_clock_gating; |
7182 | else if (IS_BROXTON(dev_priv)) | 7196 | else if (IS_BROXTON(dev_priv)) |
7183 | dev_priv->display.init_clock_gating = bxt_init_clock_gating; | 7197 | dev_priv->display.init_clock_gating = bxt_init_clock_gating; |
7184 | else if (IS_BROADWELL(dev_priv)) | 7198 | else if (IS_BROADWELL(dev_priv)) |