diff options
author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2016-06-22 14:57:07 -0400 |
---|---|---|
committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2016-07-07 06:10:20 -0400 |
commit | d7edc4e57bfefc5c2830a01f013cebdb814f8ffb (patch) | |
tree | b2d804fb1ee865bebf5ef05a4f56a9ea6ff6e512 /drivers/gpu/drm/i915/intel_display.c | |
parent | cca0502b9c6bf4a289a5e71a9a3794e73973e9e3 (diff) |
drm/i915: Kill has_dsi_encoder
has_dsi_encoder was introduced to indicate that the pipe is driving
a DSI encoder. Now that we have the output_types bitmask that can
tell us the same thing, let's just kill has_dsi_encoder.
v2: Rebase, handle BXT DSI transcoder, rewrote commit message
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1466621833-5054-10-git-send-email-ville.syrjala@linux.intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 47 |
1 files changed, 19 insertions, 28 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 907945545f6b..8704355e471a 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c | |||
@@ -1959,7 +1959,7 @@ static void intel_enable_pipe(struct intel_crtc *crtc) | |||
1959 | * need the check. | 1959 | * need the check. |
1960 | */ | 1960 | */ |
1961 | if (HAS_GMCH_DISPLAY(dev_priv)) | 1961 | if (HAS_GMCH_DISPLAY(dev_priv)) |
1962 | if (crtc->config->has_dsi_encoder) | 1962 | if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI)) |
1963 | assert_dsi_pll_enabled(dev_priv); | 1963 | assert_dsi_pll_enabled(dev_priv); |
1964 | else | 1964 | else |
1965 | assert_pll_enabled(dev_priv, pipe); | 1965 | assert_pll_enabled(dev_priv, pipe); |
@@ -4829,7 +4829,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc) | |||
4829 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) | 4829 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
4830 | intel_dp_set_m_n(intel_crtc, M1_N1); | 4830 | intel_dp_set_m_n(intel_crtc, M1_N1); |
4831 | 4831 | ||
4832 | if (!intel_crtc->config->has_dsi_encoder) | 4832 | if (!transcoder_is_dsi(cpu_transcoder)) |
4833 | intel_set_pipe_timings(intel_crtc); | 4833 | intel_set_pipe_timings(intel_crtc); |
4834 | 4834 | ||
4835 | intel_set_pipe_src_size(intel_crtc); | 4835 | intel_set_pipe_src_size(intel_crtc); |
@@ -4845,7 +4845,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc) | |||
4845 | &intel_crtc->config->fdi_m_n, NULL); | 4845 | &intel_crtc->config->fdi_m_n, NULL); |
4846 | } | 4846 | } |
4847 | 4847 | ||
4848 | if (!intel_crtc->config->has_dsi_encoder) | 4848 | if (!transcoder_is_dsi(cpu_transcoder)) |
4849 | haswell_set_pipeconf(crtc); | 4849 | haswell_set_pipeconf(crtc); |
4850 | 4850 | ||
4851 | haswell_set_pipemisc(crtc); | 4851 | haswell_set_pipemisc(crtc); |
@@ -4867,7 +4867,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc) | |||
4867 | if (intel_crtc->config->has_pch_encoder) | 4867 | if (intel_crtc->config->has_pch_encoder) |
4868 | dev_priv->display.fdi_link_train(crtc); | 4868 | dev_priv->display.fdi_link_train(crtc); |
4869 | 4869 | ||
4870 | if (!intel_crtc->config->has_dsi_encoder) | 4870 | if (!transcoder_is_dsi(cpu_transcoder)) |
4871 | intel_ddi_enable_pipe_clock(intel_crtc); | 4871 | intel_ddi_enable_pipe_clock(intel_crtc); |
4872 | 4872 | ||
4873 | if (INTEL_INFO(dev)->gen >= 9) | 4873 | if (INTEL_INFO(dev)->gen >= 9) |
@@ -4882,7 +4882,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc) | |||
4882 | intel_color_load_luts(&pipe_config->base); | 4882 | intel_color_load_luts(&pipe_config->base); |
4883 | 4883 | ||
4884 | intel_ddi_set_pipe_settings(crtc); | 4884 | intel_ddi_set_pipe_settings(crtc); |
4885 | if (!intel_crtc->config->has_dsi_encoder) | 4885 | if (!transcoder_is_dsi(cpu_transcoder)) |
4886 | intel_ddi_enable_transcoder_func(crtc); | 4886 | intel_ddi_enable_transcoder_func(crtc); |
4887 | 4887 | ||
4888 | if (dev_priv->display.initial_watermarks != NULL) | 4888 | if (dev_priv->display.initial_watermarks != NULL) |
@@ -4891,7 +4891,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc) | |||
4891 | intel_update_watermarks(crtc); | 4891 | intel_update_watermarks(crtc); |
4892 | 4892 | ||
4893 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ | 4893 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ |
4894 | if (!intel_crtc->config->has_dsi_encoder) | 4894 | if (!transcoder_is_dsi(cpu_transcoder)) |
4895 | intel_enable_pipe(intel_crtc); | 4895 | intel_enable_pipe(intel_crtc); |
4896 | 4896 | ||
4897 | if (intel_crtc->config->has_pch_encoder) | 4897 | if (intel_crtc->config->has_pch_encoder) |
@@ -5024,13 +5024,13 @@ static void haswell_crtc_disable(struct drm_crtc *crtc) | |||
5024 | assert_vblank_disabled(crtc); | 5024 | assert_vblank_disabled(crtc); |
5025 | 5025 | ||
5026 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ | 5026 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ |
5027 | if (!intel_crtc->config->has_dsi_encoder) | 5027 | if (!transcoder_is_dsi(cpu_transcoder)) |
5028 | intel_disable_pipe(intel_crtc); | 5028 | intel_disable_pipe(intel_crtc); |
5029 | 5029 | ||
5030 | if (intel_crtc->config->dp_encoder_is_mst) | 5030 | if (intel_crtc->config->dp_encoder_is_mst) |
5031 | intel_ddi_set_vc_payload_alloc(crtc, false); | 5031 | intel_ddi_set_vc_payload_alloc(crtc, false); |
5032 | 5032 | ||
5033 | if (!intel_crtc->config->has_dsi_encoder) | 5033 | if (!transcoder_is_dsi(cpu_transcoder)) |
5034 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); | 5034 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
5035 | 5035 | ||
5036 | if (INTEL_INFO(dev)->gen >= 9) | 5036 | if (INTEL_INFO(dev)->gen >= 9) |
@@ -5038,7 +5038,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc) | |||
5038 | else | 5038 | else |
5039 | ironlake_pfit_disable(intel_crtc, false); | 5039 | ironlake_pfit_disable(intel_crtc, false); |
5040 | 5040 | ||
5041 | if (!intel_crtc->config->has_dsi_encoder) | 5041 | if (!transcoder_is_dsi(cpu_transcoder)) |
5042 | intel_ddi_disable_pipe_clock(intel_crtc); | 5042 | intel_ddi_disable_pipe_clock(intel_crtc); |
5043 | 5043 | ||
5044 | for_each_encoder_on_crtc(dev, crtc, encoder) | 5044 | for_each_encoder_on_crtc(dev, crtc, encoder) |
@@ -6279,7 +6279,7 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc) | |||
6279 | if (encoder->post_disable) | 6279 | if (encoder->post_disable) |
6280 | encoder->post_disable(encoder); | 6280 | encoder->post_disable(encoder); |
6281 | 6281 | ||
6282 | if (!intel_crtc->config->has_dsi_encoder) { | 6282 | if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) { |
6283 | if (IS_CHERRYVIEW(dev)) | 6283 | if (IS_CHERRYVIEW(dev)) |
6284 | chv_disable_pll(dev_priv, pipe); | 6284 | chv_disable_pll(dev_priv, pipe); |
6285 | else if (IS_VALLEYVIEW(dev)) | 6285 | else if (IS_VALLEYVIEW(dev)) |
@@ -7278,7 +7278,7 @@ static void vlv_compute_dpll(struct intel_crtc *crtc, | |||
7278 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | 7278 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
7279 | 7279 | ||
7280 | /* DPLL not used with DSI, but still need the rest set up */ | 7280 | /* DPLL not used with DSI, but still need the rest set up */ |
7281 | if (!pipe_config->has_dsi_encoder) | 7281 | if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI)) |
7282 | pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE | | 7282 | pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE | |
7283 | DPLL_EXT_BUFFER_ENABLE_VLV; | 7283 | DPLL_EXT_BUFFER_ENABLE_VLV; |
7284 | 7284 | ||
@@ -7295,7 +7295,7 @@ static void chv_compute_dpll(struct intel_crtc *crtc, | |||
7295 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | 7295 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
7296 | 7296 | ||
7297 | /* DPLL not used with DSI, but still need the rest set up */ | 7297 | /* DPLL not used with DSI, but still need the rest set up */ |
7298 | if (!pipe_config->has_dsi_encoder) | 7298 | if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI)) |
7299 | pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE; | 7299 | pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE; |
7300 | 7300 | ||
7301 | pipe_config->dpll_hw_state.dpll_md = | 7301 | pipe_config->dpll_hw_state.dpll_md = |
@@ -9858,10 +9858,7 @@ static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state) | |||
9858 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, | 9858 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
9859 | struct intel_crtc_state *crtc_state) | 9859 | struct intel_crtc_state *crtc_state) |
9860 | { | 9860 | { |
9861 | struct intel_encoder *intel_encoder = | 9861 | if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) { |
9862 | intel_ddi_get_crtc_new_encoder(crtc_state); | ||
9863 | |||
9864 | if (intel_encoder->type != INTEL_OUTPUT_DSI) { | ||
9865 | if (!intel_ddi_pll_select(crtc, crtc_state)) | 9862 | if (!intel_ddi_pll_select(crtc, crtc_state)) |
9866 | return -EINVAL; | 9863 | return -EINVAL; |
9867 | } | 9864 | } |
@@ -10028,8 +10025,6 @@ static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, | |||
10028 | enum transcoder cpu_transcoder; | 10025 | enum transcoder cpu_transcoder; |
10029 | u32 tmp; | 10026 | u32 tmp; |
10030 | 10027 | ||
10031 | pipe_config->has_dsi_encoder = false; | ||
10032 | |||
10033 | for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { | 10028 | for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { |
10034 | if (port == PORT_A) | 10029 | if (port == PORT_A) |
10035 | cpu_transcoder = TRANSCODER_DSI_A; | 10030 | cpu_transcoder = TRANSCODER_DSI_A; |
@@ -10061,11 +10056,10 @@ static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, | |||
10061 | continue; | 10056 | continue; |
10062 | 10057 | ||
10063 | pipe_config->cpu_transcoder = cpu_transcoder; | 10058 | pipe_config->cpu_transcoder = cpu_transcoder; |
10064 | pipe_config->has_dsi_encoder = true; | ||
10065 | break; | 10059 | break; |
10066 | } | 10060 | } |
10067 | 10061 | ||
10068 | return pipe_config->has_dsi_encoder; | 10062 | return transcoder_is_dsi(pipe_config->cpu_transcoder); |
10069 | } | 10063 | } |
10070 | 10064 | ||
10071 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, | 10065 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
@@ -10129,18 +10123,16 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, | |||
10129 | 10123 | ||
10130 | active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask); | 10124 | active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask); |
10131 | 10125 | ||
10132 | if (IS_BROXTON(dev_priv)) { | 10126 | if (IS_BROXTON(dev_priv) && |
10133 | bxt_get_dsi_transcoder_state(crtc, pipe_config, | 10127 | bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) { |
10134 | &power_domain_mask); | 10128 | WARN_ON(active); |
10135 | WARN_ON(active && pipe_config->has_dsi_encoder); | 10129 | active = true; |
10136 | if (pipe_config->has_dsi_encoder) | ||
10137 | active = true; | ||
10138 | } | 10130 | } |
10139 | 10131 | ||
10140 | if (!active) | 10132 | if (!active) |
10141 | goto out; | 10133 | goto out; |
10142 | 10134 | ||
10143 | if (!pipe_config->has_dsi_encoder) { | 10135 | if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) { |
10144 | haswell_get_ddi_port_state(crtc, pipe_config); | 10136 | haswell_get_ddi_port_state(crtc, pipe_config); |
10145 | intel_get_pipe_timings(crtc, pipe_config); | 10137 | intel_get_pipe_timings(crtc, pipe_config); |
10146 | } | 10138 | } |
@@ -12783,7 +12775,6 @@ intel_pipe_config_compare(struct drm_device *dev, | |||
12783 | } else | 12775 | } else |
12784 | PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); | 12776 | PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); |
12785 | 12777 | ||
12786 | PIPE_CONF_CHECK_I(has_dsi_encoder); | ||
12787 | PIPE_CONF_CHECK_X(output_types); | 12778 | PIPE_CONF_CHECK_X(output_types); |
12788 | 12779 | ||
12789 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); | 12780 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |