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authorDamien Lespiau <damien.lespiau@intel.com>2015-06-04 11:56:18 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2015-06-15 08:32:49 -0400
commitcaf4e2527599a86f1b7d6c7e13546d80e7e50a7c (patch)
treea4c7336d05bb79827709272e99ef46688a184b74 /drivers/gpu/drm/i915/intel_display.c
parentabd41dc93c37abc89fb0470a8195c58f37aa52ac (diff)
drm/i915: Make sure our labels start at column 0
I noticed one of those and it turned out we have a few lingering around. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 193ba79e5a41..9c07098d2e13 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7077,7 +7077,7 @@ static int i965gm_get_display_clock_speed(struct drm_device *dev)
7077 7077
7078 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); 7078 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7079 7079
7080 fail: 7080fail:
7081 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp); 7081 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7082 return 200000; 7082 return 200000;
7083} 7083}
@@ -7118,7 +7118,7 @@ static int g33_get_display_clock_speed(struct drm_device *dev)
7118 7118
7119 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); 7119 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7120 7120
7121 fail: 7121fail:
7122 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp); 7122 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7123 return 190476; 7123 return 190476;
7124} 7124}