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authorMaarten Lankhorst <maarten.lankhorst@linux.intel.com>2015-08-27 09:44:05 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2015-09-14 04:03:13 -0400
commitbfd16b2a23dc99f2af3f5c4f54aa153347f2dc3c (patch)
treeb04131f041a00948d19217ce67154b50120abaf9 /drivers/gpu/drm/i915/intel_display.c
parentf4502c25ebd04691f284fdafff4a5613299c36dc (diff)
drm/i915: Make updating pipe without modeset atomic.
Instead of doing a hack during primary plane commit the state is updated during atomic evasion. It handles differences in pipe size and the panel fitter. This is continuing on top of Daniel's work to make faster modesets atomic, and not yet enabled by default. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> [danvet: - simplify/future-proof if ladder that Jesse spotted - resolve conflict in pipe_config_check and don't spuriously move the code.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c106
1 files changed, 66 insertions, 40 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 19049198364a..1691ec23bb95 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -112,6 +112,9 @@ static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_cr
112 struct intel_crtc_state *crtc_state); 112 struct intel_crtc_state *crtc_state);
113static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, 113static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
114 int num_connectors); 114 int num_connectors);
115static void skylake_pfit_enable(struct intel_crtc *crtc);
116static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
117static void ironlake_pfit_enable(struct intel_crtc *crtc);
115static void intel_modeset_setup_hw_state(struct drm_device *dev); 118static void intel_modeset_setup_hw_state(struct drm_device *dev);
116 119
117typedef struct { 120typedef struct {
@@ -3265,14 +3268,20 @@ static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3265 return pending; 3268 return pending;
3266} 3269}
3267 3270
3268static void intel_update_pipe_size(struct intel_crtc *crtc) 3271static void intel_update_pipe_config(struct intel_crtc *crtc,
3272 struct intel_crtc_state *old_crtc_state)
3269{ 3273{
3270 struct drm_device *dev = crtc->base.dev; 3274 struct drm_device *dev = crtc->base.dev;
3271 struct drm_i915_private *dev_priv = dev->dev_private; 3275 struct drm_i915_private *dev_priv = dev->dev_private;
3272 const struct drm_display_mode *adjusted_mode; 3276 struct intel_crtc_state *pipe_config =
3277 to_intel_crtc_state(crtc->base.state);
3273 3278
3274 if (!i915.fastboot) 3279 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3275 return; 3280 crtc->base.mode = crtc->base.state->mode;
3281
3282 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3283 old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3284 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3276 3285
3277 if (HAS_DDI(dev)) 3286 if (HAS_DDI(dev))
3278 intel_set_pipe_csc(&crtc->base); 3287 intel_set_pipe_csc(&crtc->base);
@@ -3284,27 +3293,24 @@ static void intel_update_pipe_size(struct intel_crtc *crtc)
3284 * fastboot case, we'll flip, but if we don't update the pipesrc and 3293 * fastboot case, we'll flip, but if we don't update the pipesrc and
3285 * pfit state, we'll end up with a big fb scanned out into the wrong 3294 * pfit state, we'll end up with a big fb scanned out into the wrong
3286 * sized surface. 3295 * sized surface.
3287 *
3288 * To fix this properly, we need to hoist the checks up into
3289 * compute_mode_changes (or above), check the actual pfit state and
3290 * whether the platform allows pfit disable with pipe active, and only
3291 * then update the pipesrc and pfit state, even on the flip path.
3292 */ 3296 */
3293 3297
3294 adjusted_mode = &crtc->config->base.adjusted_mode;
3295
3296 I915_WRITE(PIPESRC(crtc->pipe), 3298 I915_WRITE(PIPESRC(crtc->pipe),
3297 ((adjusted_mode->crtc_hdisplay - 1) << 16) | 3299 ((pipe_config->pipe_src_w - 1) << 16) |
3298 (adjusted_mode->crtc_vdisplay - 1)); 3300 (pipe_config->pipe_src_h - 1));
3299 if (!crtc->config->pch_pfit.enabled && 3301
3300 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || 3302 /* on skylake this is done by detaching scalers */
3301 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { 3303 if (INTEL_INFO(dev)->gen >= 9) {
3302 I915_WRITE(PF_CTL(crtc->pipe), 0); 3304 skl_detach_scalers(crtc);
3303 I915_WRITE(PF_WIN_POS(crtc->pipe), 0); 3305
3304 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0); 3306 if (pipe_config->pch_pfit.enabled)
3307 skylake_pfit_enable(crtc);
3308 } else if (HAS_PCH_SPLIT(dev)) {
3309 if (pipe_config->pch_pfit.enabled)
3310 ironlake_pfit_enable(crtc);
3311 else if (old_crtc_state->pch_pfit.enabled)
3312 ironlake_pfit_disable(crtc, true);
3305 } 3313 }
3306 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3307 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3308} 3314}
3309 3315
3310static void intel_fdi_normal_train(struct drm_crtc *crtc) 3316static void intel_fdi_normal_train(struct drm_crtc *crtc)
@@ -4961,7 +4967,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc)
4961 } 4967 }
4962} 4968}
4963 4969
4964static void ironlake_pfit_disable(struct intel_crtc *crtc) 4970static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
4965{ 4971{
4966 struct drm_device *dev = crtc->base.dev; 4972 struct drm_device *dev = crtc->base.dev;
4967 struct drm_i915_private *dev_priv = dev->dev_private; 4973 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -4969,7 +4975,7 @@ static void ironlake_pfit_disable(struct intel_crtc *crtc)
4969 4975
4970 /* To avoid upsetting the power well on haswell only disable the pfit if 4976 /* To avoid upsetting the power well on haswell only disable the pfit if
4971 * it's in use. The hw state code will make sure we get this right. */ 4977 * it's in use. The hw state code will make sure we get this right. */
4972 if (crtc->config->pch_pfit.enabled) { 4978 if (force || crtc->config->pch_pfit.enabled) {
4973 I915_WRITE(PF_CTL(pipe), 0); 4979 I915_WRITE(PF_CTL(pipe), 0);
4974 I915_WRITE(PF_WIN_POS(pipe), 0); 4980 I915_WRITE(PF_WIN_POS(pipe), 0);
4975 I915_WRITE(PF_WIN_SZ(pipe), 0); 4981 I915_WRITE(PF_WIN_SZ(pipe), 0);
@@ -4996,7 +5002,7 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
4996 5002
4997 intel_disable_pipe(intel_crtc); 5003 intel_disable_pipe(intel_crtc);
4998 5004
4999 ironlake_pfit_disable(intel_crtc); 5005 ironlake_pfit_disable(intel_crtc, false);
5000 5006
5001 if (intel_crtc->config->has_pch_encoder) 5007 if (intel_crtc->config->has_pch_encoder)
5002 ironlake_fdi_disable(crtc); 5008 ironlake_fdi_disable(crtc);
@@ -5059,7 +5065,7 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
5059 if (INTEL_INFO(dev)->gen >= 9) 5065 if (INTEL_INFO(dev)->gen >= 9)
5060 skylake_scaler_disable(intel_crtc); 5066 skylake_scaler_disable(intel_crtc);
5061 else 5067 else
5062 ironlake_pfit_disable(intel_crtc); 5068 ironlake_pfit_disable(intel_crtc, false);
5063 5069
5064 intel_ddi_disable_pipe_clock(intel_crtc); 5070 intel_ddi_disable_pipe_clock(intel_crtc);
5065 5071
@@ -12218,7 +12224,6 @@ static bool intel_fuzzy_clock_check(int clock1, int clock2)
12218 base.head) \ 12224 base.head) \
12219 if (mask & (1 <<(intel_crtc)->pipe)) 12225 if (mask & (1 <<(intel_crtc)->pipe))
12220 12226
12221
12222static bool 12227static bool
12223intel_compare_m_n(unsigned int m, unsigned int n, 12228intel_compare_m_n(unsigned int m, unsigned int n,
12224 unsigned int m2, unsigned int n2, 12229 unsigned int m2, unsigned int n2,
@@ -12439,19 +12444,21 @@ intel_pipe_config_compare(struct drm_device *dev,
12439 DRM_MODE_FLAG_NVSYNC); 12444 DRM_MODE_FLAG_NVSYNC);
12440 } 12445 }
12441 12446
12442 PIPE_CONF_CHECK_I(pipe_src_w);
12443 PIPE_CONF_CHECK_I(pipe_src_h);
12444
12445 PIPE_CONF_CHECK_X(gmch_pfit.control); 12447 PIPE_CONF_CHECK_X(gmch_pfit.control);
12446 /* pfit ratios are autocomputed by the hw on gen4+ */ 12448 /* pfit ratios are autocomputed by the hw on gen4+ */
12447 if (INTEL_INFO(dev)->gen < 4) 12449 if (INTEL_INFO(dev)->gen < 4)
12448 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); 12450 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12449 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); 12451 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12450 12452
12451 PIPE_CONF_CHECK_I(pch_pfit.enabled); 12453 if (!adjust) {
12452 if (current_config->pch_pfit.enabled) { 12454 PIPE_CONF_CHECK_I(pipe_src_w);
12453 PIPE_CONF_CHECK_X(pch_pfit.pos); 12455 PIPE_CONF_CHECK_I(pipe_src_h);
12454 PIPE_CONF_CHECK_X(pch_pfit.size); 12456
12457 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12458 if (current_config->pch_pfit.enabled) {
12459 PIPE_CONF_CHECK_X(pch_pfit.pos);
12460 PIPE_CONF_CHECK_X(pch_pfit.size);
12461 }
12455 } 12462 }
12456 12463
12457 PIPE_CONF_CHECK_I(scaler_state.scaler_id); 12464 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
@@ -12616,7 +12623,8 @@ check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
12616 struct intel_crtc_state *pipe_config, *sw_config; 12623 struct intel_crtc_state *pipe_config, *sw_config;
12617 bool active; 12624 bool active;
12618 12625
12619 if (!needs_modeset(crtc->state)) 12626 if (!needs_modeset(crtc->state) &&
12627 !to_intel_crtc_state(crtc->state)->update_pipe)
12620 continue; 12628 continue;
12621 12629
12622 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state); 12630 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
@@ -12912,7 +12920,6 @@ static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12912 return ret; 12920 return ret;
12913} 12921}
12914 12922
12915
12916static int intel_modeset_checks(struct drm_atomic_state *state) 12923static int intel_modeset_checks(struct drm_atomic_state *state)
12917{ 12924{
12918 struct drm_device *dev = state->dev; 12925 struct drm_device *dev = state->dev;
@@ -13003,6 +13010,7 @@ static int intel_atomic_check(struct drm_device *dev,
13003 to_intel_crtc_state(crtc->state), 13010 to_intel_crtc_state(crtc->state),
13004 pipe_config, true)) { 13011 pipe_config, true)) {
13005 crtc_state->mode_changed = false; 13012 crtc_state->mode_changed = false;
13013 to_intel_crtc_state(crtc_state)->update_pipe = true;
13006 } 13014 }
13007 13015
13008 if (needs_modeset(crtc_state)) { 13016 if (needs_modeset(crtc_state)) {
@@ -13100,16 +13108,30 @@ static int intel_atomic_commit(struct drm_device *dev,
13100 for_each_crtc_in_state(state, crtc, crtc_state, i) { 13108 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13101 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 13109 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13102 bool modeset = needs_modeset(crtc->state); 13110 bool modeset = needs_modeset(crtc->state);
13111 bool update_pipe = !modeset &&
13112 to_intel_crtc_state(crtc->state)->update_pipe;
13113 unsigned long put_domains = 0;
13103 13114
13104 if (modeset && crtc->state->active) { 13115 if (modeset && crtc->state->active) {
13105 update_scanline_offset(to_intel_crtc(crtc)); 13116 update_scanline_offset(to_intel_crtc(crtc));
13106 dev_priv->display.crtc_enable(crtc); 13117 dev_priv->display.crtc_enable(crtc);
13107 } 13118 }
13108 13119
13120 if (update_pipe) {
13121 put_domains = modeset_get_crtc_power_domains(crtc);
13122
13123 /* make sure intel_modeset_check_state runs */
13124 any_ms = true;
13125 }
13126
13109 if (!modeset) 13127 if (!modeset)
13110 intel_pre_plane_update(intel_crtc); 13128 intel_pre_plane_update(intel_crtc);
13111 13129
13112 drm_atomic_helper_commit_planes_on_crtc(crtc_state); 13130 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13131
13132 if (put_domains)
13133 modeset_put_power_domains(dev_priv, put_domains);
13134
13113 intel_post_plane_update(intel_crtc); 13135 intel_post_plane_update(intel_crtc);
13114 } 13136 }
13115 13137
@@ -13426,10 +13448,6 @@ intel_commit_primary_plane(struct drm_plane *plane,
13426 if (!crtc->state->active) 13448 if (!crtc->state->active)
13427 return; 13449 return;
13428 13450
13429 if (state->visible)
13430 /* FIXME: kill this fastboot hack */
13431 intel_update_pipe_size(intel_crtc);
13432
13433 dev_priv->display.update_primary_plane(crtc, fb, 13451 dev_priv->display.update_primary_plane(crtc, fb,
13434 state->src.x1 >> 16, 13452 state->src.x1 >> 16,
13435 state->src.y1 >> 16); 13453 state->src.y1 >> 16);
@@ -13450,6 +13468,9 @@ static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13450{ 13468{
13451 struct drm_device *dev = crtc->dev; 13469 struct drm_device *dev = crtc->dev;
13452 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 13470 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13471 struct intel_crtc_state *old_intel_state =
13472 to_intel_crtc_state(old_crtc_state);
13473 bool modeset = needs_modeset(crtc->state);
13453 13474
13454 if (intel_crtc->atomic.update_wm_pre) 13475 if (intel_crtc->atomic.update_wm_pre)
13455 intel_update_watermarks(crtc); 13476 intel_update_watermarks(crtc);
@@ -13458,7 +13479,12 @@ static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13458 if (crtc->state->active) 13479 if (crtc->state->active)
13459 intel_pipe_update_start(intel_crtc); 13480 intel_pipe_update_start(intel_crtc);
13460 13481
13461 if (!needs_modeset(crtc->state) && INTEL_INFO(dev)->gen >= 9) 13482 if (modeset)
13483 return;
13484
13485 if (to_intel_crtc_state(crtc->state)->update_pipe)
13486 intel_update_pipe_config(intel_crtc, old_intel_state);
13487 else if (INTEL_INFO(dev)->gen >= 9)
13462 skl_detach_scalers(intel_crtc); 13488 skl_detach_scalers(intel_crtc);
13463} 13489}
13464 13490