drm/i915: state readout and cross checking for limited_color_range

At least on those platforms which have a simple bit and don't rely
on the fully programmable CSC unit to do this.

Note that with the current code this includes CHV, but I guess that
platform will match BYT.

Reviewed-by: Naresh Kumar Kachhi <naresh.kumar.kachhi@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 9 insertions, 0 deletions

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 6240f1f543b9..3a5b2ed53220 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6062,6 +6062,9 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
                 }
         }
 
+        if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
+                pipe_config->limited_color_range = true;
+
         if (INTEL_INFO(dev)->gen < 4)
                 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
 
@@ -7068,6 +7071,9 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
                 break;
         }
 
+        if (tmp & PIPECONF_COLOR_RANGE_SELECT)
+                pipe_config->limited_color_range = true;
+
         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
                 struct intel_shared_dpll *pll;
 
@@ -9884,6 +9890,9 @@ intel_pipe_config_compare(struct drm_device *dev,
 
         PIPE_CONF_CHECK_I(pixel_multiplier);
         PIPE_CONF_CHECK_I(has_hdmi_sink);
+        if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
+            IS_VALLEYVIEW(dev))
+                PIPE_CONF_CHECK_I(limited_color_range);
 
         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
                               DRM_MODE_FLAG_INTERLACE);