Revert "drm/i915/ilk: Don't disable SSC source if it's in use"

This reverts commit f165d2834ceb3d5c29bebadadc27629bebf402ac.

It breaks one of our CI systems. Quoting from Ville:

[   13.100979] [drm:ironlake_init_pch_refclk] has_panel 1 has_lvds 1 has_ck505 0 using_ssc_source 1
[   13.101413] ------------[ cut here ]------------
[   13.101429] kernel BUG at drivers/gpu/drm/i915/intel_display.c:8528!

"which is the 'BUG_ON(val != final)' at the end of ironlake_init_pch_refclk()."

Cc: stable@vger.kernel.org
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Lyude <cpaul@redhat.com>
Cc: marius.c.vlad@intel.com
References: https://www.spinics.net/lists/dri-devel/msg109557.html
Acked-by: Lyude <cpaul@redhat.com>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>

1 files changed, 13 insertions, 36 deletions

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 12ff79594bc1..473c8fdb38b9 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8361,14 +8361,12 @@ static void ironlake_init_pch_refclk(struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
         struct intel_encoder *encoder;
-        int i;
         u32 val, final;
         bool has_lvds = false;
         bool has_cpu_edp = false;
         bool has_panel = false;
         bool has_ck505 = false;
         bool can_ssc = false;
-        bool using_ssc_source = false;
 
         /* We need to take the global config into account */
         for_each_intel_encoder(dev, encoder) {
@@ -8395,22 +8393,8 @@ static void ironlake_init_pch_refclk(struct drm_device *dev)
                 can_ssc = true;
         }
 
-        /* Check if any DPLLs are using the SSC source */
-        for (i = 0; i < dev_priv->num_shared_dpll; i++) {
-                u32 temp = I915_READ(PCH_DPLL(i));
-
-                if (!(temp & DPLL_VCO_ENABLE))
-                        continue;
-
-                if ((temp & PLL_REF_INPUT_MASK) ==
-                    PLLB_REF_INPUT_SPREADSPECTRUMIN) {
-                        using_ssc_source = true;
-                        break;
-                }
-        }
-
-        DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
-                      has_panel, has_lvds, has_ck505, using_ssc_source);
+        DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
+                      has_panel, has_lvds, has_ck505);
 
         /* Ironlake: try to setup display ref clock before DPLL
          * enabling. This is only under driver's control after
@@ -8430,12 +8414,9 @@ static void ironlake_init_pch_refclk(struct drm_device *dev)
         else
                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
 
+        final &= ~DREF_SSC_SOURCE_MASK;
         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
-
-        if (!using_ssc_source) {
-                final &= ~DREF_SSC_SOURCE_MASK;
-                final &= ~DREF_SSC1_ENABLE;
-        }
+        final &= ~DREF_SSC1_ENABLE;
 
         if (has_panel) {
                 final |= DREF_SSC_SOURCE_ENABLE;
@@ -8498,7 +8479,7 @@ static void ironlake_init_pch_refclk(struct drm_device *dev)
                 POSTING_READ(PCH_DREF_CONTROL);
                 udelay(200);
         } else {
-                DRM_DEBUG_KMS("Disabling CPU source output\n");
+                DRM_DEBUG_KMS("Disabling SSC entirely\n");
 
                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
 
@@ -8509,20 +8490,16 @@ static void ironlake_init_pch_refclk(struct drm_device *dev)
                 POSTING_READ(PCH_DREF_CONTROL);
                 udelay(200);
 
-                if (!using_ssc_source) {
-                        DRM_DEBUG_KMS("Disabling SSC source\n");
-
-                        /* Turn off the SSC source */
-                        val &= ~DREF_SSC_SOURCE_MASK;
-                        val |= DREF_SSC_SOURCE_DISABLE;
+                /* Turn off the SSC source */
+                val &= ~DREF_SSC_SOURCE_MASK;
+                val |= DREF_SSC_SOURCE_DISABLE;
 
-                        /* Turn off SSC1 */
-                        val &= ~DREF_SSC1_ENABLE;
+                /* Turn off SSC1 */
+                val &= ~DREF_SSC1_ENABLE;
 
-                        I915_WRITE(PCH_DREF_CONTROL, val);
-                        POSTING_READ(PCH_DREF_CONTROL);
-                        udelay(200);
-                }
+                I915_WRITE(PCH_DREF_CONTROL, val);
+                POSTING_READ(PCH_DREF_CONTROL);
+                udelay(200);
         }
 
         BUG_ON(val != final);