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authorVille Syrjälä <ville.syrjala@linux.intel.com>2014-08-12 12:39:54 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2014-08-13 08:23:37 -0400
commit8ac5466926daef2406f7b25e9a272567cb81adb0 (patch)
tree55a2dfebed636d8ff8f20b3a43cd5224b3f36bf3 /drivers/gpu/drm/i915/intel_display.c
parentd7ce484eeec43079ad842f1d351f53998ed6bb30 (diff)
drm/i915: Unify ivb_update_cursor() and i9xx_update_cursor()
Ever since commit 5efb3e2838536832c9b6872512e6b6daf592cee9 Author: Ville Syrjälä <ville.syrjala@linux.intel.com> Date: Wed Apr 9 13:28:53 2014 +0300 drm/i915/chv: Add cursor pipe offsets the only difference between i9xx_update_cursor() and ivb_update_cursor() was the hsw+ pipe csc handling. Let's unify them and we can rid outselves of some duplicated code. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c41
1 files changed, 1 insertions, 40 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index cd3dc3b72798..b3fb127131f0 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8104,43 +8104,6 @@ static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8104 } 8104 }
8105 cntl |= pipe << 28; /* Connect to correct pipe */ 8105 cntl |= pipe << 28; /* Connect to correct pipe */
8106 } 8106 }
8107 if (intel_crtc->cursor_cntl != cntl) {
8108 I915_WRITE(CURCNTR(pipe), cntl);
8109 POSTING_READ(CURCNTR(pipe));
8110 intel_crtc->cursor_cntl = cntl;
8111 }
8112
8113 /* and commit changes on next vblank */
8114 I915_WRITE(CURBASE(pipe), base);
8115 POSTING_READ(CURBASE(pipe));
8116}
8117
8118static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
8119{
8120 struct drm_device *dev = crtc->dev;
8121 struct drm_i915_private *dev_priv = dev->dev_private;
8122 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8123 int pipe = intel_crtc->pipe;
8124 uint32_t cntl;
8125
8126 cntl = 0;
8127 if (base) {
8128 cntl = MCURSOR_GAMMA_ENABLE;
8129 switch (intel_crtc->cursor_width) {
8130 case 64:
8131 cntl |= CURSOR_MODE_64_ARGB_AX;
8132 break;
8133 case 128:
8134 cntl |= CURSOR_MODE_128_ARGB_AX;
8135 break;
8136 case 256:
8137 cntl |= CURSOR_MODE_256_ARGB_AX;
8138 break;
8139 default:
8140 WARN_ON(1);
8141 return;
8142 }
8143 }
8144 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) 8107 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8145 cntl |= CURSOR_PIPE_CSC_ENABLE; 8108 cntl |= CURSOR_PIPE_CSC_ENABLE;
8146 8109
@@ -8199,9 +8162,7 @@ static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8199 8162
8200 I915_WRITE(CURPOS(pipe), pos); 8163 I915_WRITE(CURPOS(pipe), pos);
8201 8164
8202 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) 8165 if (IS_845G(dev) || IS_I865G(dev))
8203 ivb_update_cursor(crtc, base);
8204 else if (IS_845G(dev) || IS_I865G(dev))
8205 i845_update_cursor(crtc, base); 8166 i845_update_cursor(crtc, base);
8206 else 8167 else
8207 i9xx_update_cursor(crtc, base); 8168 i9xx_update_cursor(crtc, base);