diff options
author | Jesse Barnes <jbarnes@virtuousgeek.org> | 2011-01-04 18:09:38 -0500 |
---|---|---|
committer | Chris Wilson <chris@chris-wilson.co.uk> | 2011-01-19 07:37:48 -0500 |
commit | 6f06ce184c765fd8d50669a8d12fdd566c920859 (patch) | |
tree | e01468f801eb21455d557f29c960541a76aa3630 /drivers/gpu/drm/i915/intel_display.c | |
parent | 0fc932b8ec36116bb759105ce910b0475e63112a (diff) |
drm/i915: set phase sync pointer override enable before setting phase sync pointer
We need to unlock the phase sync pointer enable bit before we can
actually enable the phase sync pointer workaround on Ironlake.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index aee2abae81ec..2842dbe3ec0d 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c | |||
@@ -2273,7 +2273,11 @@ static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |||
2273 | udelay(150); | 2273 | udelay(150); |
2274 | 2274 | ||
2275 | /* Ironlake workaround, enable clock pointer after FDI enable*/ | 2275 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
2276 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_ENABLE); | 2276 | if (HAS_PCH_IBX(dev)) { |
2277 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); | ||
2278 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | ||
2279 | FDI_RX_PHASE_SYNC_POINTER_EN); | ||
2280 | } | ||
2277 | 2281 | ||
2278 | reg = FDI_RX_IIR(pipe); | 2282 | reg = FDI_RX_IIR(pipe); |
2279 | for (tries = 0; tries < 5; tries++) { | 2283 | for (tries = 0; tries < 5; tries++) { |
@@ -2516,10 +2520,12 @@ static void ironlake_fdi_disable(struct drm_crtc *crtc) | |||
2516 | udelay(100); | 2520 | udelay(100); |
2517 | 2521 | ||
2518 | /* Ironlake workaround, disable clock pointer after downing FDI */ | 2522 | /* Ironlake workaround, disable clock pointer after downing FDI */ |
2519 | if (HAS_PCH_IBX(dev)) | 2523 | if (HAS_PCH_IBX(dev)) { |
2524 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); | ||
2520 | I915_WRITE(FDI_RX_CHICKEN(pipe), | 2525 | I915_WRITE(FDI_RX_CHICKEN(pipe), |
2521 | I915_READ(FDI_RX_CHICKEN(pipe) & | 2526 | I915_READ(FDI_RX_CHICKEN(pipe) & |
2522 | ~FDI_RX_PHASE_SYNC_POINTER_ENABLE)); | 2527 | ~FDI_RX_PHASE_SYNC_POINTER_EN)); |
2528 | } | ||
2523 | 2529 | ||
2524 | /* still set train pattern 1 */ | 2530 | /* still set train pattern 1 */ |
2525 | reg = FDI_TX_CTL(pipe); | 2531 | reg = FDI_TX_CTL(pipe); |