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authorAnder Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>2015-04-21 10:13:21 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2015-05-08 07:04:09 -0400
commit4978cc93d9ac240b435ce60431aef24239b4c270 (patch)
tree8d48e9a36fb0197593d84a21ad6250682ac4ab92 /drivers/gpu/drm/i915/intel_display.c
parent2bfb4627580ae91d2978e1c071ed1a4b5039f2fd (diff)
drm/i915: Preserve shared DPLL information in new pipe_config
When a new pipe_config is calculated, the fields related to shared dplls are reset, under the assumption that they will be recalculated as part of the modeset, which is true with the current state of the code. As we convert to atomic, however, it will be possible to calculate a new pipe_config and skip the modeset. In that case, after the state swap we still want the shared dplls to be preserved. Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_display.c')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c16
1 files changed, 14 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index e3e4a04a18bf..b392ce3dd6c1 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11467,13 +11467,21 @@ clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11467{ 11467{
11468 struct drm_crtc_state tmp_state; 11468 struct drm_crtc_state tmp_state;
11469 struct intel_crtc_scaler_state scaler_state; 11469 struct intel_crtc_scaler_state scaler_state;
11470 struct intel_dpll_hw_state dpll_hw_state;
11471 enum intel_dpll_id shared_dpll;
11470 11472
11471 /* Clear only the intel specific part of the crtc state excluding scalers */ 11473 /* Clear only the intel specific part of the crtc state excluding scalers */
11472 tmp_state = crtc_state->base; 11474 tmp_state = crtc_state->base;
11473 scaler_state = crtc_state->scaler_state; 11475 scaler_state = crtc_state->scaler_state;
11476 shared_dpll = crtc_state->shared_dpll;
11477 dpll_hw_state = crtc_state->dpll_hw_state;
11478
11474 memset(crtc_state, 0, sizeof *crtc_state); 11479 memset(crtc_state, 0, sizeof *crtc_state);
11480
11475 crtc_state->base = tmp_state; 11481 crtc_state->base = tmp_state;
11476 crtc_state->scaler_state = scaler_state; 11482 crtc_state->scaler_state = scaler_state;
11483 crtc_state->shared_dpll = shared_dpll;
11484 crtc_state->dpll_hw_state = dpll_hw_state;
11477} 11485}
11478 11486
11479static int 11487static int
@@ -11502,7 +11510,6 @@ intel_modeset_pipe_config(struct drm_crtc *crtc,
11502 11510
11503 pipe_config->cpu_transcoder = 11511 pipe_config->cpu_transcoder =
11504 (enum transcoder) to_intel_crtc(crtc)->pipe; 11512 (enum transcoder) to_intel_crtc(crtc)->pipe;
11505 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
11506 11513
11507 /* 11514 /*
11508 * Sanitize sync polarity flags based on requested ones. If neither 11515 * Sanitize sync polarity flags based on requested ones. If neither
@@ -12266,9 +12273,14 @@ static int __intel_set_mode_setup_plls(struct drm_atomic_state *state)
12266 12273
12267 for_each_crtc_in_state(state, crtc, crtc_state, i) { 12274 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12268 intel_crtc = to_intel_crtc(crtc); 12275 intel_crtc = to_intel_crtc(crtc);
12276 intel_crtc_state = to_intel_crtc_state(crtc_state);
12269 12277
12270 if (needs_modeset(crtc_state)) 12278 if (needs_modeset(crtc_state)) {
12271 clear_pipes |= 1 << intel_crtc->pipe; 12279 clear_pipes |= 1 << intel_crtc->pipe;
12280 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
12281 memset(&intel_crtc_state->dpll_hw_state, 0,
12282 sizeof(intel_crtc_state->dpll_hw_state));
12283 }
12272 } 12284 }
12273 12285
12274 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes); 12286 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);