drm/i915/chv: Update Cherryview DPLL changes to support Port D. v2

The additional DPLL registers added to support Port D.  Besides, add
some new PHY control and status registers based on B-spec.

v2: Based on Ville review
	- Corrected DPIO_PHY_STATUS offset and name.
    - Rebase based on upstream change after introduce enum dpio_phy and
      enum dpio_channel.

v3: Rebased on top of Antti's 3-pipe prep patch. Note that the new offsets for
the DPLL registers aren't in place yet, so this introduces a slight regression.
But since 3 pipe support isn't fully enabled yet anyaway in -internal this
shouldn't matter too much.

Signed-off-by: Chon Ming Lee <chon.ming.lee@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

1 files changed, 9 insertions, 2 deletions

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 63055f1244d0..c42593fd53a5 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1535,21 +1535,28 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
                 struct intel_digital_port *dport)
 {
         u32 port_mask;
+        int dpll_reg;
 
         switch (dport->port) {
         case PORT_B:
                 port_mask = DPLL_PORTB_READY_MASK;
+                dpll_reg = DPLL(0);
                 break;
         case PORT_C:
                 port_mask = DPLL_PORTC_READY_MASK;
+                dpll_reg = DPLL(0);
+                break;
+        case PORT_D:
+                port_mask = DPLL_PORTD_READY_MASK;
+                dpll_reg = DPIO_PHY_STATUS;
                 break;
         default:
                 BUG();
         }
 
-        if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
+        if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
-                     port_name(dport->port), I915_READ(DPLL(0)));
+                     port_name(dport->port), I915_READ(dpll_reg));
 }
 
 /**