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| author | Imre Deak <imre.deak@intel.com> | 2014-01-29 06:25:41 -0500 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-01-29 14:46:05 -0500 |
| commit | dada1a9ffccc832b0130658d26454d37bf41f610 (patch) | |
| tree | 81dadc16744a85e923a7ffdc102c479c43aabb83 /drivers/gpu/drm/i915/i915_gem_evict.c | |
| parent | ec5e0cfb19e79ce3a87b281ce4c2682eb659fa6e (diff) | |
drm/i915: fix initial timestamps for PP sequencing logic
The initial jiffies value can be non-0, so set the inital panel power
sequencer timestamps accordingly. This didn't cause a problem on 64 bit
machines but on 32 bit jiffies is initially -300*HZ, so if the panel
power is initally off in the call from edp_panel_vdd_on()->
wait_panel_power_cycle() we'd wait up to ~300 sec more than needed.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_gem_evict.c')
0 files changed, 0 insertions, 0 deletions