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authorChris Wilson <chris@chris-wilson.co.uk>2015-04-27 08:41:14 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2015-05-20 05:25:45 -0400
commit2e2f351dbf29681d54a3a0f1003c5bb9bc832072 (patch)
tree1203ea9d322de8a584366af3dc252f2da3e52d8f /drivers/gpu/drm/i915/i915_gem.c
parent779949f4b1968d28229e7375fd199f54ed883dc4 (diff)
drm/i915: Remove domain flubbing from i915_gem_object_finish_gpu()
We no longer interpolate domains in the same manner, and even if we did, we should trust setting either of the other write domains would trigger an invalidation rather than force it. Remove the tweaking of the read_domains since it serves no purpose and use i915_gem_object_wait_rendering() directly. Note that this goes back to commit a8198eea156df47e0e843ac5c7d4c8774e121c42 Author: Chris Wilson <chris@chris-wilson.co.uk> Date: Wed Apr 13 22:04:09 2011 +0100 drm/i915: Introduce i915_gem_object_finish_gpu() and gpu domain tracking died in commit cc889e0f6ce6a63c62db17d702ecfed86d58083f Author: Daniel Vetter <daniel.vetter@ffwll.ch> Date: Wed Jun 13 20:45:19 2012 +0200 drm/i915: disable flushing_list/gpu_write_list which is more than 1 year older. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> [danvet: Add notes with information dug out of git history.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_gem.c')
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c26
1 files changed, 3 insertions, 23 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index fb48e7277252..5ff96f94c2ee 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -40,9 +40,6 @@
40 40
41static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); 41static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
42static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); 42static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
43static __must_check int
44i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
45 bool readonly);
46static void 43static void
47i915_gem_object_retire(struct drm_i915_gem_object *obj); 44i915_gem_object_retire(struct drm_i915_gem_object *obj);
48 45
@@ -1397,7 +1394,7 @@ i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj)
1397 * Ensures that all rendering to the object has completed and the object is 1394 * Ensures that all rendering to the object has completed and the object is
1398 * safe to unbind from the GTT or access from the CPU. 1395 * safe to unbind from the GTT or access from the CPU.
1399 */ 1396 */
1400static __must_check int 1397int
1401i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, 1398i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1402 bool readonly) 1399 bool readonly)
1403{ 1400{
@@ -3078,7 +3075,7 @@ int i915_vma_unbind(struct i915_vma *vma)
3078 3075
3079 BUG_ON(obj->pages == NULL); 3076 BUG_ON(obj->pages == NULL);
3080 3077
3081 ret = i915_gem_object_finish_gpu(obj); 3078 ret = i915_gem_object_wait_rendering(obj, false);
3082 if (ret) 3079 if (ret)
3083 return ret; 3080 return ret;
3084 /* Continue on if we fail due to EIO, the GPU is hung so we 3081 /* Continue on if we fail due to EIO, the GPU is hung so we
@@ -3853,7 +3850,7 @@ int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3853 } 3850 }
3854 3851
3855 if (i915_gem_obj_bound_any(obj)) { 3852 if (i915_gem_obj_bound_any(obj)) {
3856 ret = i915_gem_object_finish_gpu(obj); 3853 ret = i915_gem_object_wait_rendering(obj, false);
3857 if (ret) 3854 if (ret)
3858 return ret; 3855 return ret;
3859 3856
@@ -4044,23 +4041,6 @@ i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
4044 obj->pin_display--; 4041 obj->pin_display--;
4045} 4042}
4046 4043
4047int
4048i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
4049{
4050 int ret;
4051
4052 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
4053 return 0;
4054
4055 ret = i915_gem_object_wait_rendering(obj, false);
4056 if (ret)
4057 return ret;
4058
4059 /* Ensure that we invalidate the GPU's caches and TLBs. */
4060 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
4061 return 0;
4062}
4063
4064/** 4044/**
4065 * Moves a single object to the CPU read, and possibly write domain. 4045 * Moves a single object to the CPU read, and possibly write domain.
4066 * 4046 *