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authorAlex Deucher <alexander.deucher@amd.com>2015-04-16 15:34:14 -0400
committerAlex Deucher <alexander.deucher@amd.com>2015-06-03 21:03:08 -0400
commit7aa27c37739c1bea219b744b351c3a74f6eb6674 (patch)
tree09042746121534c23184f428748704098dab779a /drivers/gpu/drm/amd/include/asic_reg/uvd
parent8630f839e0d0c439098b084d8867b82e3aa6084a (diff)
drm/amdgpu: add UVD 5.0 register headers
These are register headers for the UVD (Universal Video Decoder) block on the GPU. Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Jammy Zhou <Jammy.Zhou@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/include/asic_reg/uvd')
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h114
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_enum.h1211
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h1046
3 files changed, 2371 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h
new file mode 100644
index 000000000000..eb4cf53427da
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_d.h
@@ -0,0 +1,114 @@
1/*
2 * UVD_5_0 Register documentation
3 *
4 * Copyright (C) 2014 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24#ifndef UVD_5_0_D_H
25#define UVD_5_0_D_H
26
27#define mmUVD_SEMA_ADDR_LOW 0x3bc0
28#define mmUVD_SEMA_ADDR_HIGH 0x3bc1
29#define mmUVD_SEMA_CMD 0x3bc2
30#define mmUVD_GPCOM_VCPU_CMD 0x3bc3
31#define mmUVD_GPCOM_VCPU_DATA0 0x3bc4
32#define mmUVD_GPCOM_VCPU_DATA1 0x3bc5
33#define mmUVD_ENGINE_CNTL 0x3bc6
34#define mmUVD_UDEC_ADDR_CONFIG 0x3bd3
35#define mmUVD_UDEC_DB_ADDR_CONFIG 0x3bd4
36#define mmUVD_UDEC_DBW_ADDR_CONFIG 0x3bd5
37#define mmUVD_LMI_RBC_RB_64BIT_BAR_LOW 0x3c69
38#define mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH 0x3c68
39#define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW 0x3c67
40#define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH 0x3c66
41#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW 0x3c5f
42#define mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH 0x3c5e
43#define mmUVD_SEMA_CNTL 0x3d00
44#define mmUVD_LMI_EXT40_ADDR 0x3d26
45#define mmUVD_CTX_INDEX 0x3d28
46#define mmUVD_CTX_DATA 0x3d29
47#define mmUVD_CGC_GATE 0x3d2a
48#define mmUVD_CGC_STATUS 0x3d2b
49#define mmUVD_CGC_CTRL 0x3d2c
50#define mmUVD_CGC_UDEC_STATUS 0x3d2d
51#define mmUVD_LMI_CTRL2 0x3d3d
52#define mmUVD_MASTINT_EN 0x3d40
53#define mmUVD_LMI_ADDR_EXT 0x3d65
54#define mmUVD_LMI_CTRL 0x3d66
55#define mmUVD_LMI_STATUS 0x3d67
56#define mmUVD_LMI_SWAP_CNTL 0x3d6d
57#define mmUVD_MP_SWAP_CNTL 0x3d6f
58#define mmUVD_MPC_CNTL 0x3d77
59#define mmUVD_MPC_SET_MUXA0 0x3d79
60#define mmUVD_MPC_SET_MUXA1 0x3d7a
61#define mmUVD_MPC_SET_MUXB0 0x3d7b
62#define mmUVD_MPC_SET_MUXB1 0x3d7c
63#define mmUVD_MPC_SET_MUX 0x3d7d
64#define mmUVD_MPC_SET_ALU 0x3d7e
65#define mmUVD_VCPU_CACHE_OFFSET0 0x3d82
66#define mmUVD_VCPU_CACHE_SIZE0 0x3d83
67#define mmUVD_VCPU_CACHE_OFFSET1 0x3d84
68#define mmUVD_VCPU_CACHE_SIZE1 0x3d85
69#define mmUVD_VCPU_CACHE_OFFSET2 0x3d86
70#define mmUVD_VCPU_CACHE_SIZE2 0x3d87
71#define mmUVD_VCPU_CNTL 0x3d98
72#define mmUVD_SOFT_RESET 0x3da0
73#define mmUVD_LMI_RBC_IB_VMID 0x3da1
74#define mmUVD_RBC_IB_SIZE 0x3da2
75#define mmUVD_LMI_RBC_RB_VMID 0x3da3
76#define mmUVD_RBC_RB_RPTR 0x3da4
77#define mmUVD_RBC_RB_WPTR 0x3da5
78#define mmUVD_RBC_RB_WPTR_CNTL 0x3da6
79#define mmUVD_RBC_RB_CNTL 0x3da9
80#define mmUVD_RBC_RB_RPTR_ADDR 0x3daa
81#define mmUVD_STATUS 0x3daf
82#define mmUVD_SEMA_TIMEOUT_STATUS 0x3db0
83#define mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL 0x3db1
84#define mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 0x3db2
85#define mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 0x3db3
86#define mmUVD_CONTEXT_ID 0x3dbd
87#define mmUVD_RBC_IB_SIZE_UPDATE 0x3df1
88#define mmUVD_SUVD_CGC_GATE 0x3be4
89#define mmUVD_SUVD_CGC_STATUS 0x3be5
90#define mmUVD_SUVD_CGC_CTRL 0x3be6
91#define ixUVD_LMI_VMID_INTERNAL 0x99
92#define ixUVD_LMI_VMID_INTERNAL2 0x9a
93#define ixUVD_LMI_CACHE_CTRL 0x9b
94#define ixUVD_LMI_SWAP_CNTL2 0xaa
95#define ixUVD_LMI_ADDR_EXT2 0xab
96#define ixUVD_CGC_MEM_CTRL 0xc0
97#define ixUVD_CGC_CTRL2 0xc1
98#define ixUVD_LMI_VMID_INTERNAL3 0x162
99#define mmUVD_PGFSM_CONFIG 0x38c0
100#define mmUVD_PGFSM_READ_TILE1 0x38c2
101#define mmUVD_PGFSM_READ_TILE2 0x38c3
102#define mmUVD_POWER_STATUS 0x38c4
103#define mmUVD_PGFSM_READ_TILE3 0x38c5
104#define mmUVD_PGFSM_READ_TILE4 0x38c6
105#define mmUVD_PGFSM_READ_TILE5 0x38c8
106#define mmUVD_PGFSM_READ_TILE6 0x38ee
107#define mmUVD_PGFSM_READ_TILE7 0x38ef
108#define mmUVD_MIF_CURR_ADDR_CONFIG 0x3992
109#define mmUVD_MIF_REF_ADDR_CONFIG 0x3993
110#define mmUVD_MIF_RECON1_ADDR_CONFIG 0x39c5
111#define ixUVD_MIF_SCLR_ADDR_CONFIG 0x4
112#define mmUVD_JPEG_ADDR_CONFIG 0x3a1f
113
114#endif /* UVD_5_0_D_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_enum.h b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_enum.h
new file mode 100644
index 000000000000..981086f8ee4e
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_enum.h
@@ -0,0 +1,1211 @@
1/*
2 * UVD_5_0 Register documentation
3 *
4 * Copyright (C) 2014 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24#ifndef UVD_5_0_ENUM_H
25#define UVD_5_0_ENUM_H
26
27typedef enum UVDFirmwareCommand {
28 UVDFC_FENCE = 0x0,
29 UVDFC_TRAP = 0x1,
30 UVDFC_DECODED_ADDR = 0x2,
31 UVDFC_MBLOCK_ADDR = 0x3,
32 UVDFC_ITBUF_ADDR = 0x4,
33 UVDFC_DISPLAY_ADDR = 0x5,
34 UVDFC_EOD = 0x6,
35 UVDFC_DISPLAY_PITCH = 0x7,
36 UVDFC_DISPLAY_TILING = 0x8,
37 UVDFC_BITSTREAM_ADDR = 0x9,
38 UVDFC_BITSTREAM_SIZE = 0xa,
39} UVDFirmwareCommand;
40typedef enum SurfaceEndian {
41 ENDIAN_NONE = 0x0,
42 ENDIAN_8IN16 = 0x1,
43 ENDIAN_8IN32 = 0x2,
44 ENDIAN_8IN64 = 0x3,
45} SurfaceEndian;
46typedef enum ArrayMode {
47 ARRAY_LINEAR_GENERAL = 0x0,
48 ARRAY_LINEAR_ALIGNED = 0x1,
49 ARRAY_1D_TILED_THIN1 = 0x2,
50 ARRAY_1D_TILED_THICK = 0x3,
51 ARRAY_2D_TILED_THIN1 = 0x4,
52 ARRAY_PRT_TILED_THIN1 = 0x5,
53 ARRAY_PRT_2D_TILED_THIN1 = 0x6,
54 ARRAY_2D_TILED_THICK = 0x7,
55 ARRAY_2D_TILED_XTHICK = 0x8,
56 ARRAY_PRT_TILED_THICK = 0x9,
57 ARRAY_PRT_2D_TILED_THICK = 0xa,
58 ARRAY_PRT_3D_TILED_THIN1 = 0xb,
59 ARRAY_3D_TILED_THIN1 = 0xc,
60 ARRAY_3D_TILED_THICK = 0xd,
61 ARRAY_3D_TILED_XTHICK = 0xe,
62 ARRAY_PRT_3D_TILED_THICK = 0xf,
63} ArrayMode;
64typedef enum PipeTiling {
65 CONFIG_1_PIPE = 0x0,
66 CONFIG_2_PIPE = 0x1,
67 CONFIG_4_PIPE = 0x2,
68 CONFIG_8_PIPE = 0x3,
69} PipeTiling;
70typedef enum BankTiling {
71 CONFIG_4_BANK = 0x0,
72 CONFIG_8_BANK = 0x1,
73} BankTiling;
74typedef enum GroupInterleave {
75 CONFIG_256B_GROUP = 0x0,
76 CONFIG_512B_GROUP = 0x1,
77} GroupInterleave;
78typedef enum RowTiling {
79 CONFIG_1KB_ROW = 0x0,
80 CONFIG_2KB_ROW = 0x1,
81 CONFIG_4KB_ROW = 0x2,
82 CONFIG_8KB_ROW = 0x3,
83 CONFIG_1KB_ROW_OPT = 0x4,
84 CONFIG_2KB_ROW_OPT = 0x5,
85 CONFIG_4KB_ROW_OPT = 0x6,
86 CONFIG_8KB_ROW_OPT = 0x7,
87} RowTiling;
88typedef enum BankSwapBytes {
89 CONFIG_128B_SWAPS = 0x0,
90 CONFIG_256B_SWAPS = 0x1,
91 CONFIG_512B_SWAPS = 0x2,
92 CONFIG_1KB_SWAPS = 0x3,
93} BankSwapBytes;
94typedef enum SampleSplitBytes {
95 CONFIG_1KB_SPLIT = 0x0,
96 CONFIG_2KB_SPLIT = 0x1,
97 CONFIG_4KB_SPLIT = 0x2,
98 CONFIG_8KB_SPLIT = 0x3,
99} SampleSplitBytes;
100typedef enum NumPipes {
101 ADDR_CONFIG_1_PIPE = 0x0,
102 ADDR_CONFIG_2_PIPE = 0x1,
103 ADDR_CONFIG_4_PIPE = 0x2,
104 ADDR_CONFIG_8_PIPE = 0x3,
105} NumPipes;
106typedef enum PipeInterleaveSize {
107 ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x0,
108 ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x1,
109} PipeInterleaveSize;
110typedef enum BankInterleaveSize {
111 ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x0,
112 ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x1,
113 ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x2,
114 ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x3,
115} BankInterleaveSize;
116typedef enum NumShaderEngines {
117 ADDR_CONFIG_1_SHADER_ENGINE = 0x0,
118 ADDR_CONFIG_2_SHADER_ENGINE = 0x1,
119} NumShaderEngines;
120typedef enum ShaderEngineTileSize {
121 ADDR_CONFIG_SE_TILE_16 = 0x0,
122 ADDR_CONFIG_SE_TILE_32 = 0x1,
123} ShaderEngineTileSize;
124typedef enum NumGPUs {
125 ADDR_CONFIG_1_GPU = 0x0,
126 ADDR_CONFIG_2_GPU = 0x1,
127 ADDR_CONFIG_4_GPU = 0x2,
128} NumGPUs;
129typedef enum MultiGPUTileSize {
130 ADDR_CONFIG_GPU_TILE_16 = 0x0,
131 ADDR_CONFIG_GPU_TILE_32 = 0x1,
132 ADDR_CONFIG_GPU_TILE_64 = 0x2,
133 ADDR_CONFIG_GPU_TILE_128 = 0x3,
134} MultiGPUTileSize;
135typedef enum RowSize {
136 ADDR_CONFIG_1KB_ROW = 0x0,
137 ADDR_CONFIG_2KB_ROW = 0x1,
138 ADDR_CONFIG_4KB_ROW = 0x2,
139} RowSize;
140typedef enum NumLowerPipes {
141 ADDR_CONFIG_1_LOWER_PIPES = 0x0,
142 ADDR_CONFIG_2_LOWER_PIPES = 0x1,
143} NumLowerPipes;
144typedef enum DebugBlockId {
145 DBG_CLIENT_BLKID_RESERVED = 0x0,
146 DBG_CLIENT_BLKID_dbg = 0x1,
147 DBG_CLIENT_BLKID_scf2 = 0x2,
148 DBG_CLIENT_BLKID_mcd5 = 0x3,
149 DBG_CLIENT_BLKID_vmc = 0x4,
150 DBG_CLIENT_BLKID_sx30 = 0x5,
151 DBG_CLIENT_BLKID_mcd2 = 0x6,
152 DBG_CLIENT_BLKID_bci1 = 0x7,
153 DBG_CLIENT_BLKID_xdma_dbg_client_wrapper = 0x8,
154 DBG_CLIENT_BLKID_mcc0 = 0x9,
155 DBG_CLIENT_BLKID_uvdf_0 = 0xa,
156 DBG_CLIENT_BLKID_uvdf_1 = 0xb,
157 DBG_CLIENT_BLKID_uvdf_2 = 0xc,
158 DBG_CLIENT_BLKID_uvdi_0 = 0xd,
159 DBG_CLIENT_BLKID_bci0 = 0xe,
160 DBG_CLIENT_BLKID_vcec0_0 = 0xf,
161 DBG_CLIENT_BLKID_cb100 = 0x10,
162 DBG_CLIENT_BLKID_cb001 = 0x11,
163 DBG_CLIENT_BLKID_mcd4 = 0x12,
164 DBG_CLIENT_BLKID_tmonw00 = 0x13,
165 DBG_CLIENT_BLKID_cb101 = 0x14,
166 DBG_CLIENT_BLKID_sx10 = 0x15,
167 DBG_CLIENT_BLKID_cb301 = 0x16,
168 DBG_CLIENT_BLKID_tmonw01 = 0x17,
169 DBG_CLIENT_BLKID_vcea0_0 = 0x18,
170 DBG_CLIENT_BLKID_vcea0_1 = 0x19,
171 DBG_CLIENT_BLKID_vcea0_2 = 0x1a,
172 DBG_CLIENT_BLKID_vcea0_3 = 0x1b,
173 DBG_CLIENT_BLKID_scf1 = 0x1c,
174 DBG_CLIENT_BLKID_sx20 = 0x1d,
175 DBG_CLIENT_BLKID_spim1 = 0x1e,
176 DBG_CLIENT_BLKID_pa10 = 0x1f,
177 DBG_CLIENT_BLKID_pa00 = 0x20,
178 DBG_CLIENT_BLKID_gmcon = 0x21,
179 DBG_CLIENT_BLKID_mcb = 0x22,
180 DBG_CLIENT_BLKID_vgt0 = 0x23,
181 DBG_CLIENT_BLKID_pc0 = 0x24,
182 DBG_CLIENT_BLKID_bci2 = 0x25,
183 DBG_CLIENT_BLKID_uvdb_0 = 0x26,
184 DBG_CLIENT_BLKID_spim3 = 0x27,
185 DBG_CLIENT_BLKID_cpc_0 = 0x28,
186 DBG_CLIENT_BLKID_cpc_1 = 0x29,
187 DBG_CLIENT_BLKID_uvdm_0 = 0x2a,
188 DBG_CLIENT_BLKID_uvdm_1 = 0x2b,
189 DBG_CLIENT_BLKID_uvdm_2 = 0x2c,
190 DBG_CLIENT_BLKID_uvdm_3 = 0x2d,
191 DBG_CLIENT_BLKID_cb000 = 0x2e,
192 DBG_CLIENT_BLKID_spim0 = 0x2f,
193 DBG_CLIENT_BLKID_mcc2 = 0x30,
194 DBG_CLIENT_BLKID_ds0 = 0x31,
195 DBG_CLIENT_BLKID_srbm = 0x32,
196 DBG_CLIENT_BLKID_ih = 0x33,
197 DBG_CLIENT_BLKID_sem = 0x34,
198 DBG_CLIENT_BLKID_sdma_0 = 0x35,
199 DBG_CLIENT_BLKID_sdma_1 = 0x36,
200 DBG_CLIENT_BLKID_hdp = 0x37,
201 DBG_CLIENT_BLKID_acp_0 = 0x38,
202 DBG_CLIENT_BLKID_acp_1 = 0x39,
203 DBG_CLIENT_BLKID_cb200 = 0x3a,
204 DBG_CLIENT_BLKID_scf3 = 0x3b,
205 DBG_CLIENT_BLKID_vceb1_0 = 0x3c,
206 DBG_CLIENT_BLKID_vcea1_0 = 0x3d,
207 DBG_CLIENT_BLKID_vcea1_1 = 0x3e,
208 DBG_CLIENT_BLKID_vcea1_2 = 0x3f,
209 DBG_CLIENT_BLKID_vcea1_3 = 0x40,
210 DBG_CLIENT_BLKID_bci3 = 0x41,
211 DBG_CLIENT_BLKID_mcd0 = 0x42,
212 DBG_CLIENT_BLKID_pa11 = 0x43,
213 DBG_CLIENT_BLKID_pa01 = 0x44,
214 DBG_CLIENT_BLKID_cb201 = 0x45,
215 DBG_CLIENT_BLKID_spim2 = 0x46,
216 DBG_CLIENT_BLKID_vgt2 = 0x47,
217 DBG_CLIENT_BLKID_pc2 = 0x48,
218 DBG_CLIENT_BLKID_smu_0 = 0x49,
219 DBG_CLIENT_BLKID_smu_1 = 0x4a,
220 DBG_CLIENT_BLKID_smu_2 = 0x4b,
221 DBG_CLIENT_BLKID_cb1 = 0x4c,
222 DBG_CLIENT_BLKID_ia0 = 0x4d,
223 DBG_CLIENT_BLKID_wd = 0x4e,
224 DBG_CLIENT_BLKID_ia1 = 0x4f,
225 DBG_CLIENT_BLKID_vcec1_0 = 0x50,
226 DBG_CLIENT_BLKID_scf0 = 0x51,
227 DBG_CLIENT_BLKID_vgt1 = 0x52,
228 DBG_CLIENT_BLKID_pc1 = 0x53,
229 DBG_CLIENT_BLKID_cb0 = 0x54,
230 DBG_CLIENT_BLKID_gdc_one_0 = 0x55,
231 DBG_CLIENT_BLKID_gdc_one_1 = 0x56,
232 DBG_CLIENT_BLKID_gdc_one_2 = 0x57,
233 DBG_CLIENT_BLKID_gdc_one_3 = 0x58,
234 DBG_CLIENT_BLKID_gdc_one_4 = 0x59,
235 DBG_CLIENT_BLKID_gdc_one_5 = 0x5a,
236 DBG_CLIENT_BLKID_gdc_one_6 = 0x5b,
237 DBG_CLIENT_BLKID_gdc_one_7 = 0x5c,
238 DBG_CLIENT_BLKID_gdc_one_8 = 0x5d,
239 DBG_CLIENT_BLKID_gdc_one_9 = 0x5e,
240 DBG_CLIENT_BLKID_gdc_one_10 = 0x5f,
241 DBG_CLIENT_BLKID_gdc_one_11 = 0x60,
242 DBG_CLIENT_BLKID_gdc_one_12 = 0x61,
243 DBG_CLIENT_BLKID_gdc_one_13 = 0x62,
244 DBG_CLIENT_BLKID_gdc_one_14 = 0x63,
245 DBG_CLIENT_BLKID_gdc_one_15 = 0x64,
246 DBG_CLIENT_BLKID_gdc_one_16 = 0x65,
247 DBG_CLIENT_BLKID_gdc_one_17 = 0x66,
248 DBG_CLIENT_BLKID_gdc_one_18 = 0x67,
249 DBG_CLIENT_BLKID_gdc_one_19 = 0x68,
250 DBG_CLIENT_BLKID_gdc_one_20 = 0x69,
251 DBG_CLIENT_BLKID_gdc_one_21 = 0x6a,
252 DBG_CLIENT_BLKID_gdc_one_22 = 0x6b,
253 DBG_CLIENT_BLKID_gdc_one_23 = 0x6c,
254 DBG_CLIENT_BLKID_gdc_one_24 = 0x6d,
255 DBG_CLIENT_BLKID_gdc_one_25 = 0x6e,
256 DBG_CLIENT_BLKID_gdc_one_26 = 0x6f,
257 DBG_CLIENT_BLKID_gdc_one_27 = 0x70,
258 DBG_CLIENT_BLKID_gdc_one_28 = 0x71,
259 DBG_CLIENT_BLKID_gdc_one_29 = 0x72,
260 DBG_CLIENT_BLKID_gdc_one_30 = 0x73,
261 DBG_CLIENT_BLKID_gdc_one_31 = 0x74,
262 DBG_CLIENT_BLKID_gdc_one_32 = 0x75,
263 DBG_CLIENT_BLKID_gdc_one_33 = 0x76,
264 DBG_CLIENT_BLKID_gdc_one_34 = 0x77,
265 DBG_CLIENT_BLKID_gdc_one_35 = 0x78,
266 DBG_CLIENT_BLKID_vceb0_0 = 0x79,
267 DBG_CLIENT_BLKID_vgt3 = 0x7a,
268 DBG_CLIENT_BLKID_pc3 = 0x7b,
269 DBG_CLIENT_BLKID_mcd3 = 0x7c,
270 DBG_CLIENT_BLKID_uvdu_0 = 0x7d,
271 DBG_CLIENT_BLKID_uvdu_1 = 0x7e,
272 DBG_CLIENT_BLKID_uvdu_2 = 0x7f,
273 DBG_CLIENT_BLKID_uvdu_3 = 0x80,
274 DBG_CLIENT_BLKID_uvdu_4 = 0x81,
275 DBG_CLIENT_BLKID_uvdu_5 = 0x82,
276 DBG_CLIENT_BLKID_uvdu_6 = 0x83,
277 DBG_CLIENT_BLKID_cb300 = 0x84,
278 DBG_CLIENT_BLKID_mcd1 = 0x85,
279 DBG_CLIENT_BLKID_sx00 = 0x86,
280 DBG_CLIENT_BLKID_uvdc_0 = 0x87,
281 DBG_CLIENT_BLKID_uvdc_1 = 0x88,
282 DBG_CLIENT_BLKID_mcc3 = 0x89,
283 DBG_CLIENT_BLKID_cpg_0 = 0x8a,
284 DBG_CLIENT_BLKID_cpg_1 = 0x8b,
285 DBG_CLIENT_BLKID_gck = 0x8c,
286 DBG_CLIENT_BLKID_mcc1 = 0x8d,
287 DBG_CLIENT_BLKID_cpf_0 = 0x8e,
288 DBG_CLIENT_BLKID_cpf_1 = 0x8f,
289 DBG_CLIENT_BLKID_rlc = 0x90,
290 DBG_CLIENT_BLKID_grbm = 0x91,
291 DBG_CLIENT_BLKID_sammsp = 0x92,
292 DBG_CLIENT_BLKID_dci_pg = 0x93,
293 DBG_CLIENT_BLKID_dci_0 = 0x94,
294 DBG_CLIENT_BLKID_dccg0_0 = 0x95,
295 DBG_CLIENT_BLKID_dccg0_1 = 0x96,
296 DBG_CLIENT_BLKID_dcfe01_0 = 0x97,
297 DBG_CLIENT_BLKID_dcfe02_0 = 0x98,
298 DBG_CLIENT_BLKID_dcfe03_0 = 0x99,
299 DBG_CLIENT_BLKID_dcfe04_0 = 0x9a,
300 DBG_CLIENT_BLKID_dcfe05_0 = 0x9b,
301 DBG_CLIENT_BLKID_dcfe06_0 = 0x9c,
302 DBG_CLIENT_BLKID_RESERVED_LAST = 0x9d,
303} DebugBlockId;
304typedef enum DebugBlockId_OLD {
305 DBG_BLOCK_ID_RESERVED = 0x0,
306 DBG_BLOCK_ID_DBG = 0x1,
307 DBG_BLOCK_ID_VMC = 0x2,
308 DBG_BLOCK_ID_PDMA = 0x3,
309 DBG_BLOCK_ID_CG = 0x4,
310 DBG_BLOCK_ID_SRBM = 0x5,
311 DBG_BLOCK_ID_GRBM = 0x6,
312 DBG_BLOCK_ID_RLC = 0x7,
313 DBG_BLOCK_ID_CSC = 0x8,
314 DBG_BLOCK_ID_SEM = 0x9,
315 DBG_BLOCK_ID_IH = 0xa,
316 DBG_BLOCK_ID_SC = 0xb,
317 DBG_BLOCK_ID_SQ = 0xc,
318 DBG_BLOCK_ID_AVP = 0xd,
319 DBG_BLOCK_ID_GMCON = 0xe,
320 DBG_BLOCK_ID_SMU = 0xf,
321 DBG_BLOCK_ID_DMA0 = 0x10,
322 DBG_BLOCK_ID_DMA1 = 0x11,
323 DBG_BLOCK_ID_SPIM = 0x12,
324 DBG_BLOCK_ID_GDS = 0x13,
325 DBG_BLOCK_ID_SPIS = 0x14,
326 DBG_BLOCK_ID_UNUSED0 = 0x15,
327 DBG_BLOCK_ID_PA0 = 0x16,
328 DBG_BLOCK_ID_PA1 = 0x17,
329 DBG_BLOCK_ID_CP0 = 0x18,
330 DBG_BLOCK_ID_CP1 = 0x19,
331 DBG_BLOCK_ID_CP2 = 0x1a,
332 DBG_BLOCK_ID_UNUSED1 = 0x1b,
333 DBG_BLOCK_ID_UVDU = 0x1c,
334 DBG_BLOCK_ID_UVDM = 0x1d,
335 DBG_BLOCK_ID_VCE = 0x1e,
336 DBG_BLOCK_ID_UNUSED2 = 0x1f,
337 DBG_BLOCK_ID_VGT0 = 0x20,
338 DBG_BLOCK_ID_VGT1 = 0x21,
339 DBG_BLOCK_ID_IA = 0x22,
340 DBG_BLOCK_ID_UNUSED3 = 0x23,
341 DBG_BLOCK_ID_SCT0 = 0x24,
342 DBG_BLOCK_ID_SCT1 = 0x25,
343 DBG_BLOCK_ID_SPM0 = 0x26,
344 DBG_BLOCK_ID_SPM1 = 0x27,
345 DBG_BLOCK_ID_TCAA = 0x28,
346 DBG_BLOCK_ID_TCAB = 0x29,
347 DBG_BLOCK_ID_TCCA = 0x2a,
348 DBG_BLOCK_ID_TCCB = 0x2b,
349 DBG_BLOCK_ID_MCC0 = 0x2c,
350 DBG_BLOCK_ID_MCC1 = 0x2d,
351 DBG_BLOCK_ID_MCC2 = 0x2e,
352 DBG_BLOCK_ID_MCC3 = 0x2f,
353 DBG_BLOCK_ID_SX0 = 0x30,
354 DBG_BLOCK_ID_SX1 = 0x31,
355 DBG_BLOCK_ID_SX2 = 0x32,
356 DBG_BLOCK_ID_SX3 = 0x33,
357 DBG_BLOCK_ID_UNUSED4 = 0x34,
358 DBG_BLOCK_ID_UNUSED5 = 0x35,
359 DBG_BLOCK_ID_UNUSED6 = 0x36,
360 DBG_BLOCK_ID_UNUSED7 = 0x37,
361 DBG_BLOCK_ID_PC0 = 0x38,
362 DBG_BLOCK_ID_PC1 = 0x39,
363 DBG_BLOCK_ID_UNUSED8 = 0x3a,
364 DBG_BLOCK_ID_UNUSED9 = 0x3b,
365 DBG_BLOCK_ID_UNUSED10 = 0x3c,
366 DBG_BLOCK_ID_UNUSED11 = 0x3d,
367 DBG_BLOCK_ID_MCB = 0x3e,
368 DBG_BLOCK_ID_UNUSED12 = 0x3f,
369 DBG_BLOCK_ID_SCB0 = 0x40,
370 DBG_BLOCK_ID_SCB1 = 0x41,
371 DBG_BLOCK_ID_UNUSED13 = 0x42,
372 DBG_BLOCK_ID_UNUSED14 = 0x43,
373 DBG_BLOCK_ID_SCF0 = 0x44,
374 DBG_BLOCK_ID_SCF1 = 0x45,
375 DBG_BLOCK_ID_UNUSED15 = 0x46,
376 DBG_BLOCK_ID_UNUSED16 = 0x47,
377 DBG_BLOCK_ID_BCI0 = 0x48,
378 DBG_BLOCK_ID_BCI1 = 0x49,
379 DBG_BLOCK_ID_BCI2 = 0x4a,
380 DBG_BLOCK_ID_BCI3 = 0x4b,
381 DBG_BLOCK_ID_UNUSED17 = 0x4c,
382 DBG_BLOCK_ID_UNUSED18 = 0x4d,
383 DBG_BLOCK_ID_UNUSED19 = 0x4e,
384 DBG_BLOCK_ID_UNUSED20 = 0x4f,
385 DBG_BLOCK_ID_CB00 = 0x50,
386 DBG_BLOCK_ID_CB01 = 0x51,
387 DBG_BLOCK_ID_CB02 = 0x52,
388 DBG_BLOCK_ID_CB03 = 0x53,
389 DBG_BLOCK_ID_CB04 = 0x54,
390 DBG_BLOCK_ID_UNUSED21 = 0x55,
391 DBG_BLOCK_ID_UNUSED22 = 0x56,
392 DBG_BLOCK_ID_UNUSED23 = 0x57,
393 DBG_BLOCK_ID_CB10 = 0x58,
394 DBG_BLOCK_ID_CB11 = 0x59,
395 DBG_BLOCK_ID_CB12 = 0x5a,
396 DBG_BLOCK_ID_CB13 = 0x5b,
397 DBG_BLOCK_ID_CB14 = 0x5c,
398 DBG_BLOCK_ID_UNUSED24 = 0x5d,
399 DBG_BLOCK_ID_UNUSED25 = 0x5e,
400 DBG_BLOCK_ID_UNUSED26 = 0x5f,
401 DBG_BLOCK_ID_TCP0 = 0x60,
402 DBG_BLOCK_ID_TCP1 = 0x61,
403 DBG_BLOCK_ID_TCP2 = 0x62,
404 DBG_BLOCK_ID_TCP3 = 0x63,
405 DBG_BLOCK_ID_TCP4 = 0x64,
406 DBG_BLOCK_ID_TCP5 = 0x65,
407 DBG_BLOCK_ID_TCP6 = 0x66,
408 DBG_BLOCK_ID_TCP7 = 0x67,
409 DBG_BLOCK_ID_TCP8 = 0x68,
410 DBG_BLOCK_ID_TCP9 = 0x69,
411 DBG_BLOCK_ID_TCP10 = 0x6a,
412 DBG_BLOCK_ID_TCP11 = 0x6b,
413 DBG_BLOCK_ID_TCP12 = 0x6c,
414 DBG_BLOCK_ID_TCP13 = 0x6d,
415 DBG_BLOCK_ID_TCP14 = 0x6e,
416 DBG_BLOCK_ID_TCP15 = 0x6f,
417 DBG_BLOCK_ID_TCP16 = 0x70,
418 DBG_BLOCK_ID_TCP17 = 0x71,
419 DBG_BLOCK_ID_TCP18 = 0x72,
420 DBG_BLOCK_ID_TCP19 = 0x73,
421 DBG_BLOCK_ID_TCP20 = 0x74,
422 DBG_BLOCK_ID_TCP21 = 0x75,
423 DBG_BLOCK_ID_TCP22 = 0x76,
424 DBG_BLOCK_ID_TCP23 = 0x77,
425 DBG_BLOCK_ID_TCP_RESERVED0 = 0x78,
426 DBG_BLOCK_ID_TCP_RESERVED1 = 0x79,
427 DBG_BLOCK_ID_TCP_RESERVED2 = 0x7a,
428 DBG_BLOCK_ID_TCP_RESERVED3 = 0x7b,
429 DBG_BLOCK_ID_TCP_RESERVED4 = 0x7c,
430 DBG_BLOCK_ID_TCP_RESERVED5 = 0x7d,
431 DBG_BLOCK_ID_TCP_RESERVED6 = 0x7e,
432 DBG_BLOCK_ID_TCP_RESERVED7 = 0x7f,
433 DBG_BLOCK_ID_DB00 = 0x80,
434 DBG_BLOCK_ID_DB01 = 0x81,
435 DBG_BLOCK_ID_DB02 = 0x82,
436 DBG_BLOCK_ID_DB03 = 0x83,
437 DBG_BLOCK_ID_DB04 = 0x84,
438 DBG_BLOCK_ID_UNUSED27 = 0x85,
439 DBG_BLOCK_ID_UNUSED28 = 0x86,
440 DBG_BLOCK_ID_UNUSED29 = 0x87,
441 DBG_BLOCK_ID_DB10 = 0x88,
442 DBG_BLOCK_ID_DB11 = 0x89,
443 DBG_BLOCK_ID_DB12 = 0x8a,
444 DBG_BLOCK_ID_DB13 = 0x8b,
445 DBG_BLOCK_ID_DB14 = 0x8c,
446 DBG_BLOCK_ID_UNUSED30 = 0x8d,
447 DBG_BLOCK_ID_UNUSED31 = 0x8e,
448 DBG_BLOCK_ID_UNUSED32 = 0x8f,
449 DBG_BLOCK_ID_TCC0 = 0x90,
450 DBG_BLOCK_ID_TCC1 = 0x91,
451 DBG_BLOCK_ID_TCC2 = 0x92,
452 DBG_BLOCK_ID_TCC3 = 0x93,
453 DBG_BLOCK_ID_TCC4 = 0x94,
454 DBG_BLOCK_ID_TCC5 = 0x95,
455 DBG_BLOCK_ID_TCC6 = 0x96,
456 DBG_BLOCK_ID_TCC7 = 0x97,
457 DBG_BLOCK_ID_SPS00 = 0x98,
458 DBG_BLOCK_ID_SPS01 = 0x99,
459 DBG_BLOCK_ID_SPS02 = 0x9a,
460 DBG_BLOCK_ID_SPS10 = 0x9b,
461 DBG_BLOCK_ID_SPS11 = 0x9c,
462 DBG_BLOCK_ID_SPS12 = 0x9d,
463 DBG_BLOCK_ID_UNUSED33 = 0x9e,
464 DBG_BLOCK_ID_UNUSED34 = 0x9f,
465 DBG_BLOCK_ID_TA00 = 0xa0,
466 DBG_BLOCK_ID_TA01 = 0xa1,
467 DBG_BLOCK_ID_TA02 = 0xa2,
468 DBG_BLOCK_ID_TA03 = 0xa3,
469 DBG_BLOCK_ID_TA04 = 0xa4,
470 DBG_BLOCK_ID_TA05 = 0xa5,
471 DBG_BLOCK_ID_TA06 = 0xa6,
472 DBG_BLOCK_ID_TA07 = 0xa7,
473 DBG_BLOCK_ID_TA08 = 0xa8,
474 DBG_BLOCK_ID_TA09 = 0xa9,
475 DBG_BLOCK_ID_TA0A = 0xaa,
476 DBG_BLOCK_ID_TA0B = 0xab,
477 DBG_BLOCK_ID_UNUSED35 = 0xac,
478 DBG_BLOCK_ID_UNUSED36 = 0xad,
479 DBG_BLOCK_ID_UNUSED37 = 0xae,
480 DBG_BLOCK_ID_UNUSED38 = 0xaf,
481 DBG_BLOCK_ID_TA10 = 0xb0,
482 DBG_BLOCK_ID_TA11 = 0xb1,
483 DBG_BLOCK_ID_TA12 = 0xb2,
484 DBG_BLOCK_ID_TA13 = 0xb3,
485 DBG_BLOCK_ID_TA14 = 0xb4,
486 DBG_BLOCK_ID_TA15 = 0xb5,
487 DBG_BLOCK_ID_TA16 = 0xb6,
488 DBG_BLOCK_ID_TA17 = 0xb7,
489 DBG_BLOCK_ID_TA18 = 0xb8,
490 DBG_BLOCK_ID_TA19 = 0xb9,
491 DBG_BLOCK_ID_TA1A = 0xba,
492 DBG_BLOCK_ID_TA1B = 0xbb,
493 DBG_BLOCK_ID_UNUSED39 = 0xbc,
494 DBG_BLOCK_ID_UNUSED40 = 0xbd,
495 DBG_BLOCK_ID_UNUSED41 = 0xbe,
496 DBG_BLOCK_ID_UNUSED42 = 0xbf,
497 DBG_BLOCK_ID_TD00 = 0xc0,
498 DBG_BLOCK_ID_TD01 = 0xc1,
499 DBG_BLOCK_ID_TD02 = 0xc2,
500 DBG_BLOCK_ID_TD03 = 0xc3,
501 DBG_BLOCK_ID_TD04 = 0xc4,
502 DBG_BLOCK_ID_TD05 = 0xc5,
503 DBG_BLOCK_ID_TD06 = 0xc6,
504 DBG_BLOCK_ID_TD07 = 0xc7,
505 DBG_BLOCK_ID_TD08 = 0xc8,
506 DBG_BLOCK_ID_TD09 = 0xc9,
507 DBG_BLOCK_ID_TD0A = 0xca,
508 DBG_BLOCK_ID_TD0B = 0xcb,
509 DBG_BLOCK_ID_UNUSED43 = 0xcc,
510 DBG_BLOCK_ID_UNUSED44 = 0xcd,
511 DBG_BLOCK_ID_UNUSED45 = 0xce,
512 DBG_BLOCK_ID_UNUSED46 = 0xcf,
513 DBG_BLOCK_ID_TD10 = 0xd0,
514 DBG_BLOCK_ID_TD11 = 0xd1,
515 DBG_BLOCK_ID_TD12 = 0xd2,
516 DBG_BLOCK_ID_TD13 = 0xd3,
517 DBG_BLOCK_ID_TD14 = 0xd4,
518 DBG_BLOCK_ID_TD15 = 0xd5,
519 DBG_BLOCK_ID_TD16 = 0xd6,
520 DBG_BLOCK_ID_TD17 = 0xd7,
521 DBG_BLOCK_ID_TD18 = 0xd8,
522 DBG_BLOCK_ID_TD19 = 0xd9,
523 DBG_BLOCK_ID_TD1A = 0xda,
524 DBG_BLOCK_ID_TD1B = 0xdb,
525 DBG_BLOCK_ID_UNUSED47 = 0xdc,
526 DBG_BLOCK_ID_UNUSED48 = 0xdd,
527 DBG_BLOCK_ID_UNUSED49 = 0xde,
528 DBG_BLOCK_ID_UNUSED50 = 0xdf,
529 DBG_BLOCK_ID_MCD0 = 0xe0,
530 DBG_BLOCK_ID_MCD1 = 0xe1,
531 DBG_BLOCK_ID_MCD2 = 0xe2,
532 DBG_BLOCK_ID_MCD3 = 0xe3,
533 DBG_BLOCK_ID_MCD4 = 0xe4,
534 DBG_BLOCK_ID_MCD5 = 0xe5,
535 DBG_BLOCK_ID_UNUSED51 = 0xe6,
536 DBG_BLOCK_ID_UNUSED52 = 0xe7,
537} DebugBlockId_OLD;
538typedef enum DebugBlockId_BY2 {
539 DBG_BLOCK_ID_RESERVED_BY2 = 0x0,
540 DBG_BLOCK_ID_VMC_BY2 = 0x1,
541 DBG_BLOCK_ID_CG_BY2 = 0x2,
542 DBG_BLOCK_ID_GRBM_BY2 = 0x3,
543 DBG_BLOCK_ID_CSC_BY2 = 0x4,
544 DBG_BLOCK_ID_IH_BY2 = 0x5,
545 DBG_BLOCK_ID_SQ_BY2 = 0x6,
546 DBG_BLOCK_ID_GMCON_BY2 = 0x7,
547 DBG_BLOCK_ID_DMA0_BY2 = 0x8,
548 DBG_BLOCK_ID_SPIM_BY2 = 0x9,
549 DBG_BLOCK_ID_SPIS_BY2 = 0xa,
550 DBG_BLOCK_ID_PA0_BY2 = 0xb,
551 DBG_BLOCK_ID_CP0_BY2 = 0xc,
552 DBG_BLOCK_ID_CP2_BY2 = 0xd,
553 DBG_BLOCK_ID_UVDU_BY2 = 0xe,
554 DBG_BLOCK_ID_VCE_BY2 = 0xf,
555 DBG_BLOCK_ID_VGT0_BY2 = 0x10,
556 DBG_BLOCK_ID_IA_BY2 = 0x11,
557 DBG_BLOCK_ID_SCT0_BY2 = 0x12,
558 DBG_BLOCK_ID_SPM0_BY2 = 0x13,
559 DBG_BLOCK_ID_TCAA_BY2 = 0x14,
560 DBG_BLOCK_ID_TCCA_BY2 = 0x15,
561 DBG_BLOCK_ID_MCC0_BY2 = 0x16,
562 DBG_BLOCK_ID_MCC2_BY2 = 0x17,
563 DBG_BLOCK_ID_SX0_BY2 = 0x18,
564 DBG_BLOCK_ID_SX2_BY2 = 0x19,
565 DBG_BLOCK_ID_UNUSED4_BY2 = 0x1a,
566 DBG_BLOCK_ID_UNUSED6_BY2 = 0x1b,
567 DBG_BLOCK_ID_PC0_BY2 = 0x1c,
568 DBG_BLOCK_ID_UNUSED8_BY2 = 0x1d,
569 DBG_BLOCK_ID_UNUSED10_BY2 = 0x1e,
570 DBG_BLOCK_ID_MCB_BY2 = 0x1f,
571 DBG_BLOCK_ID_SCB0_BY2 = 0x20,
572 DBG_BLOCK_ID_UNUSED13_BY2 = 0x21,
573 DBG_BLOCK_ID_SCF0_BY2 = 0x22,
574 DBG_BLOCK_ID_UNUSED15_BY2 = 0x23,
575 DBG_BLOCK_ID_BCI0_BY2 = 0x24,
576 DBG_BLOCK_ID_BCI2_BY2 = 0x25,
577 DBG_BLOCK_ID_UNUSED17_BY2 = 0x26,
578 DBG_BLOCK_ID_UNUSED19_BY2 = 0x27,
579 DBG_BLOCK_ID_CB00_BY2 = 0x28,
580 DBG_BLOCK_ID_CB02_BY2 = 0x29,
581 DBG_BLOCK_ID_CB04_BY2 = 0x2a,
582 DBG_BLOCK_ID_UNUSED22_BY2 = 0x2b,
583 DBG_BLOCK_ID_CB10_BY2 = 0x2c,
584 DBG_BLOCK_ID_CB12_BY2 = 0x2d,
585 DBG_BLOCK_ID_CB14_BY2 = 0x2e,
586 DBG_BLOCK_ID_UNUSED25_BY2 = 0x2f,
587 DBG_BLOCK_ID_TCP0_BY2 = 0x30,
588 DBG_BLOCK_ID_TCP2_BY2 = 0x31,
589 DBG_BLOCK_ID_TCP4_BY2 = 0x32,
590 DBG_BLOCK_ID_TCP6_BY2 = 0x33,
591 DBG_BLOCK_ID_TCP8_BY2 = 0x34,
592 DBG_BLOCK_ID_TCP10_BY2 = 0x35,
593 DBG_BLOCK_ID_TCP12_BY2 = 0x36,
594 DBG_BLOCK_ID_TCP14_BY2 = 0x37,
595 DBG_BLOCK_ID_TCP16_BY2 = 0x38,
596 DBG_BLOCK_ID_TCP18_BY2 = 0x39,
597 DBG_BLOCK_ID_TCP20_BY2 = 0x3a,
598 DBG_BLOCK_ID_TCP22_BY2 = 0x3b,
599 DBG_BLOCK_ID_TCP_RESERVED0_BY2 = 0x3c,
600 DBG_BLOCK_ID_TCP_RESERVED2_BY2 = 0x3d,
601 DBG_BLOCK_ID_TCP_RESERVED4_BY2 = 0x3e,
602 DBG_BLOCK_ID_TCP_RESERVED6_BY2 = 0x3f,
603 DBG_BLOCK_ID_DB00_BY2 = 0x40,
604 DBG_BLOCK_ID_DB02_BY2 = 0x41,
605 DBG_BLOCK_ID_DB04_BY2 = 0x42,
606 DBG_BLOCK_ID_UNUSED28_BY2 = 0x43,
607 DBG_BLOCK_ID_DB10_BY2 = 0x44,
608 DBG_BLOCK_ID_DB12_BY2 = 0x45,
609 DBG_BLOCK_ID_DB14_BY2 = 0x46,
610 DBG_BLOCK_ID_UNUSED31_BY2 = 0x47,
611 DBG_BLOCK_ID_TCC0_BY2 = 0x48,
612 DBG_BLOCK_ID_TCC2_BY2 = 0x49,
613 DBG_BLOCK_ID_TCC4_BY2 = 0x4a,
614 DBG_BLOCK_ID_TCC6_BY2 = 0x4b,
615 DBG_BLOCK_ID_SPS00_BY2 = 0x4c,
616 DBG_BLOCK_ID_SPS02_BY2 = 0x4d,
617 DBG_BLOCK_ID_SPS11_BY2 = 0x4e,
618 DBG_BLOCK_ID_UNUSED33_BY2 = 0x4f,
619 DBG_BLOCK_ID_TA00_BY2 = 0x50,
620 DBG_BLOCK_ID_TA02_BY2 = 0x51,
621 DBG_BLOCK_ID_TA04_BY2 = 0x52,
622 DBG_BLOCK_ID_TA06_BY2 = 0x53,
623 DBG_BLOCK_ID_TA08_BY2 = 0x54,
624 DBG_BLOCK_ID_TA0A_BY2 = 0x55,
625 DBG_BLOCK_ID_UNUSED35_BY2 = 0x56,
626 DBG_BLOCK_ID_UNUSED37_BY2 = 0x57,
627 DBG_BLOCK_ID_TA10_BY2 = 0x58,
628 DBG_BLOCK_ID_TA12_BY2 = 0x59,
629 DBG_BLOCK_ID_TA14_BY2 = 0x5a,
630 DBG_BLOCK_ID_TA16_BY2 = 0x5b,
631 DBG_BLOCK_ID_TA18_BY2 = 0x5c,
632 DBG_BLOCK_ID_TA1A_BY2 = 0x5d,
633 DBG_BLOCK_ID_UNUSED39_BY2 = 0x5e,
634 DBG_BLOCK_ID_UNUSED41_BY2 = 0x5f,
635 DBG_BLOCK_ID_TD00_BY2 = 0x60,
636 DBG_BLOCK_ID_TD02_BY2 = 0x61,
637 DBG_BLOCK_ID_TD04_BY2 = 0x62,
638 DBG_BLOCK_ID_TD06_BY2 = 0x63,
639 DBG_BLOCK_ID_TD08_BY2 = 0x64,
640 DBG_BLOCK_ID_TD0A_BY2 = 0x65,
641 DBG_BLOCK_ID_UNUSED43_BY2 = 0x66,
642 DBG_BLOCK_ID_UNUSED45_BY2 = 0x67,
643 DBG_BLOCK_ID_TD10_BY2 = 0x68,
644 DBG_BLOCK_ID_TD12_BY2 = 0x69,
645 DBG_BLOCK_ID_TD14_BY2 = 0x6a,
646 DBG_BLOCK_ID_TD16_BY2 = 0x6b,
647 DBG_BLOCK_ID_TD18_BY2 = 0x6c,
648 DBG_BLOCK_ID_TD1A_BY2 = 0x6d,
649 DBG_BLOCK_ID_UNUSED47_BY2 = 0x6e,
650 DBG_BLOCK_ID_UNUSED49_BY2 = 0x6f,
651 DBG_BLOCK_ID_MCD0_BY2 = 0x70,
652 DBG_BLOCK_ID_MCD2_BY2 = 0x71,
653 DBG_BLOCK_ID_MCD4_BY2 = 0x72,
654 DBG_BLOCK_ID_UNUSED51_BY2 = 0x73,
655} DebugBlockId_BY2;
656typedef enum DebugBlockId_BY4 {
657 DBG_BLOCK_ID_RESERVED_BY4 = 0x0,
658 DBG_BLOCK_ID_CG_BY4 = 0x1,
659 DBG_BLOCK_ID_CSC_BY4 = 0x2,
660 DBG_BLOCK_ID_SQ_BY4 = 0x3,
661 DBG_BLOCK_ID_DMA0_BY4 = 0x4,
662 DBG_BLOCK_ID_SPIS_BY4 = 0x5,
663 DBG_BLOCK_ID_CP0_BY4 = 0x6,
664 DBG_BLOCK_ID_UVDU_BY4 = 0x7,
665 DBG_BLOCK_ID_VGT0_BY4 = 0x8,
666 DBG_BLOCK_ID_SCT0_BY4 = 0x9,
667 DBG_BLOCK_ID_TCAA_BY4 = 0xa,
668 DBG_BLOCK_ID_MCC0_BY4 = 0xb,
669 DBG_BLOCK_ID_SX0_BY4 = 0xc,
670 DBG_BLOCK_ID_UNUSED4_BY4 = 0xd,
671 DBG_BLOCK_ID_PC0_BY4 = 0xe,
672 DBG_BLOCK_ID_UNUSED10_BY4 = 0xf,
673 DBG_BLOCK_ID_SCB0_BY4 = 0x10,
674 DBG_BLOCK_ID_SCF0_BY4 = 0x11,
675 DBG_BLOCK_ID_BCI0_BY4 = 0x12,
676 DBG_BLOCK_ID_UNUSED17_BY4 = 0x13,
677 DBG_BLOCK_ID_CB00_BY4 = 0x14,
678 DBG_BLOCK_ID_CB04_BY4 = 0x15,
679 DBG_BLOCK_ID_CB10_BY4 = 0x16,
680 DBG_BLOCK_ID_CB14_BY4 = 0x17,
681 DBG_BLOCK_ID_TCP0_BY4 = 0x18,
682 DBG_BLOCK_ID_TCP4_BY4 = 0x19,
683 DBG_BLOCK_ID_TCP8_BY4 = 0x1a,
684 DBG_BLOCK_ID_TCP12_BY4 = 0x1b,
685 DBG_BLOCK_ID_TCP16_BY4 = 0x1c,
686 DBG_BLOCK_ID_TCP20_BY4 = 0x1d,
687 DBG_BLOCK_ID_TCP_RESERVED0_BY4 = 0x1e,
688 DBG_BLOCK_ID_TCP_RESERVED4_BY4 = 0x1f,
689 DBG_BLOCK_ID_DB_BY4 = 0x20,
690 DBG_BLOCK_ID_DB04_BY4 = 0x21,
691 DBG_BLOCK_ID_DB10_BY4 = 0x22,
692 DBG_BLOCK_ID_DB14_BY4 = 0x23,
693 DBG_BLOCK_ID_TCC0_BY4 = 0x24,
694 DBG_BLOCK_ID_TCC4_BY4 = 0x25,
695 DBG_BLOCK_ID_SPS00_BY4 = 0x26,
696 DBG_BLOCK_ID_SPS11_BY4 = 0x27,
697 DBG_BLOCK_ID_TA00_BY4 = 0x28,
698 DBG_BLOCK_ID_TA04_BY4 = 0x29,
699 DBG_BLOCK_ID_TA08_BY4 = 0x2a,
700 DBG_BLOCK_ID_UNUSED35_BY4 = 0x2b,
701 DBG_BLOCK_ID_TA10_BY4 = 0x2c,
702 DBG_BLOCK_ID_TA14_BY4 = 0x2d,
703 DBG_BLOCK_ID_TA18_BY4 = 0x2e,
704 DBG_BLOCK_ID_UNUSED39_BY4 = 0x2f,
705 DBG_BLOCK_ID_TD00_BY4 = 0x30,
706 DBG_BLOCK_ID_TD04_BY4 = 0x31,
707 DBG_BLOCK_ID_TD08_BY4 = 0x32,
708 DBG_BLOCK_ID_UNUSED43_BY4 = 0x33,
709 DBG_BLOCK_ID_TD10_BY4 = 0x34,
710 DBG_BLOCK_ID_TD14_BY4 = 0x35,
711 DBG_BLOCK_ID_TD18_BY4 = 0x36,
712 DBG_BLOCK_ID_UNUSED47_BY4 = 0x37,
713 DBG_BLOCK_ID_MCD0_BY4 = 0x38,
714 DBG_BLOCK_ID_MCD4_BY4 = 0x39,
715} DebugBlockId_BY4;
716typedef enum DebugBlockId_BY8 {
717 DBG_BLOCK_ID_RESERVED_BY8 = 0x0,
718 DBG_BLOCK_ID_CSC_BY8 = 0x1,
719 DBG_BLOCK_ID_DMA0_BY8 = 0x2,
720 DBG_BLOCK_ID_CP0_BY8 = 0x3,
721 DBG_BLOCK_ID_VGT0_BY8 = 0x4,
722 DBG_BLOCK_ID_TCAA_BY8 = 0x5,
723 DBG_BLOCK_ID_SX0_BY8 = 0x6,
724 DBG_BLOCK_ID_PC0_BY8 = 0x7,
725 DBG_BLOCK_ID_SCB0_BY8 = 0x8,
726 DBG_BLOCK_ID_BCI0_BY8 = 0x9,
727 DBG_BLOCK_ID_CB00_BY8 = 0xa,
728 DBG_BLOCK_ID_CB10_BY8 = 0xb,
729 DBG_BLOCK_ID_TCP0_BY8 = 0xc,
730 DBG_BLOCK_ID_TCP8_BY8 = 0xd,
731 DBG_BLOCK_ID_TCP16_BY8 = 0xe,
732 DBG_BLOCK_ID_TCP_RESERVED0_BY8 = 0xf,
733 DBG_BLOCK_ID_DB00_BY8 = 0x10,
734 DBG_BLOCK_ID_DB10_BY8 = 0x11,
735 DBG_BLOCK_ID_TCC0_BY8 = 0x12,
736 DBG_BLOCK_ID_SPS00_BY8 = 0x13,
737 DBG_BLOCK_ID_TA00_BY8 = 0x14,
738 DBG_BLOCK_ID_TA08_BY8 = 0x15,
739 DBG_BLOCK_ID_TA10_BY8 = 0x16,
740 DBG_BLOCK_ID_TA18_BY8 = 0x17,
741 DBG_BLOCK_ID_TD00_BY8 = 0x18,
742 DBG_BLOCK_ID_TD08_BY8 = 0x19,
743 DBG_BLOCK_ID_TD10_BY8 = 0x1a,
744 DBG_BLOCK_ID_TD18_BY8 = 0x1b,
745 DBG_BLOCK_ID_MCD0_BY8 = 0x1c,
746} DebugBlockId_BY8;
747typedef enum DebugBlockId_BY16 {
748 DBG_BLOCK_ID_RESERVED_BY16 = 0x0,
749 DBG_BLOCK_ID_DMA0_BY16 = 0x1,
750 DBG_BLOCK_ID_VGT0_BY16 = 0x2,
751 DBG_BLOCK_ID_SX0_BY16 = 0x3,
752 DBG_BLOCK_ID_SCB0_BY16 = 0x4,
753 DBG_BLOCK_ID_CB00_BY16 = 0x5,
754 DBG_BLOCK_ID_TCP0_BY16 = 0x6,
755 DBG_BLOCK_ID_TCP16_BY16 = 0x7,
756 DBG_BLOCK_ID_DB00_BY16 = 0x8,
757 DBG_BLOCK_ID_TCC0_BY16 = 0x9,
758 DBG_BLOCK_ID_TA00_BY16 = 0xa,
759 DBG_BLOCK_ID_TA10_BY16 = 0xb,
760 DBG_BLOCK_ID_TD00_BY16 = 0xc,
761 DBG_BLOCK_ID_TD10_BY16 = 0xd,
762 DBG_BLOCK_ID_MCD0_BY16 = 0xe,
763} DebugBlockId_BY16;
764typedef enum ColorTransform {
765 DCC_CT_AUTO = 0x0,
766 DCC_CT_NONE = 0x1,
767 ABGR_TO_A_BG_G_RB = 0x2,
768 BGRA_TO_BG_G_RB_A = 0x3,
769} ColorTransform;
770typedef enum CompareRef {
771 REF_NEVER = 0x0,
772 REF_LESS = 0x1,
773 REF_EQUAL = 0x2,
774 REF_LEQUAL = 0x3,
775 REF_GREATER = 0x4,
776 REF_NOTEQUAL = 0x5,
777 REF_GEQUAL = 0x6,
778 REF_ALWAYS = 0x7,
779} CompareRef;
780typedef enum ReadSize {
781 READ_256_BITS = 0x0,
782 READ_512_BITS = 0x1,
783} ReadSize;
784typedef enum DepthFormat {
785 DEPTH_INVALID = 0x0,
786 DEPTH_16 = 0x1,
787 DEPTH_X8_24 = 0x2,
788 DEPTH_8_24 = 0x3,
789 DEPTH_X8_24_FLOAT = 0x4,
790 DEPTH_8_24_FLOAT = 0x5,
791 DEPTH_32_FLOAT = 0x6,
792 DEPTH_X24_8_32_FLOAT = 0x7,
793} DepthFormat;
794typedef enum ZFormat {
795 Z_INVALID = 0x0,
796 Z_16 = 0x1,
797 Z_24 = 0x2,
798 Z_32_FLOAT = 0x3,
799} ZFormat;
800typedef enum StencilFormat {
801 STENCIL_INVALID = 0x0,
802 STENCIL_8 = 0x1,
803} StencilFormat;
804typedef enum CmaskMode {
805 CMASK_CLEAR_NONE = 0x0,
806 CMASK_CLEAR_ONE = 0x1,
807 CMASK_CLEAR_ALL = 0x2,
808 CMASK_ANY_EXPANDED = 0x3,
809 CMASK_ALPHA0_FRAG1 = 0x4,
810 CMASK_ALPHA0_FRAG2 = 0x5,
811 CMASK_ALPHA0_FRAG4 = 0x6,
812 CMASK_ALPHA0_FRAGS = 0x7,
813 CMASK_ALPHA1_FRAG1 = 0x8,
814 CMASK_ALPHA1_FRAG2 = 0x9,
815 CMASK_ALPHA1_FRAG4 = 0xa,
816 CMASK_ALPHA1_FRAGS = 0xb,
817 CMASK_ALPHAX_FRAG1 = 0xc,
818 CMASK_ALPHAX_FRAG2 = 0xd,
819 CMASK_ALPHAX_FRAG4 = 0xe,
820 CMASK_ALPHAX_FRAGS = 0xf,
821} CmaskMode;
822typedef enum QuadExportFormat {
823 EXPORT_UNUSED = 0x0,
824 EXPORT_32_R = 0x1,
825 EXPORT_32_GR = 0x2,
826 EXPORT_32_AR = 0x3,
827 EXPORT_FP16_ABGR = 0x4,
828 EXPORT_UNSIGNED16_ABGR = 0x5,
829 EXPORT_SIGNED16_ABGR = 0x6,
830 EXPORT_32_ABGR = 0x7,
831} QuadExportFormat;
832typedef enum QuadExportFormatOld {
833 EXPORT_4P_32BPC_ABGR = 0x0,
834 EXPORT_4P_16BPC_ABGR = 0x1,
835 EXPORT_4P_32BPC_GR = 0x2,
836 EXPORT_4P_32BPC_AR = 0x3,
837 EXPORT_2P_32BPC_ABGR = 0x4,
838 EXPORT_8P_32BPC_R = 0x5,
839} QuadExportFormatOld;
840typedef enum ColorFormat {
841 COLOR_INVALID = 0x0,
842 COLOR_8 = 0x1,
843 COLOR_16 = 0x2,
844 COLOR_8_8 = 0x3,
845 COLOR_32 = 0x4,
846 COLOR_16_16 = 0x5,
847 COLOR_10_11_11 = 0x6,
848 COLOR_11_11_10 = 0x7,
849 COLOR_10_10_10_2 = 0x8,
850 COLOR_2_10_10_10 = 0x9,
851 COLOR_8_8_8_8 = 0xa,
852 COLOR_32_32 = 0xb,
853 COLOR_16_16_16_16 = 0xc,
854 COLOR_RESERVED_13 = 0xd,
855 COLOR_32_32_32_32 = 0xe,
856 COLOR_RESERVED_15 = 0xf,
857 COLOR_5_6_5 = 0x10,
858 COLOR_1_5_5_5 = 0x11,
859 COLOR_5_5_5_1 = 0x12,
860 COLOR_4_4_4_4 = 0x13,
861 COLOR_8_24 = 0x14,
862 COLOR_24_8 = 0x15,
863 COLOR_X24_8_32_FLOAT = 0x16,
864 COLOR_RESERVED_23 = 0x17,
865} ColorFormat;
866typedef enum SurfaceFormat {
867 FMT_INVALID = 0x0,
868 FMT_8 = 0x1,
869 FMT_16 = 0x2,
870 FMT_8_8 = 0x3,
871 FMT_32 = 0x4,
872 FMT_16_16 = 0x5,
873 FMT_10_11_11 = 0x6,
874 FMT_11_11_10 = 0x7,
875 FMT_10_10_10_2 = 0x8,
876 FMT_2_10_10_10 = 0x9,
877 FMT_8_8_8_8 = 0xa,
878 FMT_32_32 = 0xb,
879 FMT_16_16_16_16 = 0xc,
880 FMT_32_32_32 = 0xd,
881 FMT_32_32_32_32 = 0xe,
882 FMT_RESERVED_4 = 0xf,
883 FMT_5_6_5 = 0x10,
884 FMT_1_5_5_5 = 0x11,
885 FMT_5_5_5_1 = 0x12,
886 FMT_4_4_4_4 = 0x13,
887 FMT_8_24 = 0x14,
888 FMT_24_8 = 0x15,
889 FMT_X24_8_32_FLOAT = 0x16,
890 FMT_RESERVED_33 = 0x17,
891 FMT_11_11_10_FLOAT = 0x18,
892 FMT_16_FLOAT = 0x19,
893 FMT_32_FLOAT = 0x1a,
894 FMT_16_16_FLOAT = 0x1b,
895 FMT_8_24_FLOAT = 0x1c,
896 FMT_24_8_FLOAT = 0x1d,
897 FMT_32_32_FLOAT = 0x1e,
898 FMT_10_11_11_FLOAT = 0x1f,
899 FMT_16_16_16_16_FLOAT = 0x20,
900 FMT_3_3_2 = 0x21,
901 FMT_6_5_5 = 0x22,
902 FMT_32_32_32_32_FLOAT = 0x23,
903 FMT_RESERVED_36 = 0x24,
904 FMT_1 = 0x25,
905 FMT_1_REVERSED = 0x26,
906 FMT_GB_GR = 0x27,
907 FMT_BG_RG = 0x28,
908 FMT_32_AS_8 = 0x29,
909 FMT_32_AS_8_8 = 0x2a,
910 FMT_5_9_9_9_SHAREDEXP = 0x2b,
911 FMT_8_8_8 = 0x2c,
912 FMT_16_16_16 = 0x2d,
913 FMT_16_16_16_FLOAT = 0x2e,
914 FMT_4_4 = 0x2f,
915 FMT_32_32_32_FLOAT = 0x30,
916 FMT_BC1 = 0x31,
917 FMT_BC2 = 0x32,
918 FMT_BC3 = 0x33,
919 FMT_BC4 = 0x34,
920 FMT_BC5 = 0x35,
921 FMT_BC6 = 0x36,
922 FMT_BC7 = 0x37,
923 FMT_32_AS_32_32_32_32 = 0x38,
924 FMT_APC3 = 0x39,
925 FMT_APC4 = 0x3a,
926 FMT_APC5 = 0x3b,
927 FMT_APC6 = 0x3c,
928 FMT_APC7 = 0x3d,
929 FMT_CTX1 = 0x3e,
930 FMT_RESERVED_63 = 0x3f,
931} SurfaceFormat;
932typedef enum BUF_DATA_FORMAT {
933 BUF_DATA_FORMAT_INVALID = 0x0,
934 BUF_DATA_FORMAT_8 = 0x1,
935 BUF_DATA_FORMAT_16 = 0x2,
936 BUF_DATA_FORMAT_8_8 = 0x3,
937 BUF_DATA_FORMAT_32 = 0x4,
938 BUF_DATA_FORMAT_16_16 = 0x5,
939 BUF_DATA_FORMAT_10_11_11 = 0x6,
940 BUF_DATA_FORMAT_11_11_10 = 0x7,
941 BUF_DATA_FORMAT_10_10_10_2 = 0x8,
942 BUF_DATA_FORMAT_2_10_10_10 = 0x9,
943 BUF_DATA_FORMAT_8_8_8_8 = 0xa,
944 BUF_DATA_FORMAT_32_32 = 0xb,
945 BUF_DATA_FORMAT_16_16_16_16 = 0xc,
946 BUF_DATA_FORMAT_32_32_32 = 0xd,
947 BUF_DATA_FORMAT_32_32_32_32 = 0xe,
948 BUF_DATA_FORMAT_RESERVED_15 = 0xf,
949} BUF_DATA_FORMAT;
950typedef enum IMG_DATA_FORMAT {
951 IMG_DATA_FORMAT_INVALID = 0x0,
952 IMG_DATA_FORMAT_8 = 0x1,
953 IMG_DATA_FORMAT_16 = 0x2,
954 IMG_DATA_FORMAT_8_8 = 0x3,
955 IMG_DATA_FORMAT_32 = 0x4,
956 IMG_DATA_FORMAT_16_16 = 0x5,
957 IMG_DATA_FORMAT_10_11_11 = 0x6,
958 IMG_DATA_FORMAT_11_11_10 = 0x7,
959 IMG_DATA_FORMAT_10_10_10_2 = 0x8,
960 IMG_DATA_FORMAT_2_10_10_10 = 0x9,
961 IMG_DATA_FORMAT_8_8_8_8 = 0xa,
962 IMG_DATA_FORMAT_32_32 = 0xb,
963 IMG_DATA_FORMAT_16_16_16_16 = 0xc,
964 IMG_DATA_FORMAT_32_32_32 = 0xd,
965 IMG_DATA_FORMAT_32_32_32_32 = 0xe,
966 IMG_DATA_FORMAT_RESERVED_15 = 0xf,
967 IMG_DATA_FORMAT_5_6_5 = 0x10,
968 IMG_DATA_FORMAT_1_5_5_5 = 0x11,
969 IMG_DATA_FORMAT_5_5_5_1 = 0x12,
970 IMG_DATA_FORMAT_4_4_4_4 = 0x13,
971 IMG_DATA_FORMAT_8_24 = 0x14,
972 IMG_DATA_FORMAT_24_8 = 0x15,
973 IMG_DATA_FORMAT_X24_8_32 = 0x16,
974 IMG_DATA_FORMAT_RESERVED_23 = 0x17,
975 IMG_DATA_FORMAT_RESERVED_24 = 0x18,
976 IMG_DATA_FORMAT_RESERVED_25 = 0x19,
977 IMG_DATA_FORMAT_RESERVED_26 = 0x1a,
978 IMG_DATA_FORMAT_RESERVED_27 = 0x1b,
979 IMG_DATA_FORMAT_RESERVED_28 = 0x1c,
980 IMG_DATA_FORMAT_RESERVED_29 = 0x1d,
981 IMG_DATA_FORMAT_RESERVED_30 = 0x1e,
982 IMG_DATA_FORMAT_RESERVED_31 = 0x1f,
983 IMG_DATA_FORMAT_GB_GR = 0x20,
984 IMG_DATA_FORMAT_BG_RG = 0x21,
985 IMG_DATA_FORMAT_5_9_9_9 = 0x22,
986 IMG_DATA_FORMAT_BC1 = 0x23,
987 IMG_DATA_FORMAT_BC2 = 0x24,
988 IMG_DATA_FORMAT_BC3 = 0x25,
989 IMG_DATA_FORMAT_BC4 = 0x26,
990 IMG_DATA_FORMAT_BC5 = 0x27,
991 IMG_DATA_FORMAT_BC6 = 0x28,
992 IMG_DATA_FORMAT_BC7 = 0x29,
993 IMG_DATA_FORMAT_RESERVED_42 = 0x2a,
994 IMG_DATA_FORMAT_RESERVED_43 = 0x2b,
995 IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x2c,
996 IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x2d,
997 IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x2e,
998 IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x2f,
999 IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x30,
1000 IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x31,
1001 IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x32,
1002 IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x33,
1003 IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x34,
1004 IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x35,
1005 IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x36,
1006 IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x37,
1007 IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x38,
1008 IMG_DATA_FORMAT_4_4 = 0x39,
1009 IMG_DATA_FORMAT_6_5_5 = 0x3a,
1010 IMG_DATA_FORMAT_1 = 0x3b,
1011 IMG_DATA_FORMAT_1_REVERSED = 0x3c,
1012 IMG_DATA_FORMAT_32_AS_8 = 0x3d,
1013 IMG_DATA_FORMAT_32_AS_8_8 = 0x3e,
1014 IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x3f,
1015} IMG_DATA_FORMAT;
1016typedef enum BUF_NUM_FORMAT {
1017 BUF_NUM_FORMAT_UNORM = 0x0,
1018 BUF_NUM_FORMAT_SNORM = 0x1,
1019 BUF_NUM_FORMAT_USCALED = 0x2,
1020 BUF_NUM_FORMAT_SSCALED = 0x3,
1021 BUF_NUM_FORMAT_UINT = 0x4,
1022 BUF_NUM_FORMAT_SINT = 0x5,
1023 BUF_NUM_FORMAT_RESERVED_6 = 0x6,
1024 BUF_NUM_FORMAT_FLOAT = 0x7,
1025} BUF_NUM_FORMAT;
1026typedef enum IMG_NUM_FORMAT {
1027 IMG_NUM_FORMAT_UNORM = 0x0,
1028 IMG_NUM_FORMAT_SNORM = 0x1,
1029 IMG_NUM_FORMAT_USCALED = 0x2,
1030 IMG_NUM_FORMAT_SSCALED = 0x3,
1031 IMG_NUM_FORMAT_UINT = 0x4,
1032 IMG_NUM_FORMAT_SINT = 0x5,
1033 IMG_NUM_FORMAT_RESERVED_6 = 0x6,
1034 IMG_NUM_FORMAT_FLOAT = 0x7,
1035 IMG_NUM_FORMAT_RESERVED_8 = 0x8,
1036 IMG_NUM_FORMAT_SRGB = 0x9,
1037 IMG_NUM_FORMAT_RESERVED_10 = 0xa,
1038 IMG_NUM_FORMAT_RESERVED_11 = 0xb,
1039 IMG_NUM_FORMAT_RESERVED_12 = 0xc,
1040 IMG_NUM_FORMAT_RESERVED_13 = 0xd,
1041 IMG_NUM_FORMAT_RESERVED_14 = 0xe,
1042 IMG_NUM_FORMAT_RESERVED_15 = 0xf,
1043} IMG_NUM_FORMAT;
1044typedef enum TileType {
1045 ARRAY_COLOR_TILE = 0x0,
1046 ARRAY_DEPTH_TILE = 0x1,
1047} TileType;
1048typedef enum NonDispTilingOrder {
1049 ADDR_SURF_MICRO_TILING_DISPLAY = 0x0,
1050 ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1,
1051} NonDispTilingOrder;
1052typedef enum MicroTileMode {
1053 ADDR_SURF_DISPLAY_MICRO_TILING = 0x0,
1054 ADDR_SURF_THIN_MICRO_TILING = 0x1,
1055 ADDR_SURF_DEPTH_MICRO_TILING = 0x2,
1056 ADDR_SURF_ROTATED_MICRO_TILING = 0x3,
1057 ADDR_SURF_THICK_MICRO_TILING = 0x4,
1058} MicroTileMode;
1059typedef enum TileSplit {
1060 ADDR_SURF_TILE_SPLIT_64B = 0x0,
1061 ADDR_SURF_TILE_SPLIT_128B = 0x1,
1062 ADDR_SURF_TILE_SPLIT_256B = 0x2,
1063 ADDR_SURF_TILE_SPLIT_512B = 0x3,
1064 ADDR_SURF_TILE_SPLIT_1KB = 0x4,
1065 ADDR_SURF_TILE_SPLIT_2KB = 0x5,
1066 ADDR_SURF_TILE_SPLIT_4KB = 0x6,
1067} TileSplit;
1068typedef enum SampleSplit {
1069 ADDR_SURF_SAMPLE_SPLIT_1 = 0x0,
1070 ADDR_SURF_SAMPLE_SPLIT_2 = 0x1,
1071 ADDR_SURF_SAMPLE_SPLIT_4 = 0x2,
1072 ADDR_SURF_SAMPLE_SPLIT_8 = 0x3,
1073} SampleSplit;
1074typedef enum PipeConfig {
1075 ADDR_SURF_P2 = 0x0,
1076 ADDR_SURF_P2_RESERVED0 = 0x1,
1077 ADDR_SURF_P2_RESERVED1 = 0x2,
1078 ADDR_SURF_P2_RESERVED2 = 0x3,
1079 ADDR_SURF_P4_8x16 = 0x4,
1080 ADDR_SURF_P4_16x16 = 0x5,
1081 ADDR_SURF_P4_16x32 = 0x6,
1082 ADDR_SURF_P4_32x32 = 0x7,
1083 ADDR_SURF_P8_16x16_8x16 = 0x8,
1084 ADDR_SURF_P8_16x32_8x16 = 0x9,
1085 ADDR_SURF_P8_32x32_8x16 = 0xa,
1086 ADDR_SURF_P8_16x32_16x16 = 0xb,
1087 ADDR_SURF_P8_32x32_16x16 = 0xc,
1088 ADDR_SURF_P8_32x32_16x32 = 0xd,
1089 ADDR_SURF_P8_32x64_32x32 = 0xe,
1090 ADDR_SURF_P8_RESERVED0 = 0xf,
1091 ADDR_SURF_P16_32x32_8x16 = 0x10,
1092 ADDR_SURF_P16_32x32_16x16 = 0x11,
1093} PipeConfig;
1094typedef enum NumBanks {
1095 ADDR_SURF_2_BANK = 0x0,
1096 ADDR_SURF_4_BANK = 0x1,
1097 ADDR_SURF_8_BANK = 0x2,
1098 ADDR_SURF_16_BANK = 0x3,
1099} NumBanks;
1100typedef enum BankWidth {
1101 ADDR_SURF_BANK_WIDTH_1 = 0x0,
1102 ADDR_SURF_BANK_WIDTH_2 = 0x1,
1103 ADDR_SURF_BANK_WIDTH_4 = 0x2,
1104 ADDR_SURF_BANK_WIDTH_8 = 0x3,
1105} BankWidth;
1106typedef enum BankHeight {
1107 ADDR_SURF_BANK_HEIGHT_1 = 0x0,
1108 ADDR_SURF_BANK_HEIGHT_2 = 0x1,
1109 ADDR_SURF_BANK_HEIGHT_4 = 0x2,
1110 ADDR_SURF_BANK_HEIGHT_8 = 0x3,
1111} BankHeight;
1112typedef enum BankWidthHeight {
1113 ADDR_SURF_BANK_WH_1 = 0x0,
1114 ADDR_SURF_BANK_WH_2 = 0x1,
1115 ADDR_SURF_BANK_WH_4 = 0x2,
1116 ADDR_SURF_BANK_WH_8 = 0x3,
1117} BankWidthHeight;
1118typedef enum MacroTileAspect {
1119 ADDR_SURF_MACRO_ASPECT_1 = 0x0,
1120 ADDR_SURF_MACRO_ASPECT_2 = 0x1,
1121 ADDR_SURF_MACRO_ASPECT_4 = 0x2,
1122 ADDR_SURF_MACRO_ASPECT_8 = 0x3,
1123} MacroTileAspect;
1124typedef enum GATCL1RequestType {
1125 GATCL1_TYPE_NORMAL = 0x0,
1126 GATCL1_TYPE_SHOOTDOWN = 0x1,
1127 GATCL1_TYPE_BYPASS = 0x2,
1128} GATCL1RequestType;
1129typedef enum TCC_CACHE_POLICIES {
1130 TCC_CACHE_POLICY_LRU = 0x0,
1131 TCC_CACHE_POLICY_STREAM = 0x1,
1132} TCC_CACHE_POLICIES;
1133typedef enum MTYPE {
1134 MTYPE_NC_NV = 0x0,
1135 MTYPE_NC = 0x1,
1136 MTYPE_CC = 0x2,
1137 MTYPE_UC = 0x3,
1138} MTYPE;
1139typedef enum PERFMON_COUNTER_MODE {
1140 PERFMON_COUNTER_MODE_ACCUM = 0x0,
1141 PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x1,
1142 PERFMON_COUNTER_MODE_MAX = 0x2,
1143 PERFMON_COUNTER_MODE_DIRTY = 0x3,
1144 PERFMON_COUNTER_MODE_SAMPLE = 0x4,
1145 PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x5,
1146 PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x6,
1147 PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x7,
1148 PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x8,
1149 PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x9,
1150 PERFMON_COUNTER_MODE_RESERVED = 0xf,
1151} PERFMON_COUNTER_MODE;
1152typedef enum PERFMON_SPM_MODE {
1153 PERFMON_SPM_MODE_OFF = 0x0,
1154 PERFMON_SPM_MODE_16BIT_CLAMP = 0x1,
1155 PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x2,
1156 PERFMON_SPM_MODE_32BIT_CLAMP = 0x3,
1157 PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x4,
1158 PERFMON_SPM_MODE_RESERVED_5 = 0x5,
1159 PERFMON_SPM_MODE_RESERVED_6 = 0x6,
1160 PERFMON_SPM_MODE_RESERVED_7 = 0x7,
1161 PERFMON_SPM_MODE_TEST_MODE_0 = 0x8,
1162 PERFMON_SPM_MODE_TEST_MODE_1 = 0x9,
1163 PERFMON_SPM_MODE_TEST_MODE_2 = 0xa,
1164} PERFMON_SPM_MODE;
1165typedef enum SurfaceTiling {
1166 ARRAY_LINEAR = 0x0,
1167 ARRAY_TILED = 0x1,
1168} SurfaceTiling;
1169typedef enum SurfaceArray {
1170 ARRAY_1D = 0x0,
1171 ARRAY_2D = 0x1,
1172 ARRAY_3D = 0x2,
1173 ARRAY_3D_SLICE = 0x3,
1174} SurfaceArray;
1175typedef enum ColorArray {
1176 ARRAY_2D_ALT_COLOR = 0x0,
1177 ARRAY_2D_COLOR = 0x1,
1178 ARRAY_3D_SLICE_COLOR = 0x3,
1179} ColorArray;
1180typedef enum DepthArray {
1181 ARRAY_2D_ALT_DEPTH = 0x0,
1182 ARRAY_2D_DEPTH = 0x1,
1183} DepthArray;
1184typedef enum ENUM_NUM_SIMD_PER_CU {
1185 NUM_SIMD_PER_CU = 0x4,
1186} ENUM_NUM_SIMD_PER_CU;
1187typedef enum MEM_PWR_FORCE_CTRL {
1188 NO_FORCE_REQUEST = 0x0,
1189 FORCE_LIGHT_SLEEP_REQUEST = 0x1,
1190 FORCE_DEEP_SLEEP_REQUEST = 0x2,
1191 FORCE_SHUT_DOWN_REQUEST = 0x3,
1192} MEM_PWR_FORCE_CTRL;
1193typedef enum MEM_PWR_FORCE_CTRL2 {
1194 NO_FORCE_REQ = 0x0,
1195 FORCE_LIGHT_SLEEP_REQ = 0x1,
1196} MEM_PWR_FORCE_CTRL2;
1197typedef enum MEM_PWR_DIS_CTRL {
1198 ENABLE_MEM_PWR_CTRL = 0x0,
1199 DISABLE_MEM_PWR_CTRL = 0x1,
1200} MEM_PWR_DIS_CTRL;
1201typedef enum MEM_PWR_SEL_CTRL {
1202 DYNAMIC_SHUT_DOWN_ENABLE = 0x0,
1203 DYNAMIC_DEEP_SLEEP_ENABLE = 0x1,
1204 DYNAMIC_LIGHT_SLEEP_ENABLE = 0x2,
1205} MEM_PWR_SEL_CTRL;
1206typedef enum MEM_PWR_SEL_CTRL2 {
1207 DYNAMIC_DEEP_SLEEP_EN = 0x0,
1208 DYNAMIC_LIGHT_SLEEP_EN = 0x1,
1209} MEM_PWR_SEL_CTRL2;
1210
1211#endif /* UVD_5_0_ENUM_H */
diff --git a/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h
new file mode 100644
index 000000000000..64749b72a0a6
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/uvd/uvd_5_0_sh_mask.h
@@ -0,0 +1,1046 @@
1/*
2 * UVD_5_0 Register documentation
3 *
4 * Copyright (C) 2014 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24#ifndef UVD_5_0_SH_MASK_H
25#define UVD_5_0_SH_MASK_H
26
27#define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28#define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29#define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30#define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31#define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32#define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33#define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34#define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35#define UVD_SEMA_CMD__MODE_MASK 0x40
36#define UVD_SEMA_CMD__MODE__SHIFT 0x6
37#define UVD_SEMA_CMD__VMID_EN_MASK 0x80
38#define UVD_SEMA_CMD__VMID_EN__SHIFT 0x7
39#define UVD_SEMA_CMD__VMID_MASK 0xf00
40#define UVD_SEMA_CMD__VMID__SHIFT 0x8
41#define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK 0x1
42#define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT 0x0
43#define UVD_GPCOM_VCPU_CMD__CMD_MASK 0x7ffffffe
44#define UVD_GPCOM_VCPU_CMD__CMD__SHIFT 0x1
45#define UVD_GPCOM_VCPU_CMD__CMD_SOURCE_MASK 0x80000000
46#define UVD_GPCOM_VCPU_CMD__CMD_SOURCE__SHIFT 0x1f
47#define UVD_GPCOM_VCPU_DATA0__DATA0_MASK 0xffffffff
48#define UVD_GPCOM_VCPU_DATA0__DATA0__SHIFT 0x0
49#define UVD_GPCOM_VCPU_DATA1__DATA1_MASK 0xffffffff
50#define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 0x0
51#define UVD_ENGINE_CNTL__ENGINE_START_MASK 0x1
52#define UVD_ENGINE_CNTL__ENGINE_START__SHIFT 0x0
53#define UVD_ENGINE_CNTL__ENGINE_START_MODE_MASK 0x2
54#define UVD_ENGINE_CNTL__ENGINE_START_MODE__SHIFT 0x1
55#define UVD_UDEC_ADDR_CONFIG__NUM_PIPES_MASK 0x7
56#define UVD_UDEC_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
57#define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
58#define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
59#define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
60#define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
61#define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
62#define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
63#define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
64#define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
65#define UVD_UDEC_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
66#define UVD_UDEC_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
67#define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
68#define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
69#define UVD_UDEC_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
70#define UVD_UDEC_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
71#define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
72#define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
73#define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES_MASK 0x7
74#define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
75#define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
76#define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
77#define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
78#define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
79#define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
80#define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
81#define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
82#define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
83#define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
84#define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
85#define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
86#define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
87#define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
88#define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
89#define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
90#define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
91#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES_MASK 0x7
92#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
93#define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
94#define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
95#define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
96#define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
97#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
98#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
99#define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
100#define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
101#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
102#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
103#define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
104#define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
105#define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
106#define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
107#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
108#define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
109#define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xffffffff
110#define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
111#define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xffffffff
112#define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
113#define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xffffffff
114#define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
115#define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xffffffff
116#define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
117#define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK 0xffffffff
118#define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0
119#define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xffffffff
120#define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0
121#define UVD_SEMA_CNTL__SEMAPHORE_EN_MASK 0x1
122#define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT 0x0
123#define UVD_SEMA_CNTL__ADVANCED_MODE_DIS_MASK 0x2
124#define UVD_SEMA_CNTL__ADVANCED_MODE_DIS__SHIFT 0x1
125#define UVD_LMI_EXT40_ADDR__ADDR_MASK 0xff
126#define UVD_LMI_EXT40_ADDR__ADDR__SHIFT 0x0
127#define UVD_LMI_EXT40_ADDR__INDEX_MASK 0x1f0000
128#define UVD_LMI_EXT40_ADDR__INDEX__SHIFT 0x10
129#define UVD_LMI_EXT40_ADDR__WRITE_ADDR_MASK 0x80000000
130#define UVD_LMI_EXT40_ADDR__WRITE_ADDR__SHIFT 0x1f
131#define UVD_CTX_INDEX__INDEX_MASK 0x1ff
132#define UVD_CTX_INDEX__INDEX__SHIFT 0x0
133#define UVD_CTX_DATA__DATA_MASK 0xffffffff
134#define UVD_CTX_DATA__DATA__SHIFT 0x0
135#define UVD_CGC_GATE__SYS_MASK 0x1
136#define UVD_CGC_GATE__SYS__SHIFT 0x0
137#define UVD_CGC_GATE__UDEC_MASK 0x2
138#define UVD_CGC_GATE__UDEC__SHIFT 0x1
139#define UVD_CGC_GATE__MPEG2_MASK 0x4
140#define UVD_CGC_GATE__MPEG2__SHIFT 0x2
141#define UVD_CGC_GATE__REGS_MASK 0x8
142#define UVD_CGC_GATE__REGS__SHIFT 0x3
143#define UVD_CGC_GATE__RBC_MASK 0x10
144#define UVD_CGC_GATE__RBC__SHIFT 0x4
145#define UVD_CGC_GATE__LMI_MC_MASK 0x20
146#define UVD_CGC_GATE__LMI_MC__SHIFT 0x5
147#define UVD_CGC_GATE__LMI_UMC_MASK 0x40
148#define UVD_CGC_GATE__LMI_UMC__SHIFT 0x6
149#define UVD_CGC_GATE__IDCT_MASK 0x80
150#define UVD_CGC_GATE__IDCT__SHIFT 0x7
151#define UVD_CGC_GATE__MPRD_MASK 0x100
152#define UVD_CGC_GATE__MPRD__SHIFT 0x8
153#define UVD_CGC_GATE__MPC_MASK 0x200
154#define UVD_CGC_GATE__MPC__SHIFT 0x9
155#define UVD_CGC_GATE__LBSI_MASK 0x400
156#define UVD_CGC_GATE__LBSI__SHIFT 0xa
157#define UVD_CGC_GATE__LRBBM_MASK 0x800
158#define UVD_CGC_GATE__LRBBM__SHIFT 0xb
159#define UVD_CGC_GATE__UDEC_RE_MASK 0x1000
160#define UVD_CGC_GATE__UDEC_RE__SHIFT 0xc
161#define UVD_CGC_GATE__UDEC_CM_MASK 0x2000
162#define UVD_CGC_GATE__UDEC_CM__SHIFT 0xd
163#define UVD_CGC_GATE__UDEC_IT_MASK 0x4000
164#define UVD_CGC_GATE__UDEC_IT__SHIFT 0xe
165#define UVD_CGC_GATE__UDEC_DB_MASK 0x8000
166#define UVD_CGC_GATE__UDEC_DB__SHIFT 0xf
167#define UVD_CGC_GATE__UDEC_MP_MASK 0x10000
168#define UVD_CGC_GATE__UDEC_MP__SHIFT 0x10
169#define UVD_CGC_GATE__WCB_MASK 0x20000
170#define UVD_CGC_GATE__WCB__SHIFT 0x11
171#define UVD_CGC_GATE__VCPU_MASK 0x40000
172#define UVD_CGC_GATE__VCPU__SHIFT 0x12
173#define UVD_CGC_GATE__SCPU_MASK 0x80000
174#define UVD_CGC_GATE__SCPU__SHIFT 0x13
175#define UVD_CGC_GATE__JPEG_MASK 0x100000
176#define UVD_CGC_GATE__JPEG__SHIFT 0x14
177#define UVD_CGC_GATE__JPEG2_MASK 0x200000
178#define UVD_CGC_GATE__JPEG2__SHIFT 0x15
179#define UVD_CGC_STATUS__SYS_SCLK_MASK 0x1
180#define UVD_CGC_STATUS__SYS_SCLK__SHIFT 0x0
181#define UVD_CGC_STATUS__SYS_DCLK_MASK 0x2
182#define UVD_CGC_STATUS__SYS_DCLK__SHIFT 0x1
183#define UVD_CGC_STATUS__SYS_VCLK_MASK 0x4
184#define UVD_CGC_STATUS__SYS_VCLK__SHIFT 0x2
185#define UVD_CGC_STATUS__UDEC_SCLK_MASK 0x8
186#define UVD_CGC_STATUS__UDEC_SCLK__SHIFT 0x3
187#define UVD_CGC_STATUS__UDEC_DCLK_MASK 0x10
188#define UVD_CGC_STATUS__UDEC_DCLK__SHIFT 0x4
189#define UVD_CGC_STATUS__UDEC_VCLK_MASK 0x20
190#define UVD_CGC_STATUS__UDEC_VCLK__SHIFT 0x5
191#define UVD_CGC_STATUS__MPEG2_SCLK_MASK 0x40
192#define UVD_CGC_STATUS__MPEG2_SCLK__SHIFT 0x6
193#define UVD_CGC_STATUS__MPEG2_DCLK_MASK 0x80
194#define UVD_CGC_STATUS__MPEG2_DCLK__SHIFT 0x7
195#define UVD_CGC_STATUS__MPEG2_VCLK_MASK 0x100
196#define UVD_CGC_STATUS__MPEG2_VCLK__SHIFT 0x8
197#define UVD_CGC_STATUS__REGS_SCLK_MASK 0x200
198#define UVD_CGC_STATUS__REGS_SCLK__SHIFT 0x9
199#define UVD_CGC_STATUS__REGS_VCLK_MASK 0x400
200#define UVD_CGC_STATUS__REGS_VCLK__SHIFT 0xa
201#define UVD_CGC_STATUS__RBC_SCLK_MASK 0x800
202#define UVD_CGC_STATUS__RBC_SCLK__SHIFT 0xb
203#define UVD_CGC_STATUS__LMI_MC_SCLK_MASK 0x1000
204#define UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT 0xc
205#define UVD_CGC_STATUS__LMI_UMC_SCLK_MASK 0x2000
206#define UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT 0xd
207#define UVD_CGC_STATUS__IDCT_SCLK_MASK 0x4000
208#define UVD_CGC_STATUS__IDCT_SCLK__SHIFT 0xe
209#define UVD_CGC_STATUS__IDCT_VCLK_MASK 0x8000
210#define UVD_CGC_STATUS__IDCT_VCLK__SHIFT 0xf
211#define UVD_CGC_STATUS__MPRD_SCLK_MASK 0x10000
212#define UVD_CGC_STATUS__MPRD_SCLK__SHIFT 0x10
213#define UVD_CGC_STATUS__MPRD_DCLK_MASK 0x20000
214#define UVD_CGC_STATUS__MPRD_DCLK__SHIFT 0x11
215#define UVD_CGC_STATUS__MPRD_VCLK_MASK 0x40000
216#define UVD_CGC_STATUS__MPRD_VCLK__SHIFT 0x12
217#define UVD_CGC_STATUS__MPC_SCLK_MASK 0x80000
218#define UVD_CGC_STATUS__MPC_SCLK__SHIFT 0x13
219#define UVD_CGC_STATUS__MPC_DCLK_MASK 0x100000
220#define UVD_CGC_STATUS__MPC_DCLK__SHIFT 0x14
221#define UVD_CGC_STATUS__LBSI_SCLK_MASK 0x200000
222#define UVD_CGC_STATUS__LBSI_SCLK__SHIFT 0x15
223#define UVD_CGC_STATUS__LBSI_VCLK_MASK 0x400000
224#define UVD_CGC_STATUS__LBSI_VCLK__SHIFT 0x16
225#define UVD_CGC_STATUS__LRBBM_SCLK_MASK 0x800000
226#define UVD_CGC_STATUS__LRBBM_SCLK__SHIFT 0x17
227#define UVD_CGC_STATUS__WCB_SCLK_MASK 0x1000000
228#define UVD_CGC_STATUS__WCB_SCLK__SHIFT 0x18
229#define UVD_CGC_STATUS__VCPU_SCLK_MASK 0x2000000
230#define UVD_CGC_STATUS__VCPU_SCLK__SHIFT 0x19
231#define UVD_CGC_STATUS__VCPU_VCLK_MASK 0x4000000
232#define UVD_CGC_STATUS__VCPU_VCLK__SHIFT 0x1a
233#define UVD_CGC_STATUS__SCPU_SCLK_MASK 0x8000000
234#define UVD_CGC_STATUS__SCPU_SCLK__SHIFT 0x1b
235#define UVD_CGC_STATUS__SCPU_VCLK_MASK 0x10000000
236#define UVD_CGC_STATUS__SCPU_VCLK__SHIFT 0x1c
237#define UVD_CGC_STATUS__JPEG_ACTIVE_MASK 0x40000000
238#define UVD_CGC_STATUS__JPEG_ACTIVE__SHIFT 0x1e
239#define UVD_CGC_STATUS__ALL_DEC_ACTIVE_MASK 0x80000000
240#define UVD_CGC_STATUS__ALL_DEC_ACTIVE__SHIFT 0x1f
241#define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x1
242#define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0
243#define UVD_CGC_CTRL__JPEG2_MODE_MASK 0x2
244#define UVD_CGC_CTRL__JPEG2_MODE__SHIFT 0x1
245#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x3c
246#define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2
247#define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x7c0
248#define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6
249#define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x800
250#define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0xb
251#define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x1000
252#define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0xc
253#define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x2000
254#define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd
255#define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x4000
256#define UVD_CGC_CTRL__UDEC_DB_MODE__SHIFT 0xe
257#define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x8000
258#define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0xf
259#define UVD_CGC_CTRL__SYS_MODE_MASK 0x10000
260#define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x10
261#define UVD_CGC_CTRL__UDEC_MODE_MASK 0x20000
262#define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x11
263#define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x40000
264#define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x12
265#define UVD_CGC_CTRL__REGS_MODE_MASK 0x80000
266#define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x13
267#define UVD_CGC_CTRL__RBC_MODE_MASK 0x100000
268#define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x14
269#define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x200000
270#define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x15
271#define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x400000
272#define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x16
273#define UVD_CGC_CTRL__IDCT_MODE_MASK 0x800000
274#define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x17
275#define UVD_CGC_CTRL__MPRD_MODE_MASK 0x1000000
276#define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x18
277#define UVD_CGC_CTRL__MPC_MODE_MASK 0x2000000
278#define UVD_CGC_CTRL__MPC_MODE__SHIFT 0x19
279#define UVD_CGC_CTRL__LBSI_MODE_MASK 0x4000000
280#define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x1a
281#define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x8000000
282#define UVD_CGC_CTRL__LRBBM_MODE__SHIFT 0x1b
283#define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000
284#define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x1c
285#define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000
286#define UVD_CGC_CTRL__VCPU_MODE__SHIFT 0x1d
287#define UVD_CGC_CTRL__SCPU_MODE_MASK 0x40000000
288#define UVD_CGC_CTRL__SCPU_MODE__SHIFT 0x1e
289#define UVD_CGC_CTRL__JPEG_MODE_MASK 0x80000000
290#define UVD_CGC_CTRL__JPEG_MODE__SHIFT 0x1f
291#define UVD_CGC_UDEC_STATUS__RE_SCLK_MASK 0x1
292#define UVD_CGC_UDEC_STATUS__RE_SCLK__SHIFT 0x0
293#define UVD_CGC_UDEC_STATUS__RE_DCLK_MASK 0x2
294#define UVD_CGC_UDEC_STATUS__RE_DCLK__SHIFT 0x1
295#define UVD_CGC_UDEC_STATUS__RE_VCLK_MASK 0x4
296#define UVD_CGC_UDEC_STATUS__RE_VCLK__SHIFT 0x2
297#define UVD_CGC_UDEC_STATUS__CM_SCLK_MASK 0x8
298#define UVD_CGC_UDEC_STATUS__CM_SCLK__SHIFT 0x3
299#define UVD_CGC_UDEC_STATUS__CM_DCLK_MASK 0x10
300#define UVD_CGC_UDEC_STATUS__CM_DCLK__SHIFT 0x4
301#define UVD_CGC_UDEC_STATUS__CM_VCLK_MASK 0x20
302#define UVD_CGC_UDEC_STATUS__CM_VCLK__SHIFT 0x5
303#define UVD_CGC_UDEC_STATUS__IT_SCLK_MASK 0x40
304#define UVD_CGC_UDEC_STATUS__IT_SCLK__SHIFT 0x6
305#define UVD_CGC_UDEC_STATUS__IT_DCLK_MASK 0x80
306#define UVD_CGC_UDEC_STATUS__IT_DCLK__SHIFT 0x7
307#define UVD_CGC_UDEC_STATUS__IT_VCLK_MASK 0x100
308#define UVD_CGC_UDEC_STATUS__IT_VCLK__SHIFT 0x8
309#define UVD_CGC_UDEC_STATUS__DB_SCLK_MASK 0x200
310#define UVD_CGC_UDEC_STATUS__DB_SCLK__SHIFT 0x9
311#define UVD_CGC_UDEC_STATUS__DB_DCLK_MASK 0x400
312#define UVD_CGC_UDEC_STATUS__DB_DCLK__SHIFT 0xa
313#define UVD_CGC_UDEC_STATUS__DB_VCLK_MASK 0x800
314#define UVD_CGC_UDEC_STATUS__DB_VCLK__SHIFT 0xb
315#define UVD_CGC_UDEC_STATUS__MP_SCLK_MASK 0x1000
316#define UVD_CGC_UDEC_STATUS__MP_SCLK__SHIFT 0xc
317#define UVD_CGC_UDEC_STATUS__MP_DCLK_MASK 0x2000
318#define UVD_CGC_UDEC_STATUS__MP_DCLK__SHIFT 0xd
319#define UVD_CGC_UDEC_STATUS__MP_VCLK_MASK 0x4000
320#define UVD_CGC_UDEC_STATUS__MP_VCLK__SHIFT 0xe
321#define UVD_CGC_UDEC_STATUS__JPEG_VCLK_MASK 0x8000
322#define UVD_CGC_UDEC_STATUS__JPEG_VCLK__SHIFT 0xf
323#define UVD_CGC_UDEC_STATUS__JPEG_SCLK_MASK 0x10000
324#define UVD_CGC_UDEC_STATUS__JPEG_SCLK__SHIFT 0x10
325#define UVD_CGC_UDEC_STATUS__JPEG2_VCLK_MASK 0x20000
326#define UVD_CGC_UDEC_STATUS__JPEG2_VCLK__SHIFT 0x11
327#define UVD_CGC_UDEC_STATUS__JPEG2_SCLK_MASK 0x40000
328#define UVD_CGC_UDEC_STATUS__JPEG2_SCLK__SHIFT 0x12
329#define UVD_LMI_CTRL2__SPH_DIS_MASK 0x1
330#define UVD_LMI_CTRL2__SPH_DIS__SHIFT 0x0
331#define UVD_LMI_CTRL2__STALL_ARB_MASK 0x2
332#define UVD_LMI_CTRL2__STALL_ARB__SHIFT 0x1
333#define UVD_LMI_CTRL2__ASSERT_UMC_URGENT_MASK 0x4
334#define UVD_LMI_CTRL2__ASSERT_UMC_URGENT__SHIFT 0x2
335#define UVD_LMI_CTRL2__MASK_UMC_URGENT_MASK 0x8
336#define UVD_LMI_CTRL2__MASK_UMC_URGENT__SHIFT 0x3
337#define UVD_LMI_CTRL2__MCIF_WR_WATERMARK_MASK 0x70
338#define UVD_LMI_CTRL2__MCIF_WR_WATERMARK__SHIFT 0x4
339#define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS_MASK 0x80
340#define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT 0x7
341#define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x100
342#define UVD_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8
343#define UVD_LMI_CTRL2__MC_READ_ID_SEL_MASK 0x600
344#define UVD_LMI_CTRL2__MC_READ_ID_SEL__SHIFT 0x9
345#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL_MASK 0x1800
346#define UVD_LMI_CTRL2__MC_WRITE_ID_SEL__SHIFT 0xb
347#define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN_MASK 0x2000
348#define UVD_LMI_CTRL2__VCPU_NC0_EXT_EN__SHIFT 0xd
349#define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN_MASK 0x4000
350#define UVD_LMI_CTRL2__VCPU_NC1_EXT_EN__SHIFT 0xe
351#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN_MASK 0x8000
352#define UVD_LMI_CTRL2__SPU_EXTRA_CID_EN__SHIFT 0xf
353#define UVD_LMI_CTRL2__RE_OFFLOAD_EN_MASK 0x10000
354#define UVD_LMI_CTRL2__RE_OFFLOAD_EN__SHIFT 0x10
355#define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM_MASK 0x1fe0000
356#define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT 0x11
357#define UVD_MASTINT_EN__OVERRUN_RST_MASK 0x1
358#define UVD_MASTINT_EN__OVERRUN_RST__SHIFT 0x0
359#define UVD_MASTINT_EN__VCPU_EN_MASK 0x2
360#define UVD_MASTINT_EN__VCPU_EN__SHIFT 0x1
361#define UVD_MASTINT_EN__SYS_EN_MASK 0x4
362#define UVD_MASTINT_EN__SYS_EN__SHIFT 0x2
363#define UVD_MASTINT_EN__INT_OVERRUN_MASK 0x7ffff0
364#define UVD_MASTINT_EN__INT_OVERRUN__SHIFT 0x4
365#define UVD_LMI_ADDR_EXT__VCPU_ADDR_EXT_MASK 0xf
366#define UVD_LMI_ADDR_EXT__VCPU_ADDR_EXT__SHIFT 0x0
367#define UVD_LMI_ADDR_EXT__CM_ADDR_EXT_MASK 0xf0
368#define UVD_LMI_ADDR_EXT__CM_ADDR_EXT__SHIFT 0x4
369#define UVD_LMI_ADDR_EXT__IT_ADDR_EXT_MASK 0xf00
370#define UVD_LMI_ADDR_EXT__IT_ADDR_EXT__SHIFT 0x8
371#define UVD_LMI_ADDR_EXT__VCPU_VM_ADDR_EXT_MASK 0xf000
372#define UVD_LMI_ADDR_EXT__VCPU_VM_ADDR_EXT__SHIFT 0xc
373#define UVD_LMI_ADDR_EXT__RE_ADDR_EXT_MASK 0xf0000
374#define UVD_LMI_ADDR_EXT__RE_ADDR_EXT__SHIFT 0x10
375#define UVD_LMI_ADDR_EXT__MP_ADDR_EXT_MASK 0xf00000
376#define UVD_LMI_ADDR_EXT__MP_ADDR_EXT__SHIFT 0x14
377#define UVD_LMI_ADDR_EXT__VCPU_NC0_ADDR_EXT_MASK 0xf000000
378#define UVD_LMI_ADDR_EXT__VCPU_NC0_ADDR_EXT__SHIFT 0x18
379#define UVD_LMI_ADDR_EXT__VCPU_NC1_ADDR_EXT_MASK 0xf0000000
380#define UVD_LMI_ADDR_EXT__VCPU_NC1_ADDR_EXT__SHIFT 0x1c
381#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_MASK 0xff
382#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x0
383#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x100
384#define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x8
385#define UVD_LMI_CTRL__REQ_MODE_MASK 0x200
386#define UVD_LMI_CTRL__REQ_MODE__SHIFT 0x9
387#define UVD_LMI_CTRL__ASSERT_MC_URGENT_MASK 0x800
388#define UVD_LMI_CTRL__ASSERT_MC_URGENT__SHIFT 0xb
389#define UVD_LMI_CTRL__MASK_MC_URGENT_MASK 0x1000
390#define UVD_LMI_CTRL__MASK_MC_URGENT__SHIFT 0xc
391#define UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK 0x2000
392#define UVD_LMI_CTRL__DATA_COHERENCY_EN__SHIFT 0xd
393#define UVD_LMI_CTRL__CRC_RESET_MASK 0x4000
394#define UVD_LMI_CTRL__CRC_RESET__SHIFT 0xe
395#define UVD_LMI_CTRL__CRC_SEL_MASK 0xf8000
396#define UVD_LMI_CTRL__CRC_SEL__SHIFT 0xf
397#define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL_MASK 0x100000
398#define UVD_LMI_CTRL__DISABLE_ON_FWV_FAIL__SHIFT 0x14
399#define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x200000
400#define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x15
401#define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN_MASK 0x400000
402#define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN__SHIFT 0x16
403#define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN_MASK 0x800000
404#define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN__SHIFT 0x17
405#define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN_MASK 0x1000000
406#define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN__SHIFT 0x18
407#define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN_MASK 0x2000000
408#define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN__SHIFT 0x19
409#define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN_MASK 0x4000000
410#define UVD_LMI_CTRL__MIF_MIF_DATA_COHERENCY_EN__SHIFT 0x1a
411#define UVD_LMI_CTRL__RFU_MASK 0xf8000000
412#define UVD_LMI_CTRL__RFU__SHIFT 0x1b
413#define UVD_LMI_STATUS__READ_CLEAN_MASK 0x1
414#define UVD_LMI_STATUS__READ_CLEAN__SHIFT 0x0
415#define UVD_LMI_STATUS__WRITE_CLEAN_MASK 0x2
416#define UVD_LMI_STATUS__WRITE_CLEAN__SHIFT 0x1
417#define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK 0x4
418#define UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT 0x2
419#define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK 0x8
420#define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT 0x3
421#define UVD_LMI_STATUS__UMC_READ_CLEAN_MASK 0x10
422#define UVD_LMI_STATUS__UMC_READ_CLEAN__SHIFT 0x4
423#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_MASK 0x20
424#define UVD_LMI_STATUS__UMC_WRITE_CLEAN__SHIFT 0x5
425#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK 0x40
426#define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW__SHIFT 0x6
427#define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE_MASK 0x80
428#define UVD_LMI_STATUS__PENDING_UVD_MC_WRITE__SHIFT 0x7
429#define UVD_LMI_STATUS__READ_CLEAN_RAW_MASK 0x100
430#define UVD_LMI_STATUS__READ_CLEAN_RAW__SHIFT 0x8
431#define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK 0x200
432#define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW__SHIFT 0x9
433#define UVD_LMI_STATUS__UMC_UVD_IDLE_MASK 0x400
434#define UVD_LMI_STATUS__UMC_UVD_IDLE__SHIFT 0xa
435#define UVD_LMI_STATUS__UMC_AVP_IDLE_MASK 0x800
436#define UVD_LMI_STATUS__UMC_AVP_IDLE__SHIFT 0xb
437#define UVD_LMI_STATUS__ADP_MC_READ_CLEAN_MASK 0x1000
438#define UVD_LMI_STATUS__ADP_MC_READ_CLEAN__SHIFT 0xc
439#define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN_MASK 0x2000
440#define UVD_LMI_STATUS__ADP_UMC_READ_CLEAN__SHIFT 0xd
441#define UVD_LMI_SWAP_CNTL__RB_MC_SWAP_MASK 0x3
442#define UVD_LMI_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0
443#define UVD_LMI_SWAP_CNTL__IB_MC_SWAP_MASK 0xc
444#define UVD_LMI_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2
445#define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP_MASK 0x30
446#define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP__SHIFT 0x4
447#define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP_MASK 0xc0
448#define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP__SHIFT 0x6
449#define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x300
450#define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x8
451#define UVD_LMI_SWAP_CNTL__CM_MC_SWAP_MASK 0xc00
452#define UVD_LMI_SWAP_CNTL__CM_MC_SWAP__SHIFT 0xa
453#define UVD_LMI_SWAP_CNTL__IT_MC_SWAP_MASK 0x3000
454#define UVD_LMI_SWAP_CNTL__IT_MC_SWAP__SHIFT 0xc
455#define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP_MASK 0xc000
456#define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP__SHIFT 0xe
457#define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP_MASK 0x30000
458#define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP__SHIFT 0x10
459#define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP_MASK 0xc0000
460#define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP__SHIFT 0x12
461#define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP_MASK 0xc00000
462#define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP__SHIFT 0x16
463#define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP_MASK 0x3000000
464#define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP__SHIFT 0x18
465#define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP_MASK 0xc000000
466#define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP__SHIFT 0x1a
467#define UVD_LMI_SWAP_CNTL__RE_MC_SWAP_MASK 0x30000000
468#define UVD_LMI_SWAP_CNTL__RE_MC_SWAP__SHIFT 0x1c
469#define UVD_LMI_SWAP_CNTL__MP_MC_SWAP_MASK 0xc0000000
470#define UVD_LMI_SWAP_CNTL__MP_MC_SWAP__SHIFT 0x1e
471#define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP_MASK 0x3
472#define UVD_MP_SWAP_CNTL__MP_REF0_MC_SWAP__SHIFT 0x0
473#define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP_MASK 0xc
474#define UVD_MP_SWAP_CNTL__MP_REF1_MC_SWAP__SHIFT 0x2
475#define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP_MASK 0x30
476#define UVD_MP_SWAP_CNTL__MP_REF2_MC_SWAP__SHIFT 0x4
477#define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP_MASK 0xc0
478#define UVD_MP_SWAP_CNTL__MP_REF3_MC_SWAP__SHIFT 0x6
479#define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP_MASK 0x300
480#define UVD_MP_SWAP_CNTL__MP_REF4_MC_SWAP__SHIFT 0x8
481#define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP_MASK 0xc00
482#define UVD_MP_SWAP_CNTL__MP_REF5_MC_SWAP__SHIFT 0xa
483#define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP_MASK 0x3000
484#define UVD_MP_SWAP_CNTL__MP_REF6_MC_SWAP__SHIFT 0xc
485#define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP_MASK 0xc000
486#define UVD_MP_SWAP_CNTL__MP_REF7_MC_SWAP__SHIFT 0xe
487#define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP_MASK 0x30000
488#define UVD_MP_SWAP_CNTL__MP_REF8_MC_SWAP__SHIFT 0x10
489#define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP_MASK 0xc0000
490#define UVD_MP_SWAP_CNTL__MP_REF9_MC_SWAP__SHIFT 0x12
491#define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP_MASK 0x300000
492#define UVD_MP_SWAP_CNTL__MP_REF10_MC_SWAP__SHIFT 0x14
493#define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP_MASK 0xc00000
494#define UVD_MP_SWAP_CNTL__MP_REF11_MC_SWAP__SHIFT 0x16
495#define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP_MASK 0x3000000
496#define UVD_MP_SWAP_CNTL__MP_REF12_MC_SWAP__SHIFT 0x18
497#define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP_MASK 0xc000000
498#define UVD_MP_SWAP_CNTL__MP_REF13_MC_SWAP__SHIFT 0x1a
499#define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP_MASK 0x30000000
500#define UVD_MP_SWAP_CNTL__MP_REF14_MC_SWAP__SHIFT 0x1c
501#define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP_MASK 0xc0000000
502#define UVD_MP_SWAP_CNTL__MP_REF15_MC_SWAP__SHIFT 0x1e
503#define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x38
504#define UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT 0x3
505#define UVD_MPC_CNTL__PERF_RST_MASK 0x40
506#define UVD_MPC_CNTL__PERF_RST__SHIFT 0x6
507#define UVD_MPC_CNTL__DBG_MUX_MASK 0xf00
508#define UVD_MPC_CNTL__DBG_MUX__SHIFT 0x8
509#define UVD_MPC_CNTL__AVE_WEIGHT_MASK 0x30000
510#define UVD_MPC_CNTL__AVE_WEIGHT__SHIFT 0x10
511#define UVD_MPC_CNTL__URGENT_EN_MASK 0x40000
512#define UVD_MPC_CNTL__URGENT_EN__SHIFT 0x12
513#define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x3f
514#define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x0
515#define UVD_MPC_SET_MUXA0__VARA_1_MASK 0xfc0
516#define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6
517#define UVD_MPC_SET_MUXA0__VARA_2_MASK 0x3f000
518#define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc
519#define UVD_MPC_SET_MUXA0__VARA_3_MASK 0xfc0000
520#define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12
521#define UVD_MPC_SET_MUXA0__VARA_4_MASK 0x3f000000
522#define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18
523#define UVD_MPC_SET_MUXA1__VARA_5_MASK 0x3f
524#define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x0
525#define UVD_MPC_SET_MUXA1__VARA_6_MASK 0xfc0
526#define UVD_MPC_SET_MUXA1__VARA_6__SHIFT 0x6
527#define UVD_MPC_SET_MUXA1__VARA_7_MASK 0x3f000
528#define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0xc
529#define UVD_MPC_SET_MUXB0__VARB_0_MASK 0x3f
530#define UVD_MPC_SET_MUXB0__VARB_0__SHIFT 0x0
531#define UVD_MPC_SET_MUXB0__VARB_1_MASK 0xfc0
532#define UVD_MPC_SET_MUXB0__VARB_1__SHIFT 0x6
533#define UVD_MPC_SET_MUXB0__VARB_2_MASK 0x3f000
534#define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc
535#define UVD_MPC_SET_MUXB0__VARB_3_MASK 0xfc0000
536#define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12
537#define UVD_MPC_SET_MUXB0__VARB_4_MASK 0x3f000000
538#define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18
539#define UVD_MPC_SET_MUXB1__VARB_5_MASK 0x3f
540#define UVD_MPC_SET_MUXB1__VARB_5__SHIFT 0x0
541#define UVD_MPC_SET_MUXB1__VARB_6_MASK 0xfc0
542#define UVD_MPC_SET_MUXB1__VARB_6__SHIFT 0x6
543#define UVD_MPC_SET_MUXB1__VARB_7_MASK 0x3f000
544#define UVD_MPC_SET_MUXB1__VARB_7__SHIFT 0xc
545#define UVD_MPC_SET_MUX__SET_0_MASK 0x7
546#define UVD_MPC_SET_MUX__SET_0__SHIFT 0x0
547#define UVD_MPC_SET_MUX__SET_1_MASK 0x38
548#define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3
549#define UVD_MPC_SET_MUX__SET_2_MASK 0x1c0
550#define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6
551#define UVD_MPC_SET_ALU__FUNCT_MASK 0x7
552#define UVD_MPC_SET_ALU__FUNCT__SHIFT 0x0
553#define UVD_MPC_SET_ALU__OPERAND_MASK 0xff0
554#define UVD_MPC_SET_ALU__OPERAND__SHIFT 0x4
555#define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x1ffffff
556#define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0
557#define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK 0x1fffff
558#define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT 0x0
559#define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK 0x1ffffff
560#define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 0x0
561#define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK 0x1fffff
562#define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1__SHIFT 0x0
563#define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2_MASK 0x1ffffff
564#define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x0
565#define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2_MASK 0x1fffff
566#define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT 0x0
567#define UVD_VCPU_CNTL__IRQ_ERR_MASK 0xf
568#define UVD_VCPU_CNTL__IRQ_ERR__SHIFT 0x0
569#define UVD_VCPU_CNTL__AXI_MAX_BRST_SIZE_IS_4_MASK 0x10
570#define UVD_VCPU_CNTL__AXI_MAX_BRST_SIZE_IS_4__SHIFT 0x4
571#define UVD_VCPU_CNTL__PMB_ED_ENABLE_MASK 0x20
572#define UVD_VCPU_CNTL__PMB_ED_ENABLE__SHIFT 0x5
573#define UVD_VCPU_CNTL__PMB_SOFT_RESET_MASK 0x40
574#define UVD_VCPU_CNTL__PMB_SOFT_RESET__SHIFT 0x6
575#define UVD_VCPU_CNTL__RBBM_SOFT_RESET_MASK 0x80
576#define UVD_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x7
577#define UVD_VCPU_CNTL__ABORT_REQ_MASK 0x100
578#define UVD_VCPU_CNTL__ABORT_REQ__SHIFT 0x8
579#define UVD_VCPU_CNTL__CLK_EN_MASK 0x200
580#define UVD_VCPU_CNTL__CLK_EN__SHIFT 0x9
581#define UVD_VCPU_CNTL__TRCE_EN_MASK 0x400
582#define UVD_VCPU_CNTL__TRCE_EN__SHIFT 0xa
583#define UVD_VCPU_CNTL__TRCE_MUX_MASK 0x1800
584#define UVD_VCPU_CNTL__TRCE_MUX__SHIFT 0xb
585#define UVD_VCPU_CNTL__DBG_MUX_MASK 0xe000
586#define UVD_VCPU_CNTL__DBG_MUX__SHIFT 0xd
587#define UVD_VCPU_CNTL__JTAG_EN_MASK 0x10000
588#define UVD_VCPU_CNTL__JTAG_EN__SHIFT 0x10
589#define UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK 0x20000
590#define UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP__SHIFT 0x11
591#define UVD_VCPU_CNTL__TIMEOUT_DIS_MASK 0x40000
592#define UVD_VCPU_CNTL__TIMEOUT_DIS__SHIFT 0x12
593#define UVD_VCPU_CNTL__SUVD_EN_MASK 0x80000
594#define UVD_VCPU_CNTL__SUVD_EN__SHIFT 0x13
595#define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL_MASK 0xff00000
596#define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14
597#define UVD_VCPU_CNTL__CABAC_MB_ACC_MASK 0x10000000
598#define UVD_VCPU_CNTL__CABAC_MB_ACC__SHIFT 0x1c
599#define UVD_VCPU_CNTL__WMV9_EN_MASK 0x40000000
600#define UVD_VCPU_CNTL__WMV9_EN__SHIFT 0x1e
601#define UVD_VCPU_CNTL__RE_OFFLOAD_EN_MASK 0x80000000
602#define UVD_VCPU_CNTL__RE_OFFLOAD_EN__SHIFT 0x1f
603#define UVD_SOFT_RESET__RBC_SOFT_RESET_MASK 0x1
604#define UVD_SOFT_RESET__RBC_SOFT_RESET__SHIFT 0x0
605#define UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK 0x2
606#define UVD_SOFT_RESET__LBSI_SOFT_RESET__SHIFT 0x1
607#define UVD_SOFT_RESET__LMI_SOFT_RESET_MASK 0x4
608#define UVD_SOFT_RESET__LMI_SOFT_RESET__SHIFT 0x2
609#define UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK 0x8
610#define UVD_SOFT_RESET__VCPU_SOFT_RESET__SHIFT 0x3
611#define UVD_SOFT_RESET__UDEC_SOFT_RESET_MASK 0x10
612#define UVD_SOFT_RESET__UDEC_SOFT_RESET__SHIFT 0x4
613#define UVD_SOFT_RESET__CSM_SOFT_RESET_MASK 0x20
614#define UVD_SOFT_RESET__CSM_SOFT_RESET__SHIFT 0x5
615#define UVD_SOFT_RESET__CXW_SOFT_RESET_MASK 0x40
616#define UVD_SOFT_RESET__CXW_SOFT_RESET__SHIFT 0x6
617#define UVD_SOFT_RESET__TAP_SOFT_RESET_MASK 0x80
618#define UVD_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x7
619#define UVD_SOFT_RESET__MPC_SOFT_RESET_MASK 0x100
620#define UVD_SOFT_RESET__MPC_SOFT_RESET__SHIFT 0x8
621#define UVD_SOFT_RESET__JPEG_SCLK_RESET_STATUS_MASK 0x200
622#define UVD_SOFT_RESET__JPEG_SCLK_RESET_STATUS__SHIFT 0x9
623#define UVD_SOFT_RESET__IH_SOFT_RESET_MASK 0x400
624#define UVD_SOFT_RESET__IH_SOFT_RESET__SHIFT 0xa
625#define UVD_SOFT_RESET__MPRD_SOFT_RESET_MASK 0x800
626#define UVD_SOFT_RESET__MPRD_SOFT_RESET__SHIFT 0xb
627#define UVD_SOFT_RESET__IDCT_SOFT_RESET_MASK 0x1000
628#define UVD_SOFT_RESET__IDCT_SOFT_RESET__SHIFT 0xc
629#define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK 0x2000
630#define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET__SHIFT 0xd
631#define UVD_SOFT_RESET__SPH_SOFT_RESET_MASK 0x4000
632#define UVD_SOFT_RESET__SPH_SOFT_RESET__SHIFT 0xe
633#define UVD_SOFT_RESET__MIF_SOFT_RESET_MASK 0x8000
634#define UVD_SOFT_RESET__MIF_SOFT_RESET__SHIFT 0xf
635#define UVD_SOFT_RESET__LCM_SOFT_RESET_MASK 0x10000
636#define UVD_SOFT_RESET__LCM_SOFT_RESET__SHIFT 0x10
637#define UVD_SOFT_RESET__SUVD_SOFT_RESET_MASK 0x20000
638#define UVD_SOFT_RESET__SUVD_SOFT_RESET__SHIFT 0x11
639#define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS_MASK 0x40000
640#define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS__SHIFT 0x12
641#define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS_MASK 0x80000
642#define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS__SHIFT 0x13
643#define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS_MASK 0x100000
644#define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS__SHIFT 0x14
645#define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS_MASK 0x200000
646#define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS__SHIFT 0x15
647#define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS_MASK 0x400000
648#define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS__SHIFT 0x16
649#define UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS_MASK 0x800000
650#define UVD_SOFT_RESET__MPRD_VCLK_RESET_STATUS__SHIFT 0x17
651#define UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS_MASK 0x1000000
652#define UVD_SOFT_RESET__MPRD_DCLK_RESET_STATUS__SHIFT 0x18
653#define UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS_MASK 0x2000000
654#define UVD_SOFT_RESET__IDCT_VCLK_RESET_STATUS__SHIFT 0x19
655#define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS_MASK 0x4000000
656#define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS__SHIFT 0x1a
657#define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS_MASK 0x8000000
658#define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS__SHIFT 0x1b
659#define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS_MASK 0x10000000
660#define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS__SHIFT 0x1c
661#define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS_MASK 0x20000000
662#define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS__SHIFT 0x1d
663#define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS_MASK 0x40000000
664#define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS__SHIFT 0x1e
665#define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS_MASK 0x80000000
666#define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS__SHIFT 0x1f
667#define UVD_LMI_RBC_IB_VMID__IB_VMID_MASK 0xf
668#define UVD_LMI_RBC_IB_VMID__IB_VMID__SHIFT 0x0
669#define UVD_RBC_IB_SIZE__IB_SIZE_MASK 0x7ffff0
670#define UVD_RBC_IB_SIZE__IB_SIZE__SHIFT 0x4
671#define UVD_LMI_RBC_RB_VMID__RB_VMID_MASK 0xf
672#define UVD_LMI_RBC_RB_VMID__RB_VMID__SHIFT 0x0
673#define UVD_RBC_RB_RPTR__RB_RPTR_MASK 0x7ffff0
674#define UVD_RBC_RB_RPTR__RB_RPTR__SHIFT 0x4
675#define UVD_RBC_RB_WPTR__RB_WPTR_MASK 0x7ffff0
676#define UVD_RBC_RB_WPTR__RB_WPTR__SHIFT 0x4
677#define UVD_RBC_RB_CNTL__RB_BUFSZ_MASK 0x1f
678#define UVD_RBC_RB_CNTL__RB_BUFSZ__SHIFT 0x0
679#define UVD_RBC_RB_CNTL__RB_BLKSZ_MASK 0x1f00
680#define UVD_RBC_RB_CNTL__RB_BLKSZ__SHIFT 0x8
681#define UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK 0x10000
682#define UVD_RBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x10
683#define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN_MASK 0x100000
684#define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN__SHIFT 0x14
685#define UVD_RBC_RB_CNTL__RB_NO_UPDATE_MASK 0x1000000
686#define UVD_RBC_RB_CNTL__RB_NO_UPDATE__SHIFT 0x18
687#define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x10000000
688#define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1c
689#define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xffffffff
690#define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x0
691#define UVD_STATUS__RBC_BUSY_MASK 0x1
692#define UVD_STATUS__RBC_BUSY__SHIFT 0x0
693#define UVD_STATUS__VCPU_REPORT_MASK 0xfe
694#define UVD_STATUS__VCPU_REPORT__SHIFT 0x1
695#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT_MASK 0x1
696#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x0
697#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT_MASK 0x2
698#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT__SHIFT 0x1
699#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT_MASK 0x4
700#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x2
701#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR_MASK 0x8
702#define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR__SHIFT 0x3
703#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN_MASK 0x1
704#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN__SHIFT 0x0
705#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT_MASK 0x1ffffe
706#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT__SHIFT 0x1
707#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x7000000
708#define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18
709#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN_MASK 0x1
710#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN__SHIFT 0x0
711#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT_MASK 0x1ffffe
712#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT__SHIFT 0x1
713#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x7000000
714#define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18
715#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN_MASK 0x1
716#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN__SHIFT 0x0
717#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT_MASK 0x1ffffe
718#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT__SHIFT 0x1
719#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x7000000
720#define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18
721#define UVD_CONTEXT_ID__CONTEXT_ID_MASK 0xffffffff
722#define UVD_CONTEXT_ID__CONTEXT_ID__SHIFT 0x0
723#define UVD_SUVD_CGC_GATE__SRE_MASK 0x1
724#define UVD_SUVD_CGC_GATE__SRE__SHIFT 0x0
725#define UVD_SUVD_CGC_GATE__SIT_MASK 0x2
726#define UVD_SUVD_CGC_GATE__SIT__SHIFT 0x1
727#define UVD_SUVD_CGC_GATE__SMP_MASK 0x4
728#define UVD_SUVD_CGC_GATE__SMP__SHIFT 0x2
729#define UVD_SUVD_CGC_GATE__SCM_MASK 0x8
730#define UVD_SUVD_CGC_GATE__SCM__SHIFT 0x3
731#define UVD_SUVD_CGC_GATE__SDB_MASK 0x10
732#define UVD_SUVD_CGC_GATE__SDB__SHIFT 0x4
733#define UVD_SUVD_CGC_GATE__SRE_H264_MASK 0x20
734#define UVD_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5
735#define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 0x40
736#define UVD_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6
737#define UVD_SUVD_CGC_GATE__SIT_H264_MASK 0x80
738#define UVD_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7
739#define UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 0x100
740#define UVD_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8
741#define UVD_SUVD_CGC_GATE__SCM_H264_MASK 0x200
742#define UVD_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9
743#define UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 0x400
744#define UVD_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa
745#define UVD_SUVD_CGC_GATE__SDB_H264_MASK 0x800
746#define UVD_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb
747#define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 0x1000
748#define UVD_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc
749#define UVD_SUVD_CGC_GATE__SCLR_MASK 0x2000
750#define UVD_SUVD_CGC_GATE__SCLR__SHIFT 0xd
751#define UVD_SUVD_CGC_GATE__UVD_SC_MASK 0x4000
752#define UVD_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe
753#define UVD_SUVD_CGC_STATUS__SRE_VCLK_MASK 0x1
754#define UVD_SUVD_CGC_STATUS__SRE_VCLK__SHIFT 0x0
755#define UVD_SUVD_CGC_STATUS__SRE_DCLK_MASK 0x2
756#define UVD_SUVD_CGC_STATUS__SRE_DCLK__SHIFT 0x1
757#define UVD_SUVD_CGC_STATUS__SIT_DCLK_MASK 0x4
758#define UVD_SUVD_CGC_STATUS__SIT_DCLK__SHIFT 0x2
759#define UVD_SUVD_CGC_STATUS__SMP_DCLK_MASK 0x8
760#define UVD_SUVD_CGC_STATUS__SMP_DCLK__SHIFT 0x3
761#define UVD_SUVD_CGC_STATUS__SCM_DCLK_MASK 0x10
762#define UVD_SUVD_CGC_STATUS__SCM_DCLK__SHIFT 0x4
763#define UVD_SUVD_CGC_STATUS__SDB_DCLK_MASK 0x20
764#define UVD_SUVD_CGC_STATUS__SDB_DCLK__SHIFT 0x5
765#define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK_MASK 0x40
766#define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT 0x6
767#define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK_MASK 0x80
768#define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK__SHIFT 0x7
769#define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK_MASK 0x100
770#define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK__SHIFT 0x8
771#define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK_MASK 0x200
772#define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK__SHIFT 0x9
773#define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK_MASK 0x400
774#define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK__SHIFT 0xa
775#define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK_MASK 0x800
776#define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK__SHIFT 0xb
777#define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK_MASK 0x1000
778#define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK__SHIFT 0xc
779#define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK_MASK 0x2000
780#define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK__SHIFT 0xd
781#define UVD_SUVD_CGC_STATUS__SCLR_DCLK_MASK 0x4000
782#define UVD_SUVD_CGC_STATUS__SCLR_DCLK__SHIFT 0xe
783#define UVD_SUVD_CGC_STATUS__UVD_SC_MASK 0x8000
784#define UVD_SUVD_CGC_STATUS__UVD_SC__SHIFT 0xf
785#define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 0x1
786#define UVD_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0
787#define UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 0x2
788#define UVD_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1
789#define UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 0x4
790#define UVD_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2
791#define UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 0x8
792#define UVD_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3
793#define UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 0x10
794#define UVD_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4
795#define UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x20
796#define UVD_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5
797#define UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x40
798#define UVD_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6
799#define UVD_LMI_VMID_INTERNAL__VCPU_NC0_VMID_MASK 0xf
800#define UVD_LMI_VMID_INTERNAL__VCPU_NC0_VMID__SHIFT 0x0
801#define UVD_LMI_VMID_INTERNAL__VCPU_NC1_VMID_MASK 0xf0
802#define UVD_LMI_VMID_INTERNAL__VCPU_NC1_VMID__SHIFT 0x4
803#define UVD_LMI_VMID_INTERNAL__DPB_VMID_MASK 0xf00
804#define UVD_LMI_VMID_INTERNAL__DPB_VMID__SHIFT 0x8
805#define UVD_LMI_VMID_INTERNAL__DBW_VMID_MASK 0xf000
806#define UVD_LMI_VMID_INTERNAL__DBW_VMID__SHIFT 0xc
807#define UVD_LMI_VMID_INTERNAL__LBSI_VMID_MASK 0xf0000
808#define UVD_LMI_VMID_INTERNAL__LBSI_VMID__SHIFT 0x10
809#define UVD_LMI_VMID_INTERNAL__IDCT_VMID_MASK 0xf00000
810#define UVD_LMI_VMID_INTERNAL__IDCT_VMID__SHIFT 0x14
811#define UVD_LMI_VMID_INTERNAL__JPEG_VMID_MASK 0xf000000
812#define UVD_LMI_VMID_INTERNAL__JPEG_VMID__SHIFT 0x18
813#define UVD_LMI_VMID_INTERNAL__JPEG2_VMID_MASK 0xf0000000
814#define UVD_LMI_VMID_INTERNAL__JPEG2_VMID__SHIFT 0x1c
815#define UVD_LMI_VMID_INTERNAL2__MIF_GPGPU_VMID_MASK 0xf
816#define UVD_LMI_VMID_INTERNAL2__MIF_GPGPU_VMID__SHIFT 0x0
817#define UVD_LMI_VMID_INTERNAL2__MIF_CURR_VMID_MASK 0xf0
818#define UVD_LMI_VMID_INTERNAL2__MIF_CURR_VMID__SHIFT 0x4
819#define UVD_LMI_VMID_INTERNAL2__MIF_REF_VMID_MASK 0xf00
820#define UVD_LMI_VMID_INTERNAL2__MIF_REF_VMID__SHIFT 0x8
821#define UVD_LMI_VMID_INTERNAL2__MIF_DBW_VMID_MASK 0xf000
822#define UVD_LMI_VMID_INTERNAL2__MIF_DBW_VMID__SHIFT 0xc
823#define UVD_LMI_VMID_INTERNAL2__MIF_CM_COLOC_VMID_MASK 0xf0000
824#define UVD_LMI_VMID_INTERNAL2__MIF_CM_COLOC_VMID__SHIFT 0x10
825#define UVD_LMI_VMID_INTERNAL2__MIF_BSD_VMID_MASK 0xf00000
826#define UVD_LMI_VMID_INTERNAL2__MIF_BSD_VMID__SHIFT 0x14
827#define UVD_LMI_VMID_INTERNAL2__MIF_BSP_VMID_MASK 0xf000000
828#define UVD_LMI_VMID_INTERNAL2__MIF_BSP_VMID__SHIFT 0x18
829#define UVD_LMI_VMID_INTERNAL2__VDMA_VMID_MASK 0xf0000000
830#define UVD_LMI_VMID_INTERNAL2__VDMA_VMID__SHIFT 0x1c
831#define UVD_LMI_CACHE_CTRL__IT_EN_MASK 0x1
832#define UVD_LMI_CACHE_CTRL__IT_EN__SHIFT 0x0
833#define UVD_LMI_CACHE_CTRL__IT_FLUSH_MASK 0x2
834#define UVD_LMI_CACHE_CTRL__IT_FLUSH__SHIFT 0x1
835#define UVD_LMI_CACHE_CTRL__CM_EN_MASK 0x4
836#define UVD_LMI_CACHE_CTRL__CM_EN__SHIFT 0x2
837#define UVD_LMI_CACHE_CTRL__CM_FLUSH_MASK 0x8
838#define UVD_LMI_CACHE_CTRL__CM_FLUSH__SHIFT 0x3
839#define UVD_LMI_CACHE_CTRL__VCPU_EN_MASK 0x10
840#define UVD_LMI_CACHE_CTRL__VCPU_EN__SHIFT 0x4
841#define UVD_LMI_CACHE_CTRL__VCPU_FLUSH_MASK 0x20
842#define UVD_LMI_CACHE_CTRL__VCPU_FLUSH__SHIFT 0x5
843#define UVD_LMI_SWAP_CNTL2__SCPU_R_MC_SWAP_MASK 0x3
844#define UVD_LMI_SWAP_CNTL2__SCPU_R_MC_SWAP__SHIFT 0x0
845#define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP_MASK 0xc
846#define UVD_LMI_SWAP_CNTL2__SCPU_W_MC_SWAP__SHIFT 0x2
847#define UVD_LMI_ADDR_EXT2__SCPU_ADDR_EXT_MASK 0xf
848#define UVD_LMI_ADDR_EXT2__SCPU_ADDR_EXT__SHIFT 0x0
849#define UVD_LMI_ADDR_EXT2__SCPU_VM_ADDR_EXT_MASK 0xf0
850#define UVD_LMI_ADDR_EXT2__SCPU_VM_ADDR_EXT__SHIFT 0x4
851#define UVD_LMI_ADDR_EXT2__SCPU_NC0_ADDR_EXT_MASK 0xf00
852#define UVD_LMI_ADDR_EXT2__SCPU_NC0_ADDR_EXT__SHIFT 0x8
853#define UVD_LMI_ADDR_EXT2__SCPU_NC1_ADDR_EXT_MASK 0xf000
854#define UVD_LMI_ADDR_EXT2__SCPU_NC1_ADDR_EXT__SHIFT 0xc
855#define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN_MASK 0x1
856#define UVD_CGC_MEM_CTRL__LMI_MC_LS_EN__SHIFT 0x0
857#define UVD_CGC_MEM_CTRL__MPC_LS_EN_MASK 0x2
858#define UVD_CGC_MEM_CTRL__MPC_LS_EN__SHIFT 0x1
859#define UVD_CGC_MEM_CTRL__MPRD_LS_EN_MASK 0x4
860#define UVD_CGC_MEM_CTRL__MPRD_LS_EN__SHIFT 0x2
861#define UVD_CGC_MEM_CTRL__WCB_LS_EN_MASK 0x8
862#define UVD_CGC_MEM_CTRL__WCB_LS_EN__SHIFT 0x3
863#define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN_MASK 0x10
864#define UVD_CGC_MEM_CTRL__UDEC_RE_LS_EN__SHIFT 0x4
865#define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN_MASK 0x20
866#define UVD_CGC_MEM_CTRL__UDEC_CM_LS_EN__SHIFT 0x5
867#define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN_MASK 0x40
868#define UVD_CGC_MEM_CTRL__UDEC_IT_LS_EN__SHIFT 0x6
869#define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN_MASK 0x80
870#define UVD_CGC_MEM_CTRL__UDEC_DB_LS_EN__SHIFT 0x7
871#define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN_MASK 0x100
872#define UVD_CGC_MEM_CTRL__UDEC_MP_LS_EN__SHIFT 0x8
873#define UVD_CGC_MEM_CTRL__SYS_LS_EN_MASK 0x200
874#define UVD_CGC_MEM_CTRL__SYS_LS_EN__SHIFT 0x9
875#define UVD_CGC_MEM_CTRL__VCPU_LS_EN_MASK 0x400
876#define UVD_CGC_MEM_CTRL__VCPU_LS_EN__SHIFT 0xa
877#define UVD_CGC_MEM_CTRL__SCPU_LS_EN_MASK 0x800
878#define UVD_CGC_MEM_CTRL__SCPU_LS_EN__SHIFT 0xb
879#define UVD_CGC_MEM_CTRL__MIF_LS_EN_MASK 0x1000
880#define UVD_CGC_MEM_CTRL__MIF_LS_EN__SHIFT 0xc
881#define UVD_CGC_MEM_CTRL__LCM_LS_EN_MASK 0x2000
882#define UVD_CGC_MEM_CTRL__LCM_LS_EN__SHIFT 0xd
883#define UVD_CGC_MEM_CTRL__JPEG_LS_EN_MASK 0x4000
884#define UVD_CGC_MEM_CTRL__JPEG_LS_EN__SHIFT 0xe
885#define UVD_CGC_MEM_CTRL__JPEG2_LS_EN_MASK 0x8000
886#define UVD_CGC_MEM_CTRL__JPEG2_LS_EN__SHIFT 0xf
887#define UVD_CGC_MEM_CTRL__LS_SET_DELAY_MASK 0xf0000
888#define UVD_CGC_MEM_CTRL__LS_SET_DELAY__SHIFT 0x10
889#define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY_MASK 0xf00000
890#define UVD_CGC_MEM_CTRL__LS_CLEAR_DELAY__SHIFT 0x14
891#define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK 0x1
892#define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN__SHIFT 0x0
893#define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK 0x2
894#define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN__SHIFT 0x1
895#define UVD_CGC_CTRL2__GATER_DIV_ID_MASK 0x1c
896#define UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT 0x2
897#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_RD0_VMID_MASK 0xf
898#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_RD0_VMID__SHIFT 0x0
899#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_RD1_VMID_MASK 0xf0
900#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_RD1_VMID__SHIFT 0x4
901#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_WR0_VMID_MASK 0xf00
902#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_WR0_VMID__SHIFT 0x8
903#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_WR1_VMID_MASK 0xf000
904#define UVD_LMI_VMID_INTERNAL3__MIF_GEN_WR1_VMID__SHIFT 0xc
905#define UVD_LMI_VMID_INTERNAL3__MIF_SCLR_VMID_MASK 0xf0000
906#define UVD_LMI_VMID_INTERNAL3__MIF_SCLR_VMID__SHIFT 0x10
907#define UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK 0xff
908#define UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR__SHIFT 0x0
909#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN_MASK 0x100
910#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_DOWN__SHIFT 0x8
911#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP_MASK 0x200
912#define UVD_PGFSM_CONFIG__UVD_PGFSM_POWER_UP__SHIFT 0x9
913#define UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT_MASK 0x400
914#define UVD_PGFSM_CONFIG__UVD_PGFSM_P1_SELECT__SHIFT 0xa
915#define UVD_PGFSM_CONFIG__UVD_PGFSM_P2_SELECT_MASK 0x800
916#define UVD_PGFSM_CONFIG__UVD_PGFSM_P2_SELECT__SHIFT 0xb
917#define UVD_PGFSM_CONFIG__UVD_PGFSM_WRITE_MASK 0x1000
918#define UVD_PGFSM_CONFIG__UVD_PGFSM_WRITE__SHIFT 0xc
919#define UVD_PGFSM_CONFIG__UVD_PGFSM_READ_MASK 0x2000
920#define UVD_PGFSM_CONFIG__UVD_PGFSM_READ__SHIFT 0xd
921#define UVD_PGFSM_CONFIG__UVD_PGFSM_REG_ADDR_MASK 0xf0000000
922#define UVD_PGFSM_CONFIG__UVD_PGFSM_REG_ADDR__SHIFT 0x1c
923#define UVD_PGFSM_READ_TILE1__UVD_PGFSM_READ_TILE1_VALUE_MASK 0xffffff
924#define UVD_PGFSM_READ_TILE1__UVD_PGFSM_READ_TILE1_VALUE__SHIFT 0x0
925#define UVD_PGFSM_READ_TILE2__UVD_PGFSM_READ_TILE2_VALUE_MASK 0xffffff
926#define UVD_PGFSM_READ_TILE2__UVD_PGFSM_READ_TILE2_VALUE__SHIFT 0x0
927#define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x3
928#define UVD_POWER_STATUS__UVD_POWER_STATUS__SHIFT 0x0
929#define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x4
930#define UVD_POWER_STATUS__UVD_PG_MODE__SHIFT 0x2
931#define UVD_POWER_STATUS__UVD_STATUS_CHECK_TIMEOUT_MASK 0x8
932#define UVD_POWER_STATUS__UVD_STATUS_CHECK_TIMEOUT__SHIFT 0x3
933#define UVD_POWER_STATUS__PWR_ON_CHECK_TIMEOUT_MASK 0x10
934#define UVD_POWER_STATUS__PWR_ON_CHECK_TIMEOUT__SHIFT 0x4
935#define UVD_POWER_STATUS__PWR_OFF_CHECK_TIMEOUT_MASK 0x20
936#define UVD_POWER_STATUS__PWR_OFF_CHECK_TIMEOUT__SHIFT 0x5
937#define UVD_POWER_STATUS__UVD_PGFSM_TIMEOUT_MODE_MASK 0xc0
938#define UVD_POWER_STATUS__UVD_PGFSM_TIMEOUT_MODE__SHIFT 0x6
939#define UVD_POWER_STATUS__UVD_PG_EN_MASK 0x100
940#define UVD_POWER_STATUS__UVD_PG_EN__SHIFT 0x8
941#define UVD_POWER_STATUS__PAUSE_DPG_REQ_MASK 0x200
942#define UVD_POWER_STATUS__PAUSE_DPG_REQ__SHIFT 0x9
943#define UVD_POWER_STATUS__PAUSE_DPG_ACK_MASK 0x400
944#define UVD_POWER_STATUS__PAUSE_DPG_ACK__SHIFT 0xa
945#define UVD_PGFSM_READ_TILE3__UVD_PGFSM_READ_TILE3_VALUE_MASK 0xffffff
946#define UVD_PGFSM_READ_TILE3__UVD_PGFSM_READ_TILE3_VALUE__SHIFT 0x0
947#define UVD_PGFSM_READ_TILE4__UVD_PGFSM_READ_TILE4_VALUE_MASK 0xffffff
948#define UVD_PGFSM_READ_TILE4__UVD_PGFSM_READ_TILE4_VALUE__SHIFT 0x0
949#define UVD_PGFSM_READ_TILE5__UVD_PGFSM_READ_TILE5_VALUE_MASK 0xffffff
950#define UVD_PGFSM_READ_TILE5__UVD_PGFSM_READ_TILE5_VALUE__SHIFT 0x0
951#define UVD_PGFSM_READ_TILE6__UVD_PGFSM_READ_TILE6_VALUE_MASK 0xffffff
952#define UVD_PGFSM_READ_TILE6__UVD_PGFSM_READ_TILE6_VALUE__SHIFT 0x0
953#define UVD_PGFSM_READ_TILE7__UVD_PGFSM_READ_TILE7_VALUE_MASK 0xffffff
954#define UVD_PGFSM_READ_TILE7__UVD_PGFSM_READ_TILE7_VALUE__SHIFT 0x0
955#define UVD_MIF_CURR_ADDR_CONFIG__NUM_PIPES_MASK 0x7
956#define UVD_MIF_CURR_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
957#define UVD_MIF_CURR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
958#define UVD_MIF_CURR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
959#define UVD_MIF_CURR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
960#define UVD_MIF_CURR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
961#define UVD_MIF_CURR_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
962#define UVD_MIF_CURR_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
963#define UVD_MIF_CURR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
964#define UVD_MIF_CURR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
965#define UVD_MIF_CURR_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
966#define UVD_MIF_CURR_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
967#define UVD_MIF_CURR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
968#define UVD_MIF_CURR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
969#define UVD_MIF_CURR_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
970#define UVD_MIF_CURR_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
971#define UVD_MIF_CURR_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
972#define UVD_MIF_CURR_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
973#define UVD_MIF_REF_ADDR_CONFIG__NUM_PIPES_MASK 0x7
974#define UVD_MIF_REF_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
975#define UVD_MIF_REF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
976#define UVD_MIF_REF_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
977#define UVD_MIF_REF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
978#define UVD_MIF_REF_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
979#define UVD_MIF_REF_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
980#define UVD_MIF_REF_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
981#define UVD_MIF_REF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
982#define UVD_MIF_REF_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
983#define UVD_MIF_REF_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
984#define UVD_MIF_REF_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
985#define UVD_MIF_REF_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
986#define UVD_MIF_REF_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
987#define UVD_MIF_REF_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
988#define UVD_MIF_REF_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
989#define UVD_MIF_REF_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
990#define UVD_MIF_REF_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
991#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_PIPES_MASK 0x7
992#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
993#define UVD_MIF_RECON1_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
994#define UVD_MIF_RECON1_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
995#define UVD_MIF_RECON1_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
996#define UVD_MIF_RECON1_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
997#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
998#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
999#define UVD_MIF_RECON1_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
1000#define UVD_MIF_RECON1_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
1001#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
1002#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
1003#define UVD_MIF_RECON1_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
1004#define UVD_MIF_RECON1_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
1005#define UVD_MIF_RECON1_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
1006#define UVD_MIF_RECON1_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
1007#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
1008#define UVD_MIF_RECON1_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
1009#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_PIPES_MASK 0x7
1010#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
1011#define UVD_MIF_SCLR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
1012#define UVD_MIF_SCLR_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
1013#define UVD_MIF_SCLR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
1014#define UVD_MIF_SCLR_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
1015#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
1016#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
1017#define UVD_MIF_SCLR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
1018#define UVD_MIF_SCLR_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
1019#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
1020#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
1021#define UVD_MIF_SCLR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
1022#define UVD_MIF_SCLR_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
1023#define UVD_MIF_SCLR_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
1024#define UVD_MIF_SCLR_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
1025#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
1026#define UVD_MIF_SCLR_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
1027#define UVD_JPEG_ADDR_CONFIG__NUM_PIPES_MASK 0x7
1028#define UVD_JPEG_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0
1029#define UVD_JPEG_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x70
1030#define UVD_JPEG_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x4
1031#define UVD_JPEG_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x700
1032#define UVD_JPEG_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8
1033#define UVD_JPEG_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x3000
1034#define UVD_JPEG_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0xc
1035#define UVD_JPEG_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x70000
1036#define UVD_JPEG_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10
1037#define UVD_JPEG_ADDR_CONFIG__NUM_GPUS_MASK 0x700000
1038#define UVD_JPEG_ADDR_CONFIG__NUM_GPUS__SHIFT 0x14
1039#define UVD_JPEG_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x3000000
1040#define UVD_JPEG_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18
1041#define UVD_JPEG_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000
1042#define UVD_JPEG_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c
1043#define UVD_JPEG_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000
1044#define UVD_JPEG_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e
1045
1046#endif /* UVD_5_0_SH_MASK_H */
generated by cgit v1.2.2 (git 2.25.0) at 2026-04-28 05:57:56 -0400