diff options
| author | David S. Miller <davem@davemloft.net> | 2016-07-06 13:35:22 -0400 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2016-07-06 13:35:22 -0400 |
| commit | 30d0844bdcea9fb8b0b3c8abfa5547bc3bcf8baa (patch) | |
| tree | 87302af9e03ee50cf135cc9ce6589f41fe3b3db1 /drivers/gpu/drm/amd/amdgpu | |
| parent | ae3e4562e2ce0149a4424c994a282955700711e7 (diff) | |
| parent | bc86765181aa26cc9afcb0a6f9f253cbb1186f26 (diff) | |
Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
Conflicts:
drivers/net/ethernet/mellanox/mlx5/core/en.h
drivers/net/ethernet/mellanox/mlx5/core/en_main.c
drivers/net/usb/r8152.c
All three conflicts were overlapping changes.
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 4 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 3 |
2 files changed, 7 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c index e19520c4b4b6..d9c88d13f8db 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | |||
| @@ -1106,6 +1106,10 @@ static void amdgpu_uvd_idle_work_handler(struct work_struct *work) | |||
| 1106 | if (fences == 0 && handles == 0) { | 1106 | if (fences == 0 && handles == 0) { |
| 1107 | if (adev->pm.dpm_enabled) { | 1107 | if (adev->pm.dpm_enabled) { |
| 1108 | amdgpu_dpm_enable_uvd(adev, false); | 1108 | amdgpu_dpm_enable_uvd(adev, false); |
| 1109 | /* just work around for uvd clock remain high even | ||
| 1110 | * when uvd dpm disabled on Polaris10 */ | ||
| 1111 | if (adev->asic_type == CHIP_POLARIS10) | ||
| 1112 | amdgpu_asic_set_uvd_clocks(adev, 0, 0); | ||
| 1109 | } else { | 1113 | } else { |
| 1110 | amdgpu_asic_set_uvd_clocks(adev, 0, 0); | 1114 | amdgpu_asic_set_uvd_clocks(adev, 0, 0); |
| 1111 | } | 1115 | } |
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 1a5cbaff1e34..b2ebd4fef6cf 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | |||
| @@ -47,6 +47,8 @@ | |||
| 47 | #include "dce/dce_10_0_d.h" | 47 | #include "dce/dce_10_0_d.h" |
| 48 | #include "dce/dce_10_0_sh_mask.h" | 48 | #include "dce/dce_10_0_sh_mask.h" |
| 49 | 49 | ||
| 50 | #include "smu/smu_7_1_3_d.h" | ||
| 51 | |||
| 50 | #define GFX8_NUM_GFX_RINGS 1 | 52 | #define GFX8_NUM_GFX_RINGS 1 |
| 51 | #define GFX8_NUM_COMPUTE_RINGS 8 | 53 | #define GFX8_NUM_COMPUTE_RINGS 8 |
| 52 | 54 | ||
| @@ -693,6 +695,7 @@ static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev) | |||
| 693 | amdgpu_program_register_sequence(adev, | 695 | amdgpu_program_register_sequence(adev, |
| 694 | polaris10_golden_common_all, | 696 | polaris10_golden_common_all, |
| 695 | (const u32)ARRAY_SIZE(polaris10_golden_common_all)); | 697 | (const u32)ARRAY_SIZE(polaris10_golden_common_all)); |
| 698 | WREG32_SMC(ixCG_ACLK_CNTL, 0x0000001C); | ||
| 696 | break; | 699 | break; |
| 697 | case CHIP_CARRIZO: | 700 | case CHIP_CARRIZO: |
| 698 | amdgpu_program_register_sequence(adev, | 701 | amdgpu_program_register_sequence(adev, |
