diff options
| author | Nava kishore Manne <nava.manne@xilinx.com> | 2016-09-23 07:26:58 -0400 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2016-09-23 09:26:20 -0400 |
| commit | e3296f19c8620a9c47b6734df84c4b3126d2fe46 (patch) | |
| tree | f0b2663c695cdf0031c137e3840dbb20b9c47b97 /drivers/gpio | |
| parent | 81d3753d9ea540c38b906399822a963e3b44a045 (diff) | |
gpio: Added zynq specific check for special pins on bank zero
This patch adds zynq specific check for bank 0 pins 7 and 8
are special and cannot be used as inputs
Signed-off-by: Nava kishore Manne <navam@xilinx.com>
Reported-by: Jonas Karlsson <Jonas.d.karlsson@gmail.com>
Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/gpio')
| -rw-r--r-- | drivers/gpio/gpio-zynq.c | 15 |
1 files changed, 13 insertions, 2 deletions
diff --git a/drivers/gpio/gpio-zynq.c b/drivers/gpio/gpio-zynq.c index e72794e463aa..6b4d10d6e10f 100644 --- a/drivers/gpio/gpio-zynq.c +++ b/drivers/gpio/gpio-zynq.c | |||
| @@ -96,6 +96,9 @@ | |||
| 96 | /* GPIO upper 16 bit mask */ | 96 | /* GPIO upper 16 bit mask */ |
| 97 | #define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000 | 97 | #define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000 |
| 98 | 98 | ||
| 99 | /* For GPIO quirks */ | ||
| 100 | #define ZYNQ_GPIO_QUIRK_FOO BIT(0) | ||
| 101 | |||
| 99 | /** | 102 | /** |
| 100 | * struct zynq_gpio - gpio device private data structure | 103 | * struct zynq_gpio - gpio device private data structure |
| 101 | * @chip: instance of the gpio_chip | 104 | * @chip: instance of the gpio_chip |
| @@ -122,6 +125,7 @@ struct zynq_gpio { | |||
| 122 | */ | 125 | */ |
| 123 | struct zynq_platform_data { | 126 | struct zynq_platform_data { |
| 124 | const char *label; | 127 | const char *label; |
| 128 | u32 quirks; | ||
| 125 | u16 ngpio; | 129 | u16 ngpio; |
| 126 | int max_bank; | 130 | int max_bank; |
| 127 | int bank_min[ZYNQMP_GPIO_MAX_BANK]; | 131 | int bank_min[ZYNQMP_GPIO_MAX_BANK]; |
| @@ -238,13 +242,19 @@ static void zynq_gpio_set_value(struct gpio_chip *chip, unsigned int pin, | |||
| 238 | static int zynq_gpio_dir_in(struct gpio_chip *chip, unsigned int pin) | 242 | static int zynq_gpio_dir_in(struct gpio_chip *chip, unsigned int pin) |
| 239 | { | 243 | { |
| 240 | u32 reg; | 244 | u32 reg; |
| 245 | bool is_zynq_gpio; | ||
| 241 | unsigned int bank_num, bank_pin_num; | 246 | unsigned int bank_num, bank_pin_num; |
| 242 | struct zynq_gpio *gpio = gpiochip_get_data(chip); | 247 | struct zynq_gpio *gpio = gpiochip_get_data(chip); |
| 243 | 248 | ||
| 249 | is_zynq_gpio = gpio->p_data->quirks & ZYNQ_GPIO_QUIRK_FOO; | ||
| 244 | zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio); | 250 | zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio); |
| 245 | 251 | ||
| 246 | /* bank 0 pins 7 and 8 are special and cannot be used as inputs */ | 252 | /* |
| 247 | if (bank_num == 0 && (bank_pin_num == 7 || bank_pin_num == 8)) | 253 | * On zynq bank 0 pins 7 and 8 are special and cannot be used |
| 254 | * as inputs. | ||
| 255 | */ | ||
| 256 | if (is_zynq_gpio && bank_num == 0 && | ||
| 257 | (bank_pin_num == 7 || bank_pin_num == 8)) | ||
| 248 | return -EINVAL; | 258 | return -EINVAL; |
| 249 | 259 | ||
| 250 | /* clear the bit in direction mode reg to set the pin as input */ | 260 | /* clear the bit in direction mode reg to set the pin as input */ |
| @@ -627,6 +637,7 @@ static const struct zynq_platform_data zynqmp_gpio_def = { | |||
| 627 | 637 | ||
| 628 | static const struct zynq_platform_data zynq_gpio_def = { | 638 | static const struct zynq_platform_data zynq_gpio_def = { |
| 629 | .label = "zynq_gpio", | 639 | .label = "zynq_gpio", |
| 640 | .quirks = ZYNQ_GPIO_QUIRK_FOO, | ||
| 630 | .ngpio = ZYNQ_GPIO_NR_GPIOS, | 641 | .ngpio = ZYNQ_GPIO_NR_GPIOS, |
| 631 | .max_bank = ZYNQ_GPIO_MAX_BANK, | 642 | .max_bank = ZYNQ_GPIO_MAX_BANK, |
| 632 | .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(), | 643 | .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(), |
